Circuit Optimization

1. © Copyright AgO Inc 20111
Circuit Synthesis Optimization
www.ago-inc.comHillol.Sarkar@ago-inc.com

2. © Copyright AgO Inc 20112
100X Faster Simulation and Six Sigma Optimization

3. © Copyright AgO Inc 20113
Challenges in Analog & RF Design
Respin avoidance
• Analog circuits are responsible for ~ 50% of IC design re-spins
• Re-spins can mean missing market windows and unbudgeted costs
Achieving design specification
• Meeting or beating performance while minimising cost of implementation
• Managing greater complexity in operating and power saving modes
Maximising yield
• Validating greater numbers of process, voltage and temperature corners
• Efficiently centering design across all PVT corners using Monte Carlo
Design porting
• Moving existing circuit designs to similar technologies
• Re-centering design to meet constraints of new technology

4. © Copyright AgO Inc 20114
Classic Analog Design Methodology
• Design methodology has changed little over the years
• Manual, iterative design with many SPICE runs
Define topology
&
resize devices
Physical layout
& adjust
Extraction
Layout verification
Design
specification &
constraints
Spice
Spice

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Optimization StrategyOptimization Strategy
Description
• DC Operation
• Increase Margin
• Quick check
• Best Design Space
Description
• Single Corner
• Meet performance
• Monte Carlo
• Ready for Center
Description
• All Corners
• Rapid Size
• Ready for P&R
Description
• Conflict
• Change Priority
• System Analysis
AgO Optimization Strategy

6. © Copyright AgO Inc 20116
AnXplorer Goals
• Quickly size W/L a circuit in a given technology
• Explore suitability of different design options
• Robust design over PVT & Monte Carlo
• Support all types of devices
• Explore results using database
• Optimize production yield

7. © Copyright AgO Inc 20117
AgO Design Methodology
AnXplorer automates device sizing
Define topology
Physical layout
& adjust
Extraction
Layout verification
Design
specification &
constraints
Feasibility
Global
Centering

8. © Copyright AgO Inc 20118
Porting of Existing Circuits
Vendor X
Vendor Y
Common challenge
• Port existing design in technology X (say
180 nm) to technology Y (in 180 nm)
• Ensure that original design goals are met
AnXplorer approach
• Start with original sized circuit
• Define variable ranges for target circuit
• “One click” command
• Optimises and centers with new PVT
corners
Same Node
Porting

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Prioritized Design Objectives
• Most tools support a weight-based prioritization
for multiple objectives
– Designer is often unsure of relative weights
• AnXplorer supports hierarchical design objectives
– User defines relative priority of different objectives
• AnXplorer achieves important objectives before
optimizing others

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Implicit Objectives Correct by
Construction
• Imposes implicit objectives on
conditions of devices at DC
operating point
• Customizable objectives
• Detects common sub-circuits and
imposes constraints on their
operating conditions
• Ensures a robust DC operating
point
• Feature only available for MOS
devices
Examples of sub-
circuits:
• transistors in
saturation
• transistors in
linear region
• current mirrors
• level shifters
• differential pairs
• voltage reference
• current mirror
banks
• etc

11. © Copyright AgO Inc 201111
Core Optimization Technology
Early Optimisation tools
• Frequently relied on traditional
convex/gradient methods
• These are known to have difficulty
with multiple local minima
AnXplorer
• Based on Evolutionary algorithm
• Capable of finding global minimum in
presence of many local minima
• Successfully optimised tough tests
e.g. Rastrigin’s function
• Optional logarithmic partitioning of
design space
Supports both simulation-based
optimization & equation-based
optimization

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Multiple Local Minimum

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Trade-off Analysis
• Finds multiple design points satisfying design
objectives
• Creates exploration database for post-
optimization analysis
– Database stores all explored design points
– Query language or GUI
• Useful for trade-off analysis with conflicting
objectives
• Useful for “what-if” analysis

14. © Copyright AgO Inc 201114
Industry Standard Formats
AnXplorer
Design objectives
Un-sized circuit
Schematics
Sized and centered
net list
Exploration
database for
Trade off analysis
Definition of
Design variables
Compatible with existing design flows

15. © Copyright AgO Inc 201115
Design Environment
• Spice Simulators
Silvaco SmartSpice
Cadence Spectre
Synopsys Spice Simulators
Mentor Eldo
Multi-threading support
• Operating system
Red Hat RHEL 5

16. © Copyright AgO Inc 201116
Silvaco
• Accurate circuit simulation
• 100% HSPICE and SPECTRE compatible Netlists
• Single event effect reliability analysis
• A leader in run-time simulation speed
• Largest collection of Spice Models

17. © Copyright AgO Inc 201117
Competitive Differentiation
• One product, four optimization steps
• Robust Centering to maximize yield –Monte Carlo
• Implicit objectives for stable DC operation
• Hierarchical design objectives
• User can perform trade-off analysis
• Industry standard formats and simulators
• Core based on Evolutionary Algorithm

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Monte Carlo Design for Six Sigma
DFSS Company