AnXplorer  New generation Analog & RF Circuit Optimization Roddy Urquhart [email_address] Hillol Sarkar [email_address]
Agenda <ul><li>Company background </li></ul><ul><li>Challenges in analog/RF design </li></ul><ul><li>Introducing AnXplorer...
Company Background <ul><li>Founded by expert CAD developers Dr Partha Ray and Dr Tathagato Rai Dastidar in 2007 </li></ul>...
Agenda <ul><li>Company background </li></ul><ul><li>Challenges in analog/RF design </li></ul><ul><li>Introducing AnXplorer...
Analog & RF ICs are Everywhere <ul><li>Analog and RF circuits are key to many systems </li></ul><ul><ul><li>Mobile communi...
Analog Design is Expensive <ul><li>Analog circuits are  </li></ul><ul><ul><li>~2% of total transistor count </li></ul></ul...
… and worse in smaller process nodes <ul><li>Costs of an analog design increase with finer geometries </li></ul><ul><ul><l...
Elimination of Re-spins is Key Challenge Source: Jim Hogan, “Escape from analog Alcatraz”, DAC 2006 Interoperability Break...
Agenda <ul><li>Company background </li></ul><ul><li>Challenges in analog/RF design </li></ul><ul><li>Introducing AnXplorer...
Classic Analog Design Methodology <ul><li>Design methodology has changed little over the years </li></ul><ul><li>Manual, i...
AgO Design Methodology <ul><li>AnXplorer automates device resizing and SPICE runs </li></ul>Define topology  Physical layo...
AnXplorer uses industry standard inputs Compatible with existing design flows Generates optimized and centred netlist that...
AnXplorer +Solido Variation-Aware Design  Compatible with existing design flows Generates optimized and centred net list t...
Working with existing environments <ul><li>Supported simulators </li></ul><ul><ul><li>Cadence Spectre  </li></ul></ul><ul>...
Optimization Approach <ul><li>Two stage optimization approach </li></ul><ul><ul><li>Global optimization using single corne...
Multi-Algorithmic Optimization Approach <ul><li>Multi-algorithmic strategy controlled by expert system </li></ul><ul><li>D...
Tough Optimization Problems Tackled <ul><li>Especially with smaller geometries circuit optimisation problems are not well-...
Cost Graph <ul><li>Objectives are prioritized in importance </li></ul><ul><li>There is no need for weights </li></ul><ul><...
Equation-Based Optimization <ul><li>AnXplorer has different modes of operation </li></ul><ul><ul><li>Graphical mode </li><...
AgO Optimisation Benefits <ul><li>Productivity improvement </li></ul><ul><ul><li>Engineering efficiency should be improved...
AgO Power Op Amp Optimization Results in 9 Hours Parameters Spec Optimized W/L DC Gain  > 80 db 94 db Bandwidth  > 500MHz ...
<ul><li>Increased DC Gain by 17.5 % </li></ul><ul><li>Increased Unity Gain Bandwidth by 83 % </li></ul><ul><li>Increased P...
<ul><li>GUI support </li></ul><ul><li>Query language support </li></ul><ul><li>Updated every 2 iterations </li></ul><ul><l...
Agenda <ul><li>Company background </li></ul><ul><li>Challenges in analog/RF design </li></ul><ul><li>Introducing AnXplorer...
Conclusion <ul><li>Analog and RF design is rapidly growing </li></ul><ul><li>Risk of respin remains high with predominantl...
AnXplorer  New generation Analog & RF Circuit Optimization Roddy Urquhart [email_address] Hillol Sarkar [email_address]
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Ag o product overview

  1. 1. AnXplorer New generation Analog & RF Circuit Optimization Roddy Urquhart [email_address] Hillol Sarkar [email_address]
  2. 2. Agenda <ul><li>Company background </li></ul><ul><li>Challenges in analog/RF design </li></ul><ul><li>Introducing AnXplorer </li></ul><ul><li>AnXplorer Optimization </li></ul><ul><li>Conclusion </li></ul>2
  3. 3. Company Background <ul><li>Founded by expert CAD developers Dr Partha Ray and Dr Tathagato Rai Dastidar in 2007 </li></ul><ul><li>Founders previously in senior CAD development positions at National Semiconductor </li></ul><ul><ul><li>Strong track record in 8 patent awards and 15 research papers published </li></ul></ul><ul><li>Headquarters established in Silicon Valley under AgO brand in 2009 </li></ul><ul><li>Worldwide sales channel established in Q1 2010 </li></ul>3
  4. 4. Agenda <ul><li>Company background </li></ul><ul><li>Challenges in analog/RF design </li></ul><ul><li>Introducing AnXplorer </li></ul><ul><li>AnXplorer Optimization </li></ul><ul><li>Conclusion </li></ul>4
  5. 5. Analog & RF ICs are Everywhere <ul><li>Analog and RF circuits are key to many systems </li></ul><ul><ul><li>Mobile communications (GSM, CDMA,WiMax, LTE) </li></ul></ul><ul><ul><li>Short-range communications (WiFi, ZigBee) </li></ul></ul><ul><ul><li>Automotive (Control systems, auto informatics) </li></ul></ul><ul><ul><li>Consumer audio and video </li></ul></ul><ul><ul><li>High speed I/O (Serdes, tranceivers, LVDS) </li></ul></ul><ul><ul><li>Medical and Bio-informatics </li></ul></ul><ul><li>Analog/mixed-signal is growing at 13% CAGR </li></ul><ul><ul><li>Semiconductors as a whole only at 10% </li></ul></ul>5
  6. 6. Analog Design is Expensive <ul><li>Analog circuits are </li></ul><ul><ul><li>~2% of total transistor count </li></ul></ul><ul><ul><li>20% of total IC area </li></ul></ul><ul><ul><li>40% of total design effort </li></ul></ul><ul><ul><li>Responsible for 50% of design respins </li></ul></ul><ul><li>Analog design requires specialist skills </li></ul><ul><ul><li>Analog designers are in short supply </li></ul></ul><ul><ul><li>Design automation for analog lags that for digital design </li></ul></ul><ul><ul><li>Tasks are labour intensive </li></ul></ul>6
  7. 7. … and worse in smaller process nodes <ul><li>Costs of an analog design increase with finer geometries </li></ul><ul><ul><li>Design cost per IC cited as going from ~$4M with 0.18 µm to ~$46M with 65 nm </li></ul></ul><ul><ul><li>More complexity through algorithmic architectures </li></ul></ul><ul><ul><ul><li>ΣΔ and randomisation </li></ul></ul></ul><ul><ul><ul><li>Auto calibration, correction and adaptation </li></ul></ul></ul><ul><ul><ul><li>More digital controls </li></ul></ul></ul><ul><ul><li>More complexity because of complex modes </li></ul></ul><ul><ul><ul><li>End application modes </li></ul></ul></ul><ul><ul><ul><li>Power saving modes </li></ul></ul></ul><ul><ul><ul><li>Circuit operation modes </li></ul></ul></ul><ul><ul><li>Calibration and tuning for process variability </li></ul></ul>Source: Jim Hogan, “Escape from analog Alcatraz”, DAC 2006 Interoperability Breakfast 7
  8. 8. Elimination of Re-spins is Key Challenge Source: Jim Hogan, “Escape from analog Alcatraz”, DAC 2006 Interoperability Breakfast 6-9 months 10-15 months 0 Time 1 st TO 1 2 3 4 Final TO Respins Design to product specification coverage 100% gap Respins not only bring unbudgeted costs but can delay projects enough to lose profitability. Often only the 1 st and 2 nd to market are the only players to profit. 2 nd challenge is to close the design gap faster 8
  9. 9. Agenda <ul><li>Company background </li></ul><ul><li>Challenges in analog/RF design </li></ul><ul><li>Introducing AnXplorer </li></ul><ul><li>AnXplorer Optimization </li></ul><ul><li>Conclusion </li></ul>9
  10. 10. Classic Analog Design Methodology <ul><li>Design methodology has changed little over the years </li></ul><ul><li>Manual, iterative design with many SPICE runs </li></ul>Define topology & resize devices Physical layout & adjust Extraction Layout verification Design specification & constraints Spice Spice 10
  11. 11. AgO Design Methodology <ul><li>AnXplorer automates device resizing and SPICE runs </li></ul>Define topology Physical layout & adjust Extraction Layout verification Design specification & constraints Spice 11 Optimization Centering AnXplorer
  12. 12. AnXplorer uses industry standard inputs Compatible with existing design flows Generates optimized and centred netlist that meets or exceeds objectives 12 AnXplorer Design objectives Un-sized circuit Schematics Sized and centered netlist Exploration database for tradeoff analysis Definition of Design variables
  13. 13. AnXplorer +Solido Variation-Aware Design Compatible with existing design flows Generates optimized and centred net list that meets or exceeds objectives 12 AnXplorer Cadence Multi-mode Simulation Un-sized circuit Schematics Sized and centered Net list Exploration database for Trade-off analysis Solido Variation Designer
  14. 14. Working with existing environments <ul><li>Supported simulators </li></ul><ul><ul><li>Cadence Spectre </li></ul></ul><ul><ul><li>Synopsys HSpice </li></ul></ul><ul><ul><li>Legend Design Technology MSim </li></ul></ul><ul><ul><li>Mentor Eldo </li></ul></ul><ul><li>Multi-threading support </li></ul><ul><li>Operating system </li></ul><ul><ul><li>Red Hat Enterprise Linux 4 </li></ul></ul>13
  15. 15. Optimization Approach <ul><li>Two stage optimization approach </li></ul><ul><ul><li>Global optimization using single corner </li></ul></ul><ul><ul><li>Local centering using all corners </li></ul></ul><ul><li>Simulation- and equation-based optimization supported </li></ul><ul><li>Hierarchical design objectives </li></ul><ul><li>Trade off analysis with exploration database </li></ul><ul><li>Multi-threading support </li></ul>14 Optimization Centering AnXplorer
  16. 16. Multi-Algorithmic Optimization Approach <ul><li>Multi-algorithmic strategy controlled by expert system </li></ul><ul><li>Device rules stored in knowledge base to ensure safe DC operation </li></ul><ul><ul><li>Intelligent handling of devices in saturation or linear </li></ul></ul><ul><ul><li>Recognition of current mirrors, level shifters, etc. </li></ul></ul><ul><li>Designer know-how used in objectives and constraints </li></ul>
  17. 17. Tough Optimization Problems Tackled <ul><li>Especially with smaller geometries circuit optimisation problems are not well-behaved and have multiple local minima </li></ul><ul><li>Many existing optimisation tools use convex or gradient optimisation </li></ul><ul><li>AnXplorer has successfully found the global minimum in the presence of many local minima for tough benchmarks such as Rastigin’s function </li></ul>
  18. 18. Cost Graph <ul><li>Objectives are prioritized in importance </li></ul><ul><li>There is no need for weights </li></ul><ul><li>Below settling time has high priority </li></ul>
  19. 19. Equation-Based Optimization <ul><li>AnXplorer has different modes of operation </li></ul><ul><ul><li>Graphical mode </li></ul></ul><ul><ul><ul><li>Simulation-based optimisation </li></ul></ul></ul><ul><ul><li>Command line mode </li></ul></ul><ul><ul><ul><li>Simulation-based optimisation </li></ul></ul></ul><ul><ul><ul><li>Equation-base optimisation </li></ul></ul></ul><ul><li>Equation-based approach supports early design exploration </li></ul><ul><ul><li>Analog systems can be described by parameterised functions </li></ul></ul><ul><ul><li>AnXplorer can optimise arbitrary functions </li></ul></ul><ul><ul><li>Functions defined in standard C </li></ul></ul>
  20. 20. AgO Optimisation Benefits <ul><li>Productivity improvement </li></ul><ul><ul><li>Engineering efficiency should be improved by at least 5 × </li></ul></ul><ul><ul><li>Highly manual and iterative sizing of circuit elements is automated </li></ul></ul><ul><ul><li>Enables experienced staff to focus on choosing circuit topologies </li></ul></ul><ul><li>Yield improvement/respin avoidance </li></ul><ul><ul><li>Robust centering of design to meet objectives </li></ul></ul><ul><ul><li>Covers variation in process, temperature and voltage </li></ul></ul><ul><li>Simpler porting to new process nodes </li></ul><ul><ul><li>Circuit resizing is key element in porting an analog circuit </li></ul></ul><ul><ul><li>Automation significantly reduces the time required </li></ul></ul>18
  21. 21. AgO Power Op Amp Optimization Results in 9 Hours Parameters Spec Optimized W/L DC Gain > 80 db 94 db Bandwidth > 500MHz 915 MHz Phase Margin > 60 Deg 64 Deg Power < 25 mA 18 mA Settling Time < 10 nsec 3 nsec
  22. 22. <ul><li>Increased DC Gain by 17.5 % </li></ul><ul><li>Increased Unity Gain Bandwidth by 83 % </li></ul><ul><li>Increased Phase Margin by 6.7 % </li></ul><ul><li>Reduced Settling Time by 70 % </li></ul><ul><li>Decreased Current Consumption by 28 % </li></ul>High Gain OpAmp Test Case Summary
  23. 23. <ul><li>GUI support </li></ul><ul><li>Query language support </li></ul><ul><li>Updated every 2 iterations </li></ul><ul><li>GUI has 2 options </li></ul><ul><ul><li>Load global data base </li></ul></ul><ul><ul><li>Load centered data base </li></ul></ul><ul><li>Query definition </li></ul><ul><li>Data base results </li></ul><ul><li>Wizard entry for optimization criteria </li></ul>AgO Data Base
  24. 24. Agenda <ul><li>Company background </li></ul><ul><li>Challenges in analog/RF design </li></ul><ul><li>Introducing AnXplorer </li></ul><ul><li>AnXplorer Optimization </li></ul><ul><li>Conclusion </li></ul>25
  25. 25. Conclusion <ul><li>Analog and RF design is rapidly growing </li></ul><ul><li>Risk of respin remains high with predominantly manual design process </li></ul><ul><li>AnXplorer can automate key manual optimization and simulation activities </li></ul><ul><li>High performance optimizer produces designs meeting objectives and constraints </li></ul><ul><li>Benefits </li></ul><ul><ul><li>Design team productivity </li></ul></ul><ul><ul><li>Yield improvement </li></ul></ul><ul><ul><li>Reduced respins </li></ul></ul>26
  26. 26. AnXplorer New generation Analog & RF Circuit Optimization Roddy Urquhart [email_address] Hillol Sarkar [email_address]

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