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AnXplorer  New generation Analog & RF Circuit Optimization Roddy Urquhart [email_address] Hillol Sarkar [email_address]
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object],2
Company Background ,[object Object],[object Object],[object Object],[object Object],[object Object],3
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object],4
Analog & RF ICs are Everywhere ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],5
Analog Design is Expensive ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],6
… and worse in smaller process nodes ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Source: Jim Hogan, “Escape from analog Alcatraz”, DAC 2006 Interoperability Breakfast 7
Elimination of Re-spins is Key Challenge Source: Jim Hogan, “Escape from analog Alcatraz”, DAC 2006 Interoperability Breakfast 6-9 months 10-15 months 0 Time   1 st  TO  1  2  3  4  Final TO Respins Design to product  specification coverage 100% gap Respins not only bring unbudgeted costs but can delay projects enough to lose profitability. Often only the 1 st  and 2 nd  to market are the only players to profit. 2 nd  challenge is to close the design  gap faster 8
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object],9
Classic Analog Design Methodology ,[object Object],[object Object],Define topology & resize devices Physical layout & adjust Extraction Layout verification Design specification & constraints Spice Spice 10
AgO Design Methodology ,[object Object],Define topology  Physical layout & adjust Extraction Layout verification Design specification & constraints Spice 11 Optimization Centering AnXplorer
AnXplorer uses industry standard inputs Compatible with existing design flows Generates optimized and centred netlist that meets or exceeds objectives 12 AnXplorer Design objectives  Un-sized circuit  Schematics  Sized and centered netlist  Exploration  database for tradeoff analysis  Definition of  Design variables
AnXplorer +Solido Variation-Aware Design  Compatible with existing design flows Generates optimized and centred net list that meets or exceeds objectives 12 AnXplorer Cadence Multi-mode  Simulation Un-sized circuit  Schematics  Sized and centered Net list  Exploration  database for Trade-off analysis  Solido Variation  Designer
Working with existing environments ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],13
Optimization Approach ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],14 Optimization Centering AnXplorer
Multi-Algorithmic Optimization Approach ,[object Object],[object Object],[object Object],[object Object],[object Object]
Tough Optimization Problems Tackled ,[object Object],[object Object],[object Object]
Cost Graph ,[object Object],[object Object],[object Object]
Equation-Based Optimization ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
AgO Optimisation Benefits ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],18
AgO Power Op Amp Optimization Results in 9 Hours Parameters Spec Optimized W/L DC Gain  > 80 db 94 db Bandwidth  > 500MHz 915 MHz Phase Margin  > 60 Deg 64 Deg Power < 25 mA 18 mA Settling Time < 10 nsec 3 nsec
[object Object],[object Object],[object Object],[object Object],[object Object],High Gain OpAmp Test Case Summary
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],AgO Data Base
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object],25
Conclusion ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],26
AnXplorer  New generation Analog & RF Circuit Optimization Roddy Urquhart [email_address] Hillol Sarkar [email_address]

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Ag o product overview

  • 1. AnXplorer New generation Analog & RF Circuit Optimization Roddy Urquhart [email_address] Hillol Sarkar [email_address]
  • 2.
  • 3.
  • 4.
  • 5.
  • 6.
  • 7.
  • 8. Elimination of Re-spins is Key Challenge Source: Jim Hogan, “Escape from analog Alcatraz”, DAC 2006 Interoperability Breakfast 6-9 months 10-15 months 0 Time 1 st TO 1 2 3 4 Final TO Respins Design to product specification coverage 100% gap Respins not only bring unbudgeted costs but can delay projects enough to lose profitability. Often only the 1 st and 2 nd to market are the only players to profit. 2 nd challenge is to close the design gap faster 8
  • 9.
  • 10.
  • 11.
  • 12. AnXplorer uses industry standard inputs Compatible with existing design flows Generates optimized and centred netlist that meets or exceeds objectives 12 AnXplorer Design objectives Un-sized circuit Schematics Sized and centered netlist Exploration database for tradeoff analysis Definition of Design variables
  • 13. AnXplorer +Solido Variation-Aware Design Compatible with existing design flows Generates optimized and centred net list that meets or exceeds objectives 12 AnXplorer Cadence Multi-mode Simulation Un-sized circuit Schematics Sized and centered Net list Exploration database for Trade-off analysis Solido Variation Designer
  • 14.
  • 15.
  • 16.
  • 17.
  • 18.
  • 19.
  • 20.
  • 21. AgO Power Op Amp Optimization Results in 9 Hours Parameters Spec Optimized W/L DC Gain > 80 db 94 db Bandwidth > 500MHz 915 MHz Phase Margin > 60 Deg 64 Deg Power < 25 mA 18 mA Settling Time < 10 nsec 3 nsec
  • 22.
  • 23.
  • 24.
  • 25.
  • 26. AnXplorer New generation Analog & RF Circuit Optimization Roddy Urquhart [email_address] Hillol Sarkar [email_address]