This document describes software for 2D block scaling and rotation control. It includes a top level function for scaling and rotating images and describes the dependencies and sub-functions. It focuses on vertical block scaling control, explaining how it determines the number of vertical blocks, initializes starting/ending rows for input/output blocks, and adjusts these values based on scaling factors and scan direction.
The document describes an algorithm for block-scaling control during vertical resizing of images. It involves dividing the target image into vertical blocks, and computing the corresponding input blocks based on the scaling ratio and scan direction. For each target block, it determines the start and end rows of the corresponding input block. It also tracks the start rows of subsequent blocks to account for cases where a block maps to a whole number of input rows. This ensures accurate mapping between input and output blocks during upscaling and downscaling in both vertical up and down scan directions.
This document discusses executing a Simulink model externally from MATLAB via the MATLAB external interface. It provides examples of executing a Simulink model from the MATLAB command line, from a C program, from FORTRAN, and from the Modular Modeling System (MMS). The examples demonstrate preserving Simulink state information when executing a model over an extended simulation by passing the final states of one interval as the initial states of the next. This allows interfacing a Simulink control model with detailed systems models in codes like TRACE or MMS.
M.G.Goman et al (1994) - PII package: Brief descriptionProject KRIT
М.Г.Гоман и другие, краткое описание пакета программ интерактивной идентификации PII, 1998 г., Центральный Аэрогидродинамический институт, г. Жуковский, 1998 г.
M.G.Goman et al, "PII - Programs of Interactive Identification. Brief description", Central Aerohydrodynamics Institute (TsAGI), Zhukovsky, Russia, 1998.
this presentation will help u with understanding basic elements of the bloc diagram and how to reduce multi loop block diagram with some suitable numerical example.
This document discusses block diagram representation. It begins by defining a block diagram as a pictorial representation of the cause-and-effect relationship of a system. Block diagrams show the components, direction of information flow with arrows, and can describe the function of each block. Block diagrams are useful for analyzing and designing control systems, but do not provide unique representations or show the physical construction or energy sources of a system. The document also discusses techniques for reducing block diagrams, such as combining or moving blocks.
This document provides an overview of block diagram representations of control systems. It discusses how block diagrams can be used to represent the input-output relationships of system elements and operations like addition and subtraction. Examples are given of drawing block diagrams from mathematical equations and reducing complex block diagrams to canonical form through techniques like combining blocks in series/parallel and eliminating feedback loops. The document also covers how block diagrams can represent multi-input, multi-output systems and provides an example block diagram of an armature-controlled DC motor system.
This document describes a video color processing algorithm that aims to improve color accuracy and image quality on mobile devices. It discusses developing algorithms to enable color enhancements without distortions, adapting to viewing conditions like ambient light, and accurately reproducing colors on wide gamut displays. The algorithm uses the CIECAM02 perceptual color model and involves offline computation of various parameters to transform color spaces and enable color and contrast processing.
The 2D composition engine provides the following key capabilities in 3 sentences or less:
It performs 2D graphics operations like block copy, rotation, scaling, color space conversion, alpha blending, and ROP operations. It supports various image formats and color spaces. The architecture includes a core processing unit with functional blocks for scaling, rotation, Porter-Duff compositing, and ROP, and it interfaces with external memory and clients through a VPDMA unit.
The document describes an algorithm for block-scaling control during vertical resizing of images. It involves dividing the target image into vertical blocks, and computing the corresponding input blocks based on the scaling ratio and scan direction. For each target block, it determines the start and end rows of the corresponding input block. It also tracks the start rows of subsequent blocks to account for cases where a block maps to a whole number of input rows. This ensures accurate mapping between input and output blocks during upscaling and downscaling in both vertical up and down scan directions.
This document discusses executing a Simulink model externally from MATLAB via the MATLAB external interface. It provides examples of executing a Simulink model from the MATLAB command line, from a C program, from FORTRAN, and from the Modular Modeling System (MMS). The examples demonstrate preserving Simulink state information when executing a model over an extended simulation by passing the final states of one interval as the initial states of the next. This allows interfacing a Simulink control model with detailed systems models in codes like TRACE or MMS.
M.G.Goman et al (1994) - PII package: Brief descriptionProject KRIT
М.Г.Гоман и другие, краткое описание пакета программ интерактивной идентификации PII, 1998 г., Центральный Аэрогидродинамический институт, г. Жуковский, 1998 г.
M.G.Goman et al, "PII - Programs of Interactive Identification. Brief description", Central Aerohydrodynamics Institute (TsAGI), Zhukovsky, Russia, 1998.
this presentation will help u with understanding basic elements of the bloc diagram and how to reduce multi loop block diagram with some suitable numerical example.
This document discusses block diagram representation. It begins by defining a block diagram as a pictorial representation of the cause-and-effect relationship of a system. Block diagrams show the components, direction of information flow with arrows, and can describe the function of each block. Block diagrams are useful for analyzing and designing control systems, but do not provide unique representations or show the physical construction or energy sources of a system. The document also discusses techniques for reducing block diagrams, such as combining or moving blocks.
This document provides an overview of block diagram representations of control systems. It discusses how block diagrams can be used to represent the input-output relationships of system elements and operations like addition and subtraction. Examples are given of drawing block diagrams from mathematical equations and reducing complex block diagrams to canonical form through techniques like combining blocks in series/parallel and eliminating feedback loops. The document also covers how block diagrams can represent multi-input, multi-output systems and provides an example block diagram of an armature-controlled DC motor system.
This document describes a video color processing algorithm that aims to improve color accuracy and image quality on mobile devices. It discusses developing algorithms to enable color enhancements without distortions, adapting to viewing conditions like ambient light, and accurately reproducing colors on wide gamut displays. The algorithm uses the CIECAM02 perceptual color model and involves offline computation of various parameters to transform color spaces and enable color and contrast processing.
The 2D composition engine provides the following key capabilities in 3 sentences or less:
It performs 2D graphics operations like block copy, rotation, scaling, color space conversion, alpha blending, and ROP operations. It supports various image formats and color spaces. The architecture includes a core processing unit with functional blocks for scaling, rotation, Porter-Duff compositing, and ROP, and it interfaces with external memory and clients through a VPDMA unit.
La Unión Europea ha propuesto un nuevo paquete de sanciones contra Rusia que incluye un embargo al petróleo ruso. El embargo se aplicaría gradualmente durante seis meses para el petróleo crudo y ocho meses para los productos refinados. El objetivo es aumentar la presión sobre Rusia para que ponga fin a su invasión de Ucrania.
The document compares the 2DBitBlt resampling scaler architecture to other scaling architectures. 2DBitBlt resampling uses a hardware efficient algorithm adapted from image warping with weighted resampling and no power of 2 limitation. It performs anti-aliasing as part of the algorithm and has potential for parallel processing. Charts show 2DBitBlt resampling outperforming polyphase and bicubic scaling in terms of aliasing, while being simpler with a single line buffer. While images may be softer than bicubic, it has advantages of guaranteed anti-aliasing and better performance for higher decimation ranges.
The document describes a video noise reduction system that uses an adaptive recursive filter. It averages a portion of the input frame with a delayed frame to reduce noise while preserving edges and details where there is no motion. The amount of noise reduction depends on the number of frames averaged and a parameter k that adapts to the average noise level. It also uses adaptive coring thresholds based on measured noise levels to determine whether pixels are filtered, bypassing the filter for large differences likely due to motion rather than noise. The system architecture includes components for YC separation, noise measurement, filtering, and output formatting. Performance results show improved noise reduction over time as more frames are averaged while minimizing ghosting artifacts from motion.
Dokumen tersebut memberikan informasi tentang blog, termasuk definisi, fungsi, dan langkah-langkah membuat blog. Blog didefinisikan sebagai kumpulan website pribadi yang memungkinkan penulisnya menampilkan berbagai jenis konten secara mudah. Fungsi blog dapat berupa media satu arah, dua arah, atau berbagai arah untuk tujuan tertentu seperti informasi dan promosi. Langkah-langkah membuat blog meliputi membuat ak
This document describes a speed-up technique for a Windows image scalar algorithm. It involves detecting when an output pixel generation cycle will be immediately followed by an input pixel consumption cycle. In this case, the cycles can be merged to improve performance. Specifically:
- During an output cycle, the algorithm checks if the remaining input fragment after subtracting the output fragment is less than the inverse scale factor.
- If so, the input pixel is fully consumed in this merged cycle. The accumulator is updated, the output pixel is produced, and a new input pixel is fetched.
- This avoids retaining the input pixel for an extra cycle and improves efficiency, especially for decimation cases where an input pixel often contributes to multiple
The document analyzes the performance of single BLT (bit blit) operations for clearing blackness on images of varying heights from 100 to 600 pixels. It finds that the total time for BLT operations increases linearly with image height. On average, each BLT operation takes approximately 1.35 3D GPU clocks or 12.3 nanoseconds per pixel, with some variation depending on the image height.
The document discusses color processing using the CIECAM02 color appearance model. It begins with an agenda that covers challenges, color spaces like RGB, XYZ, LMS, and CIECAM02. It then explains CIECAM02 and its inverse, how they model human color perception and account for viewing conditions. The document discusses color processing techniques like contrast enhancement, saturation adjustment, hue manipulation, and gamut mapping to handle out-of-gamut colors. It aims to perform color processing and management across the color reproduction chain from capture to display in a perceptually accurate manner.
This document discusses architectural synthesis of DSP structured datapaths. It provides an overview of the architectural level synthesis problem and subtasks like scheduling, binding, and architecture optimization. The document describes using novel mathematical programming formulations to optimize performance and structural complexity for DSP synthesis. It also discusses techniques to improve the solution time for integer linear programming formulations, and provides results for typical high-level synthesis benchmarks.
The document describes the Mismatch Noise Cancellation (MNC) architecture. The key components of the MNC architecture are:
1. A pseudo-random number generator that generates random binary sequences.
2. A mismatch estimation block that estimates mismatches.
3. A noise cancellation block that corrects the effects of mismatches.
4. Synchronization elements that synchronize data flow.
This document is a thesis submitted by Shereef B. M. Shehata to Concordia University in 1997 for the degree of Doctor of Philosophy in Electrical and Computer Engineering. The thesis proposes a technique for high level synthesis of digital signal processing cores targeting field programmable gate arrays (FPGAs). The technique aims to optimize the total execution time of the synthesized architecture using integer linear programming while accounting for the structural characteristics of FPGAs early in the synthesis process. This includes optimizing interconnect usage and estimating system clock duration.
MP3 Audio Decoding involves perceptual audio encoding using psychoacoustic analysis and quantization. It uses a filter bank to split audio into 32 subbands and a hybrid filter bank combining MDCT and traditional filter banks. Quantization and encoding involves bit allocation across scalefactor bands based on masking thresholds from the psychoacoustic model. The decoder reconstructs audio using inverse quantization and filtering.
Inertial sensors use a mass-spring system where a proof mass is suspended by a spring and responds to input forces. The displacement of the mass is measured to sense the force. Forces can be applied through electrostatic transduction. Capacitive sensing is commonly used to measure the displacement of the mass. The system acts as a second-order dynamical system where the input force is transduced to mass displacement which is then transduced to an output charge. Key parameters that impact sensor performance include the transduction gain and damping forces.
Gyroscope sensors measure angular velocity by detecting the Coriolis effect on a vibrating mass. They have specifications including measurement range, number of sensing axes, nonlinearity, temperature range, and noise parameters. MEMS gyroscopes typically use a vibrating proof mass driven electrostatically while rotation is detected via sense electrodes measuring the Coriolis-induced deflection perpendicular to the drive mode. The Coriolis effect causes an apparent deflection in a rotating reference frame due to inertial forces.
The document describes an assignment to implement an A* search algorithm to solve 8-puzzle and its variations. It involves creating Board and Solver classes with specified APIs to represent game boards and find the minimum moves solution. The A* search uses a priority queue and either Hamming or Manhattan heuristics to efficiently find the optimal solution if the board is solvable, otherwise it reports as unsolvable. Sample inputs and outputs are provided to test the implementation.
This document provides a reference guide for vision functions in OpenVX 1.1, listing functions for common image processing tasks like filtering, feature detection, arithmetic operations on images, and more. Each function is described briefly, noting input/output image formats and data types for parameters. The guide is intended to help developers working with the OpenVX API to select appropriate functions and understand their parameters and data formats.
The document describes various computer vision functions available in the OpenVX API. Some key functions include:
1. Arithmetic functions like addition, subtraction, and convolution to perform basic image operations.
2. Feature detection functions like Harris corners, fast corners, and Canny edge detection to detect interest points and edges.
3. Filtering functions like box filtering, Gaussian filtering, and non-linear filtering to preprocess images.
4. Morphological functions like erosion, dilation, opening and closing for tasks like noise removal.
Parameters include images of various data formats as input and output. Functions are available in both immediate and graph modes to provide flexibility in implementation.
This document describes gate level modeling in Verilog. It discusses gate types like AND, OR, and NOT gates that can be used as primitives. It describes how to instantiate gates and provides examples of instantiating gates like NAND and AND gates. It also describes structural modeling of circuits like a 2-input multiplexer, full adder, D latch, and master-slave JK flip-flop using gate level primitives.
This document discusses two-dimensional geometric transformations in computer graphics. It begins by introducing basic 2D transformations including translation, rotation, scaling, reflection, and shearing. It then explains how homogeneous coordinates can be used to represent all geometric transformations as matrix multiplications. The first transformation discussed in detail is translation, which repositions an object by adding translation distances tx and ty to the original x and y coordinates.
La Unión Europea ha propuesto un nuevo paquete de sanciones contra Rusia que incluye un embargo al petróleo ruso. El embargo se aplicaría gradualmente durante seis meses para el petróleo crudo y ocho meses para los productos refinados. El objetivo es aumentar la presión sobre Rusia para que ponga fin a su invasión de Ucrania.
The document compares the 2DBitBlt resampling scaler architecture to other scaling architectures. 2DBitBlt resampling uses a hardware efficient algorithm adapted from image warping with weighted resampling and no power of 2 limitation. It performs anti-aliasing as part of the algorithm and has potential for parallel processing. Charts show 2DBitBlt resampling outperforming polyphase and bicubic scaling in terms of aliasing, while being simpler with a single line buffer. While images may be softer than bicubic, it has advantages of guaranteed anti-aliasing and better performance for higher decimation ranges.
The document describes a video noise reduction system that uses an adaptive recursive filter. It averages a portion of the input frame with a delayed frame to reduce noise while preserving edges and details where there is no motion. The amount of noise reduction depends on the number of frames averaged and a parameter k that adapts to the average noise level. It also uses adaptive coring thresholds based on measured noise levels to determine whether pixels are filtered, bypassing the filter for large differences likely due to motion rather than noise. The system architecture includes components for YC separation, noise measurement, filtering, and output formatting. Performance results show improved noise reduction over time as more frames are averaged while minimizing ghosting artifacts from motion.
Dokumen tersebut memberikan informasi tentang blog, termasuk definisi, fungsi, dan langkah-langkah membuat blog. Blog didefinisikan sebagai kumpulan website pribadi yang memungkinkan penulisnya menampilkan berbagai jenis konten secara mudah. Fungsi blog dapat berupa media satu arah, dua arah, atau berbagai arah untuk tujuan tertentu seperti informasi dan promosi. Langkah-langkah membuat blog meliputi membuat ak
This document describes a speed-up technique for a Windows image scalar algorithm. It involves detecting when an output pixel generation cycle will be immediately followed by an input pixel consumption cycle. In this case, the cycles can be merged to improve performance. Specifically:
- During an output cycle, the algorithm checks if the remaining input fragment after subtracting the output fragment is less than the inverse scale factor.
- If so, the input pixel is fully consumed in this merged cycle. The accumulator is updated, the output pixel is produced, and a new input pixel is fetched.
- This avoids retaining the input pixel for an extra cycle and improves efficiency, especially for decimation cases where an input pixel often contributes to multiple
The document analyzes the performance of single BLT (bit blit) operations for clearing blackness on images of varying heights from 100 to 600 pixels. It finds that the total time for BLT operations increases linearly with image height. On average, each BLT operation takes approximately 1.35 3D GPU clocks or 12.3 nanoseconds per pixel, with some variation depending on the image height.
The document discusses color processing using the CIECAM02 color appearance model. It begins with an agenda that covers challenges, color spaces like RGB, XYZ, LMS, and CIECAM02. It then explains CIECAM02 and its inverse, how they model human color perception and account for viewing conditions. The document discusses color processing techniques like contrast enhancement, saturation adjustment, hue manipulation, and gamut mapping to handle out-of-gamut colors. It aims to perform color processing and management across the color reproduction chain from capture to display in a perceptually accurate manner.
This document discusses architectural synthesis of DSP structured datapaths. It provides an overview of the architectural level synthesis problem and subtasks like scheduling, binding, and architecture optimization. The document describes using novel mathematical programming formulations to optimize performance and structural complexity for DSP synthesis. It also discusses techniques to improve the solution time for integer linear programming formulations, and provides results for typical high-level synthesis benchmarks.
The document describes the Mismatch Noise Cancellation (MNC) architecture. The key components of the MNC architecture are:
1. A pseudo-random number generator that generates random binary sequences.
2. A mismatch estimation block that estimates mismatches.
3. A noise cancellation block that corrects the effects of mismatches.
4. Synchronization elements that synchronize data flow.
This document is a thesis submitted by Shereef B. M. Shehata to Concordia University in 1997 for the degree of Doctor of Philosophy in Electrical and Computer Engineering. The thesis proposes a technique for high level synthesis of digital signal processing cores targeting field programmable gate arrays (FPGAs). The technique aims to optimize the total execution time of the synthesized architecture using integer linear programming while accounting for the structural characteristics of FPGAs early in the synthesis process. This includes optimizing interconnect usage and estimating system clock duration.
MP3 Audio Decoding involves perceptual audio encoding using psychoacoustic analysis and quantization. It uses a filter bank to split audio into 32 subbands and a hybrid filter bank combining MDCT and traditional filter banks. Quantization and encoding involves bit allocation across scalefactor bands based on masking thresholds from the psychoacoustic model. The decoder reconstructs audio using inverse quantization and filtering.
Inertial sensors use a mass-spring system where a proof mass is suspended by a spring and responds to input forces. The displacement of the mass is measured to sense the force. Forces can be applied through electrostatic transduction. Capacitive sensing is commonly used to measure the displacement of the mass. The system acts as a second-order dynamical system where the input force is transduced to mass displacement which is then transduced to an output charge. Key parameters that impact sensor performance include the transduction gain and damping forces.
Gyroscope sensors measure angular velocity by detecting the Coriolis effect on a vibrating mass. They have specifications including measurement range, number of sensing axes, nonlinearity, temperature range, and noise parameters. MEMS gyroscopes typically use a vibrating proof mass driven electrostatically while rotation is detected via sense electrodes measuring the Coriolis-induced deflection perpendicular to the drive mode. The Coriolis effect causes an apparent deflection in a rotating reference frame due to inertial forces.
The document describes an assignment to implement an A* search algorithm to solve 8-puzzle and its variations. It involves creating Board and Solver classes with specified APIs to represent game boards and find the minimum moves solution. The A* search uses a priority queue and either Hamming or Manhattan heuristics to efficiently find the optimal solution if the board is solvable, otherwise it reports as unsolvable. Sample inputs and outputs are provided to test the implementation.
This document provides a reference guide for vision functions in OpenVX 1.1, listing functions for common image processing tasks like filtering, feature detection, arithmetic operations on images, and more. Each function is described briefly, noting input/output image formats and data types for parameters. The guide is intended to help developers working with the OpenVX API to select appropriate functions and understand their parameters and data formats.
The document describes various computer vision functions available in the OpenVX API. Some key functions include:
1. Arithmetic functions like addition, subtraction, and convolution to perform basic image operations.
2. Feature detection functions like Harris corners, fast corners, and Canny edge detection to detect interest points and edges.
3. Filtering functions like box filtering, Gaussian filtering, and non-linear filtering to preprocess images.
4. Morphological functions like erosion, dilation, opening and closing for tasks like noise removal.
Parameters include images of various data formats as input and output. Functions are available in both immediate and graph modes to provide flexibility in implementation.
This document describes gate level modeling in Verilog. It discusses gate types like AND, OR, and NOT gates that can be used as primitives. It describes how to instantiate gates and provides examples of instantiating gates like NAND and AND gates. It also describes structural modeling of circuits like a 2-input multiplexer, full adder, D latch, and master-slave JK flip-flop using gate level primitives.
This document discusses two-dimensional geometric transformations in computer graphics. It begins by introducing basic 2D transformations including translation, rotation, scaling, reflection, and shearing. It then explains how homogeneous coordinates can be used to represent all geometric transformations as matrix multiplications. The first transformation discussed in detail is translation, which repositions an object by adding translation distances tx and ty to the original x and y coordinates.
The document discusses various Java layout managers including FlowLayout, BorderLayout, CardLayout, GridLayout, and GridBagLayout. It provides details on their constructors, methods, and usage. FlowLayout is the default layout that arranges components from left to right, top to bottom. BorderLayout divides a container into five regions. CardLayout switches between panels like cards. GridLayout evenly divides space into a grid of rows and columns. GridBagLayout is more flexible than GridLayout and allows control of component size and position with GridBagConstraints.
The document discusses two-dimensional viewing and clipping techniques in computer graphics. It describes how a window defines the scene to view and a viewport defines where it is displayed. Different transformations map the window coordinates to normalized device coordinates. Clipping techniques like Cohen-Sutherland clipping and Liang-Barsky clipping are used to only display the parts of lines and polygons within the viewport boundaries. Text clipping can be done by bounding text as a whole, character-by-character, or by clipping individual character components.
The document provides reference information for various computer vision functions in the OpenVX 1.3 framework. It describes functions for common image processing tasks like filtering, feature extraction, morphology operations, and more. Each function listing includes the C-style function prototypes and brief descriptions of parameters and data types. Section numbers refer to the full OpenVX 1.3 specification.
2. Top Level Function for Scaling and rotation
• void Block_scaler_rot (regfield_struc *regfield_ptr, unsigned char
**A_in, unsigned char **R_in, unsigned char **G_in, unsigned char
**B_in, unsigned char **A_out, unsigned char **R_out, unsigned char
**G_out, unsigned char **B_out)
• This function is the top Level scale and rotate function. It is
input is the input image to be scaled and rotated. The output is
the scaled and rotated image.
4. Horizontal Scaler Control
• void horiz_scaler_control (long *H_in_Block_St_col, long
*H_in_Block_End_col, long *H_out_Block_St_col, long
*H_out_Block_End_col, int srcW, int tarW, int H_scan_dir, int
Scale_factor_h, int Inv_scale_h, int H_no_blocks)
• This function will determine the starting/ending column for each block in the
horizontal direction H_in_Block_St_col, H_in_Block_End_col for the input
image to be scaled.
• This function will also determine the starting/ending column for each block
in the horizontal direction H_out_Block_End_col, H_out_Block_End_col for
the output scaled image.
5. Block-scaling control (The notion of pixel index does not depend on the
direction of scan)
tarH
srcH
srcW tarW(H =1,V=1)
(H =1,V=tarH)
(H =tarW,V=1)
(H =1,V=srcH) (H =srcW,V=srcH)
(H =tarW,V=tarH)
(H =1,V=1) (H =srcW,V=1)
5
14. Vertical block-scaling control
out_Blk_sz_v = 32;
V_no_blocks = ceil(tarH ./out_Blk_sz_v)
Determine the vertical number of blocks
Initialize the first row of the first output vertical block based
On the direction of scan
14
15. Vertical Block-scaling control (Vertical number of blocks is the same in
the output and input)
Vert_blox_index =1
Vert_blox_index =
V_no_blocks
Vert_blox_index =1
15
16. Vertical block-scaling control
if (V_scan_dir == 1)
% Vertical scan is Down
V_in_Block_St_row(1) = 1;
V_out_Block_St_row(1) = 1;
else
% Vertical scan is Up
V_in_Block_St_row(1) = srcH;
V_out_Block_St_row(1) = tarH;
end
Initialize the Start row of the first input vertical block based
on the direction of scan
While Scaning target image pixel rows
According to the direction of scan
1<= tar_row<= (tar_H)
Initialize the Start row of the first output vertical block based
On the direction of scan
16
17. Vertical Block-scaling control (Starting vertical row of the first vertical
block for the input and output)
V_in_Block_St_row(1)
V_in_Block_St_row(1) = tarH
V_out_Block_St_row(1)
V_in_Block_St_row(1) = srcH
17
18. Vertical block-scaling control (Determine the output vertical block
boundary)
while (( V_scan_dir ==1) && tar_row <= tarH || (( V_scan_dir ==2) && tar_row >= 1 ) )
% At boundary row of an output vertical block
if ( ((V_scan_dir == 1) && (rem(tar_row,out_Blk_sz_v) == 0 )) || ...
((V_scan_dir == 2) && ( rem(((tarH-tar_row)+1), out_Blk_sz_v) == 0 )) )
While Scaning target image pixel rows
According to the direction of scan
1<= tar_row<= (tar_H)
At each vertical block boundary
of the target image
Compute the vertical block index
18
20. Vertical block-scaling control (Compute the current vertical block index
depending on the direction of scan)
% compute the current vertical block index
% Vertically Down
if (V_scan_dir == 1)
Vert_Block_Index = floor(tar_row./out_Blk_sz_v);
else
% Vertically Up
Vert_Block_Index = floor(((tarH-tar_row)+1) ./ out_Blk_sz_v);
end
At each vertical block boundary
of the target image do:
Compute the vertical block index
20
22. Vertical block-scaling control (Compute the end row of the output
vertical block)
% compute the block-end boundary of the current output vertical block
V_out_Block_End_row(Vert_Block_Index) = tar_row;
Compute the vertical block index
Compute the end row of the current output vertical block
22
23. Vertical block-scaling control (Compute the end row of the output
vertical block)
V_out_Block_End_row(1)
V_out_Block_End_row(V_no_blocks-1)
V_out_Block_End_row(V_no_blocks)=tarH
V_out_Block_End_row(V_no_blocks)=1
V_out_Block_End_row(V_no_blocks-1)
V_out_Block_End_row(1)
23
24. Vertical block-scaling control (Compute the end row of the current input
vertical block, for vertical down scan)
if(V_scan_dir ==1)
if(Inv_scale_v >= 1)
% down scaling
V_in_Block_End_row(Vert_Block_Index) = ceil(tar_row * Inv_scale_v);
else
V_in_Block_End_row(Vert_Block_Index) = ceil(tar_row * Inv_scale_v)+1;
end
if ( V_in_Block_End_row(Vert_Block_Index) > srcH)
V_in_Block_End_row(Vert_Block_Index) = srcH;
end
Compute the end row of the current output vertical block
compute the block-end boundary of the current input
vertical block (Vertical down scan)
24
25. Vertical block-scaling control (Compute the end row of the current input
vertical block, for vertical down scan) Down-Scaling
V_in_Block_End_row(1)
V_in_Block_End_row(2)
V_in_Block_End_row(V_no_blocks-1)
V_in_Block_End_row(V_no_blocks)
25
26. Vertical block-scaling control (Compute the end row of the current input
vertical block, for vertical down scan) Up-Scaling
V_in_Block_End_row(1)
V_in_Block_End_row(2)
V_in_Block_End_row(V_no_blocks-1)
V_in_Block_End_row(V_no_blocks)
26
27. Vertical block-scaling control (Compute the end row of the current input
vertical block, for vertical up scan)
else
% Vertical Up Scan
if(Inv_scale_v >= 1)
% down scaling
V_in_Block_End_row(Vert_Block_Index) = srcH - (ceil( ((tarH-tar_row)+1) * Inv_scale_v) ) + 1;
else
V_in_Block_End_row(Vert_Block_Index) = srcH - (ceil( ((tarH-tar_row)+1) * Inv_scale_v) ) ;
end
if ( V_in_Block_End_row(Vert_Block_Index) < 1)
V_in_Block_End_row(Vert_Block_Index) = 1;
end
end
Compute the end row of the current output vertical block
compute the block-end boundary of the current input
vertical block (Vertical up scan)
27
28. Vertical block-scaling control (Compute the end row of the current input
vertical block, for vertical up scan) Down-Scaling
V_in_Block_End_row(1)
V_in_Block_End_row(2)
V_in_Block_End_row(V_no_blocks-1)
V_in_Block_End_row(V_no_blocks)
28
29. Vertical block-scaling control (Compute the end row of the current input
vertical block, for vertical up scan) Up-Scaling
V_in_Block_End_row(1)
V_in_Block_End_row(2)
V_in_Block_End_row(V_no_blocks-1)
V_in_Block_End_row(V_no_blocks)
29
30. Vertical block-scaling control (Compute the start row of the next output
vertical block)
if (V_scan_dir == 1)
% Vertically Down
V_out_Block_St_row(Vert_Block_Index+1) = V_out_Block_End_row(Vert_Block_Index)+1;
if (V_out_Block_St_row(Vert_Block_Index+1) > tarH)
V_out_Block_St_row(Vert_Block_Index+1) = tarH;
end
else
% Vertically Up
V_out_Block_St_row(Vert_Block_Index+1) = V_out_Block_End_row(Vert_Block_Index)-1;
if (V_out_Block_St_row(Vert_Block_Index+1) < 1)
V_out_Block_St_row(Vert_Block_Index+1) = 1;
end
end
compute the block-end boundary of the current input
vertical block (Vertical down/up scan)
compute the block-start boundary of the next output
vertical block (Vertical down/up scan)
30
31. Vertical block-scaling control (Compute the start row of the output
vertical block)
V_out_Block_St_row(1) = 1
V_out_Block_St_row(V_no_blocks-1)
V_out_Block_St_row(V_no_blocks)
V_out_Block_St_row(V_no_blocks)
V_out_Block_St_row(V_no_blocks-1)
V_out_Block_St_row(1) = tarH
31
32. Vertical block-scaling control (Compute the start row of the next input
vertical block, for vertical down scan)
if(V_scan_dir ==1)
if(Inv_scale_v >= 1)
% down scaling
V_in_Block_St_row(Vert_Block_Index+1) = V_in_Block_End_row(Vert_Block_Index);
else
% Up scaling
V_in_Block_St_row(Vert_Block_Index+1) = V_in_Block_End_row(Vert_Block_Index)-1;
end
if (V_in_Block_St_row(Vert_Block_Index+1) > srcH)
V_in_Block_St_row(Vert_Block_Index+1) = srcH;
end
compute the block-start boundary of the current output
vertical block (Vertical down/up scan)
compute the block-start boundary of the next input
vertical block (Vertical down scan)
32
33. Vertical block-scaling control (Compute the start row of the input
vertical block, for vertical down scan) Down-Scaling
V_in_Block_St_row(1)
V_in_Block_St_row(2)
V_in_Block_St_row(V_no_blocks-1)
V_in_Block_St_row(V_no_blocks)
33
34. Vertical block-scaling control (Compute the start row of the input
vertical block, for vertical down scan) Up-Scaling
V_in_Block_St_row(1)
V_in_Block_St_row(2)
V_in_Block_St_row(V_no_blocks-1)
V_in_Block_St_row(V_no_blocks)
34
35. Vertical block-scaling control (Compute the start row of the next input
vertical block, for vertical up scan)
else
if (Inv_scale_v >= 1)
% down scale
V_in_Block_St_row(Vert_Block_Index+1) = V_in_Block_End_row(Vert_Block_Index);
else
% compute the block-start boundary of the current input vertical block
V_in_Block_St_row(Vert_Block_Index+1) = V_in_Block_End_row(Vert_Block_Index)+1;
end
if (V_in_Block_St_row(Vert_Block_Index+1) < 1)
V_in_Block_St_row(Vert_Block_Index+1) = 1;
end
end
compute the block-start boundary of the current output
vertical block (Vertical down/up scan)
compute the block-start boundary of the next input
vertical block (Vertical up scan)
35
36. Vertical block-scaling control (Compute the start row of the input
vertical block, for vertical up scan) Down-Scaling
V_in_Block_ST_row(1)
V_in_Block_St_row(2)
V_in_Block_St_row(V_no_blocks-1)
V_in_Block_St_row(V_no_blocks)
36
37. Vertical block-scaling control (Compute the start row of the input
vertical block, for vertical up scan) Up-Scaling
V_in_Block_End_row(1)
V_in_Block_End_row(2)
V_in_Block_End_row(V_no_blocks-1)
V_in_Block_End_row(V_no_blocks)
37
38. Vertical block-scaling control (Adjust the start row of the next input
vertical block, if the current input block has no vertical pixel fraction)
if (V_scan_dir == 1)
% Vertical down
if ( ( ceil(tar_row * Inv_scale_v) - (tar_row * Inv_scale_v)) == 0)
V_in_Block_St_row(Vert_Block_Index+1) = V_in_Block_St_row(Vert_Block_Index+1) + 1;
end
if (V_in_Block_St_row(Vert_Block_Index+1) > srcH)
V_in_Block_St_row(Vert_Block_Index+1) = srcH;
end
else
% Vertical Up
if ( ( (ceil( ((tarH-tar_row)+1) * Inv_scale_v) ) - ( ((tarH-tar_row)+1) * Inv_scale_v) ) == 0)
V_in_Block_St_row(Vert_Block_Index+1) = V_in_Block_St_row(Vert_Block_Index+1) - 1;
end
if (V_in_Block_St_row(Vert_Block_Index+1) < 1)
V_in_Block_St_row(Vert_Block_Index+1) = 1;
end
end
compute the block-start boundary of the current input
vertical block (Vertical down/up scan)
Adjust the block-start boundary of the current input
vertical block if the real current vertical block
ended on a pixel boundary (Vertical down/up scan)
38
39. Vertical block-scaling control (Adjust the start row of the next input vertical block, if the
current input block has no vertical pixel fraction) Vertical down scan, Down-Scaling
V_in_Block_St_row(1)
V_in_Block_St_row(2)
V_in_Block_St_row(V_no_blocks-1)
V_in_Block_St_row(V_no_blocks)
39
40. Vertical block-scaling control (Adjust the start row of the next input vertical block, if the
current input block has no vertical pixel fraction) Vertical down scan, Up-Scaling
V_in_Block_St_row(1)
V_in_Block_St_row(2)
V_in_Block_St_row(V_no_blocks-1)
V_in_Block_St_row(V_no_blocks)
40
41. Vertical block-scaling control (Adjust the start row of the next input vertical block, if the
current input block has no vertical pixel fraction) Vertical up scan, Down-Scaling
V_in_Block_ST_row(1)
V_in_Block_St_row(2)
V_in_Block_St_row(V_no_blocks-1)
V_in_Block_St_row(V_no_blocks)
41
42. Vertical block-scaling control (Adjust the start row of the next input vertical block, if the
current input block has no vertical pixel fraction) Vertical up scan, Up-Scaling
V_in_Block_ST_row(1)
V_in_Block_St_row(2)
V_in_Block_St_row(V_no_blocks-1)
V_in_Block_St_row(V_no_blocks)
42