The document outlines a syllabus for a computer systems architecture course, covering key topics like basic building blocks, memory units, and input-output architecture. It also discusses the architecture of digital computers, including the roles of hardware and software, along with descriptions of micro-operations and register transfer language. Evaluation methods for students include internal and end-semester assessments, and recommended resources for further study are provided.

1. Computer Systems Architecture
Syllabus, Evaluation and Suggested Books

2. Syllabus
• Unit-I Basic Building Blocks
• Unit-II Register Transfer and Micro Operations
• Unit-III Memory Unit
• Unit-IV Input-Output Architecture

3. Syllabus
• Unit-I Basic Building Blocks: Boolean logic and Boolean algebra,
tri-state logic; flip-flops, counters, shift registers, adders,
subtractor, encoders, decoders, multiplexors, de-multiplexors.
• Unit-II Register Transfer and Micro Operations: Bus and memory
transfers, arithmetic, logic shift micro-operations; basic
computer organization: common bus system, instruction
formats, instruction cycle, interrupt cycle, input/output
configuration, CPU organization, register organization, stack
organization, micro programmed control unit, RISC architecture;
microprocessor architecture, modern computing architectures.
• Unit-III Memory Unit: Primary memory, secondary memory,
associative memory, sequential access, direct access storage
devices.
• Unit-IV Input-Output Architecture: Input/Output devices; data
transfer schemes - programmed I/O and DMA transfer; data
transfer schemes for microprocessors.

4. Evaluation
Internal Assessment (30 Marks)
– Mid sem. Examination ≈ 15—20 marks.
– Assignment ≈ 10-- 15 Marks.
– *Test or Presentation ≈ 5 Marks.
End Sem. Examination (70 Marks)

5. Book
• Morris Mano, Computer System Architecture,
3rd Edition, Pearson

6. Introduction to Computer
Systems Architecture

7. Computer Systems Architecture
• A computer system is basically a machine that
simplifies complicated tasks.
• Computer Architecture is concern with the structure
and behaviour of the computer as seen by the user. It
includes the information, the instruction set and
techniques for addressing memory. The architectural
design of a computer system is concerned with the
specifications of the functional modules, such as
processor, memory and structuring them together
into a computer system.
“Computer Architecture is a study of computer
systems”

8. Components in the Computer System
Architecture
Input Unit, Output Unit, Storage Unit, Arithmetic Logic
Unit and Control Unit etc.

9. Broad categories
• A computer system is subdivided into two
functional entities:
• Hardware of the computer system consists of
all the electronic components and
electromechanical devices that comprise the
physical entity of the device.
• Software consists of the instructions and data
that the computer manipulates to perform
various data-processing tasks.

10. Broad categories
• Hardware of the computer system is usually divided into
three major parts.
 Input devices
 CPU (ALU,CU and Memory)
 Output devices
• Software consists of a collection of programs whose
purpose is to make more efficient use of the computer.
 Program: A set of instructions that directs a computer's
hardware to perform a task.
 Instructions are basic commands used to communicate with
the processor. A computer can execute billions of instructions
per second.

11. How Computer System Works ?
• Program – List of instructions given to the computer
• Information– data, images, files, videos
• Processor– Process the information according to the
instructions in the program
Processor
Program Information
results
11

12. Binary System & Logic Gates
• Computer is a digital device, which works on two levels of
signal. These two levels of signal as High and Low.
• Digital computers use the binary number system, which
has two digits: 0 and 1.
0 means Low
1 means High
• Manipulation of binary information is done by logic
circuits called Gates.
• Each gate has a distinct graphic symbol and its operation
can be described by means of an algebraic expression.
• Input-Output relationship of the binary variables for each
gate can be represented in tabular form by a truth table.

15. Book
• Morris Mano, Computer System Architecture,
3rd Edition, Pearson

16. Register Transfer,
Bus and Memory Transfer

17. Register Transfer Language
• Digital Computer System: interconnection of
digital hardware module that accomplish a
specific information-processing task.
• The various modules are interconnected with
common data and control paths.
• The modules are constructed from digital
components as registers, decoders, arithmetic
elements and control logic.
• Digital Module: Registers + Operations
performed on the data stored in registers.
• Micro-operations: The operations executed on
data stored in registers.

18. The result of the operation may be:
– replace the previous binary information of a
register or
– transferred to another register
• Micro-operations: Examples:- shift, count, clear and
load.
• A counter with parallel load is capable of performing
the micro-operations increment and load.
• A bidirectional shift register is capable of performing
the shift right and shift left micro-operations.
Register Transfer Language

19. • The internal hardware organization of a digital
computer is defined by specifying:
The set of registers it contains and their function.
The sequence of micro-operations performed on the
binary information stored in the registers.
The control that initiates the sequence of micro-operations
• Digital Computer = Registers +
Micro-operations Hardware +
Control Functions
Register Transfer Language

20. Register Transfer Language
• Register Transfer Language (RTL) : a symbolic
notation used to describe the micro-operation
transfers among registers.
 Define symbols for various types of micro-
operations
 Describe the hardware that implements these
micro-operations

21. Register Transfer
• Computer registers are designated by capital
letters (sometimes followed by numerals) to
denote the function of the register.
MAR: Memory Address Register (holds an
address for a memory unit)
PC: Program Counter
IR: Instruction Register
SR: Status Register
R1: Processor Register

22. • The individual flip-flops in an n-bit register are
numbered in sequence from 0 to n-1 (from the right
position toward the left position).
• Most common way to represent a register is by a
rectangular box.
• A 16 bit register can be partitioned into two parts,
low bytes and high byte.
Fig: A block diagram of a register
Register Transfer

23. • Information transfer from one register to another is
described by a replacement operator: R2 ← R1
• This statement denotes a transfer of the content of
register R1 into register R2.
• The transfer happens in one clock cycle.
• The content of the R1 (source) does not change.
• The content of the R2 (destination) will be lost and
replaced by the new data transferred from R1.
• We are assuming that the circuits are available from the
outputs of the source register to the inputs of the destination
register, and that the destination register has a parallel load
capability.
Register Transfer

24. • Conditional transfer occurs only under a control
condition
if(P=1) then (R2 ← R1)
• Representation of a (conditional) transfer
P: R2 ← R1
• A binary condition (P equals to 0 or 1) determines
when the transfer occurs.
• The content of R1 is transferred into R2 only if P is 1.
Register Transfer

25. Hardware implementation of a controlled transfer: P: R2 ← R1
Register Transfer

26. Basic Symbols for Register Transfers
Symbol Description Examples
Letters &
numerals
Denotes a register MAR, R2
Parenthesis ( ) Denotes a part of a register R2(0-7), R2(L)
Arrow ← Denotes transfer of
information
R2 ← R1
Comma , Separates two micro-
operations
R2 ← R1, R1 ← R2
Register Transfer

27. Bus and Memory Transfers
• A typical digital computer has many registers and
paths must be provided to transfer information from
one register to another.
• The number of wires will be excessive if separate
lines are used between each register and all other
registers in the system.
• Common Bus System is a scheme for transferring
information between registers in a multiple-register
configuration.
• Bus: set of common lines, one for each bit of a
register, through which binary information is
transferred one at a time.
• Control signals determine which register is selected
by the bus during each particular register transfer.

28. Bus and Memory Transfers
• One way of constructing a common bus system is
with multiplexers.
• The multiplexers select the source register whose
binary information is then placed on the bus.

29. Bus system for four registers

30. Bus and Memory Transfers
Construction of a bus system for four registers
(Example)
• Each register has four bits, numbered 0 through 3.
• The bus consists of four 4 × 1 multiplexers and two
selection inputs, S1 and S0.
• Both the selection lines are connected to the
selection inputs of all four multiplexers.
• The selection lines choose the four bits of one
register and transfer them into the four-line common
bus.

31. Bus and Memory Transfers
• In general, a bus system will multiplex k registers of n
bits each to produce an n-line common bus.
• The number of multiplexers needed to construct the
bus is equal to n, the number of bits in each register.
• The size of each multiplexer must be k x 1 since it
multiplexes k data lines.
• For example, a common bus for eight registers of 16
bits each requires 16 multiplexers, one for each line
in the bus.
• Each multiplexer must have 8 data input lines and 3
selection lines to multiplex one significant bit in 8
registers.
no. of the Registers = no. of I/P lines in Mux
size of the Register= no. of Mux = no. of bus lines

32. Bus and Memory Transfers
• A common bus system can be constructed with
three-state gates instead of multiplexers.

33. Bus and Memory Transfers:
Three-State Bus Buffers
• A bus system can be constructed with three-state
buffer gates instead of multiplexers
• A three-state buffer is a digital circuit that exhibits
three states:
o logic-0,
o logic-1, and
o high-impedance (Hi-Z)

34. Bus and Memory Transfers:
Three-State Bus Buffers
A
C=1
B
A
C=0
B
A B
Buffer
A B
Open Circuit
• Tri-state buffer has both a normal input and a control
input.
• The high-impedance state behaves like an open
circuit, which means that the output is disconnected
and does not have a logic significance.

35. Bus and Memory Transfers:
Three-State Bus Buffers

36. Bus and Memory Transfers:
Three-State Bus Buffers
• The outputs of four buffers are connected together
to form a single bus line.
• When the enable input of decoder is 0, all of its four
outputs are 0, all of its four outputs are 0, and bus
line is in a high-impedance state because all four
buffers are disabled.
• When the enable input is active, one of the three-
state buffers will be active, depending on the select
inputs of the decoder.
• Three-state gates may perform any conventional logic, such as
AND or NAND.

37. Bus and Memory Transfers:
Memory Transfer
• Memory read : Transfer from memory
• Memory write : Transfer to memory
• A memory word will be symbolized by the letter M.
• It is necessary to specify the address of M when
writing /reading memory
• This is done by enclosing the address in square
brackets following the letter M
• Example: M[0016] : the memory contents at address
0x0016

38. Bus and Memory Transfers:
Memory Transfer
• Assume that the address of a memory unit is stored
in a register called the Address Register AR
• Lets represent a Data Register with DR.
• Transfer of information into DR from the memory
word M selected by the address in AR .
Read: DR ← M[AR]
• Transfer of information from DR into the memory
word M selected by the address in AR .
Write: M[AR] ← DR

39. Arithmetic Micro-operations

40. Arithmetic Microoperations
• A microoperation is an elementary operation
performed with the data stored in registers.
• The microoperations most often encountered in digital
computers are classified into four categories:
 Register transfer microoperations (on binary
information)
 Arithmetic microoperations (on numeric data
stored in the registers)
 Logic microoperations (bit manipulations on non-
numeric data)
 Shift microoperations

41. Arithmetic Microoperations
• The basic arithmetic microoperations are: addition,
subtraction, increment, and decrement.

42. Arithmetic Microoperations
• The arithmetic microoperations change the
information content.
• Addition Microoperation:
R3 ←R1+R2
• Subtraction Microoperation:
R3 ←R1- R2 or :
R3 ←R1+R2+1
1’s complement

43. Arithmetic Microoperations
• One’s Complement Microoperation:
R2 ←R2
• Two’s Complement Microoperation:
R2 ←R2+1
• Increment Microoperation:
R2 ←R2+1
• Decrement Microoperation:
R2 ←R2-1

44. Arithmetic Microoperations:
Binary Adder
• A binary adder is constructed with full-adder circuits
connected in cascade, with the output carry from
one full-adder connected to the input carry of the
next full-adder.
Fig: 4-bit binary adder

45. Arithmetic Microoperations:
Binary Adder
• 4-bit binary adder is constructed with interconnection
of four full-adders (FA).
• An n-bit binary adder requires n full-adders.
• The n data bits for the A inputs come from one
register.
• The n data bits for the B inputs come from another
register.
• The sum can be transferred to a third register or one
of the source registers, replacing its previous content.

46. Arithmetic Microoperations:
Binary Adder
• 4 data bits for the A inputs come from one register.
• 4 data bits for the B inputs come from another
register.
• The augend bits of A and the addend bits of B are
designated by subscript numbers from right to left,
with subscript 0 denoting the low-order bit.
• The input carry to the binary adder is C0 and the
output carry is C4.
• The output carry from each full-adder is connected
to the input carry of the next-high-order full-adder.

47. Arithmetic Microoperations:
Binary Adder-Subtractor
• The subtraction A-B can be done by taking the 2’
complement of B and adding it to A. The 2’s
complement can be obtained by taking the 1’
complement and adding one to the least significant
pair of bits.
• The 1’ complement can be implemented with
inverters and a one can be added to the sum through
the input carry.
• The addition and subtraction operation can be
combined into one common circuit by including an
exclusive-OR gate with each full-adder.

48. Arithmetic Microoperations:
Binary Adder-Subtractor
• The mode input M controls the operation.
• When M=0 the circuit is an Adder and when M=1 the
circuit becomes a Subtractor.
Fig: 4-bit Adder-Subtractor

49. Arithmetic Microoperations:
Binary Adder-Subtractor
• Each exclusive-OR gate receives input M and one of
the input of B.
• When M=0, we have B 0=B.

• The full-adder receive the value of B, the input carry
C0 is 0, and the circuit performs A plus B.
• When M=1, we have B  1=B’ and C0 =1.
• The inputs are all complemented and a 1 is added
through the input carry C0.
• The circuit performs the operation A plus the 2’s
complement of B.

50. Arithmetic Microoperations:
Binary Adder-Subtractor
• For unsigned numbers, this gives A – B if A≥B
provided that there is overflow or
• For signed numbers, the result is A – B provided that
there is no overflow.
the 2’s complement of the result if A < B
(example: 3 – 5 = -2= 1110)

51. Arithmetic Microoperations:
Binary Incrementer
• The increment microoperation adds one to a
number in a register.
• Binary Incrementer can also be implemented
using a counter.
• A incrementer can be accomplished by half-
adders (HA) connected in cascade.

52. Arithmetic Microoperations:
Binary Incrementer
C S
x y
HA
C S
x y
HA
C S
x y
HA
C S
x y
HA
S0
S1
S2
S3
C4
1
A0
A1
A2
A3
Fig: 4-bit Binary Incrementer

53. Arithmetic Microoperations:
Binary Incrementer
• One of the input to the least significant half-
adder (HA) is connected to logic-1.
• The output carry from one half-adder is
connected to one of the input of the next-
higher-order half-adder.
• The circuit receives the four bits from A0
through A3, adds one to it, and generates the
incremented output in S0 through S3.
• An n-bit binary incrementer can be extended
by including n half-adders.

54. Arithmetic Microoperations:
Binary decrementer
• A binary decrementer can be implemented by
adding 1111 to the desired register each time.

55. Arithmetic Microoperations:
Arithmetic Circuit
• Arithmetic circuit performs seven distinct arithmetic
operations and the basic component of it is the
parallel adder.
• By controlling the data inputs to the adder, it is
possible to obtain different types of arithmetic
operations.
• The output of the binary adder is calculated from the
following arithmetic sum:
D = A + Y + Cin

56. Arithmetic Microoperations: 4-bit Arithmetic Circuit

57. Arithmetic Microoperations:
Arithmetic Circuit
• 4-bit Arithmetic circuit has four full-adder circuits that
constitute the 4-bit adder and four multiplexers for
choosing different operations.
• There are two 4-bit inputs A and B and a 4-bit output
D.
• The four inputs from A go directly to the X inputs of
the binary adder.
• Each of the four inputs from B are connected to the
data inputs of the multiplexers.
• The multiplexers data inputs also receive the
complement of B.

58. Arithmetic Microoperations:
Arithmetic Circuit
• The other two data inputs are connected to logic-0
and logic-1.
• The four multiplexers are controlled by two selection
inputs S1 and S0. The input carry Cin, goes to the carry
input of the FA in the least significant position. The
other carries are connected from one stage to the
next.
• By controlling the value of Y with the two selection
inputs S1 and S0 and making Cin equal to 0 or 1, it is
possible to generate the eight arithmetic
microoperations

59. Arithmetic Microoperations:
Arithmetic Circuit

60. Arithmetic Circuit

61. Logic Microoperations

62. Logic Microoperations
• Logic microoperations specify binary operations
for strings of bits stored in registers.
• These operations consider each bit of the
register separately and treat them as binary
variables.
• For example, the exclusive-OR microoperation
with the contents of two registers RI and R2 is
symbolized by the statement
• The exclusive-OR microoperation symbolizes
the logic computation

63. Special symbols
• For logic microoperations some special symbols
are adopted.
• The reason for adopting the special symbols is
to be able to distinguish the symbols used in
arithmetic microoperations.

64. Four basic microoperations
OR Microoperation
• Symbol: 
• Gate:
• Example: 100110  010110 = 110110

65. AND Microoperation
• Symbol: 
• Gate:
• Example: 100110  010110 = 000110
Four basic microoperations

66. Complement (NOT) Microoperation
• Symbol:

• Gate:
• Example: 1010110 = 0101001
Four basic microoperations

67. XOR (Exclusive-OR) Microoperation
• Symbol: 
• Gate:
• Example: 100110  010110 = 110000
Four basic microoperations

68. • The + between R2 and R3 specifies an add
microoperation.
• The OR microoperation is designated by the symbol V
between registers R5
• and R6.
Four basic microoperations

69. List of Logic Microoperations
• There are 16 different logic operations that can be
performed with two binary variables.
• The Boolean functions
listed in the first column
represents a
relationship between
two binary variables x
and y.
• The logic micro-
operations listed in the
second column
represent a relationship
between the binary
content of two registers
A and B.

70. List of Logic Microoperations
• The 16 different logic operations can be
determined from all possible truth tables
obtained with two binary variables.
• Each of the 16 columns F0 through F15
represents a truth table of one possible Boolean
function for the two variables x and y.

71. List of Logic Microoperations
• Most computers use
only four:- AND, OR,
XOR, and complement
operations to derive 16
logic microoperations.

72. Logic Circuit
• It consists of four gates and a multiplexer. Each of the
four logic operations is generated through a gate that
performs the required logic.
• The two selection inputs S1 and S0 choose one of the
data inputs of the multiplexer and direct its value to the
output.

73. Some Applications
• Logic micro-operations are very useful for
manipulating individual bits or a portion of a
word stored in a register.
• They can be used to change bit values, delete a
group of bits or insert new bits values into a
register.

74. Selective-set operation
• The selective-set operation sets to 1 the bits in
register A where there are corresponding l's in
register B. It does not affect bit positions that
have 0's in B.
• The OR microoperation can be used to
selectively set bits of a register.

75. Selective-complement operation
• The selective-complement operation
complements bits in A where there are
corresponding 1's in B. It does not affect bit
positions that have 0's in B. For example:
• The exclusive-OR microoperation can be used
to selectively complement bits of a register.

76. Selective-clear operation
• The selective-clear operation clears to 0 the bits
in A only where there are corresponding l's in B.
For example:
• The corresponding logic microoperation is

77. Mask operation
• The mask operation is similar to the selective-
clear operation except that the bits of A are
cleared only where there are corresponding O's
in B. The mask operation is an AND micro
operation as seen from the following numerical
example:

78. Insert operation
• The insert operation inserts a new value into a
group of bits. This is done by first masking the
bits and then ORing them with the required
value.
• For example, suppose that an A register
contains eight bits, 0110 1010. To replace the
four leftmost bits by the value 1001 we first mask
the four unwanted bits:
AND
OR

79. Clear operation
• The clear operation compares the words in A
and B and produces an all 0's result if the two
numbers are equal.
• This operation is achieved by an exclusive-OR
microoperation as shown by the following
example

80. Shift Microoperations

81. Microoperations
• A microoperation is an elementary operation
performed with the data stored in registers.
• The microoperations most often encountered in digital
computers are classified into four categories:
 Register transfer microoperations (on binary
information)
 Arithmetic microoperations (on numeric data
stored in the registers)
 Logic microoperations (bit manipulations on non-
numeric data)
 Shift microoperations

82. Shift Microoperations
• Shift microoperations are used for serial transfer of
data.
• The Shift microoperations that specify a 1-bit shift to
the left of the content of register R and a 1-bit shift
to the right of the content of register R.
• During a shift-left operation the serial input transfers
a bit into the rightmost position.
• During a shift-right operation the serial input
transfers a bit into the leftmost position.
Fig: Shift Left Fig: Shift Right

83. Types of Shift Microoperations
There are three types of shifts Microoperations :
1) Logical
2) Circular
3) Arithmetic

84. Logical Shift
• A logical shift is one that transfers 0 through the
serial input.
• The symbols shl and shr for logical shift-left and
shift-right microoperations.
• The bit transferred to the end position through the
serial input is assumed to be 0 during a logical
shift.

85. Logical Shift
• A logical shift is one that transfers 0 through the
serial input.
• The symbols shl and shr for logical shift-left and
shift-right microoperations.

86. Circular Shift
• The circular shift (also known as a rotate
operation) circulates the bits of the register
around the two ends without loss of information.
• This is accomplished by connecting the serial
output of the shift register to its serial input.
• We will use the symbols cil and cir for the circular
shift left and right, respectively.

87. Arithmetic Shift
• An arithmetic shift microoperation shifts a signed
binary number to the left or right.
• An arithmetic shift-left multiplies a signed binary
number by 2.
• An arithmetic shift-right divides the number by 2.
• Arithmetic shifts must leave the sign bit unchanged
because the sign of the number remains the same
when it is multiplied or divided by 2.
• Negative numbers are stored in 2’s complement
form.
Fig: arithmetic shift right

88. Arithmetic Shift
• An arithmetic shift microoperation shifts a signed
binary number to the left or right.
• An arithmetic shift-left multiplies a signed binary
number by 2.
• An arithmetic shift-right divides the number by 2.
• Arithmetic shifts must leave the sign bit unchanged
because the sign of the number remains the same
when it is multiplied or divided by 2.
• Negative numbers are stored in 2’s complement
form.
Fig: arithmetic shift right

89. Arithmetic Shift
• The arithmetic shift-right leaves the sign bit
unchanged and shifts the number (including the
sign bit) to the right.
• Thus Rn-1 remains the same, Rn-2 receives the bit
from Rn-1 " and so on for the other bits in the
register. The bit in R0 is lost.

90. Arithmetic Shift
• The arithmetic shift-left inserts a 0 into R0 and
shifts all other bits to the left.
• The initial bit of Rn-1 is lost and replaced by the bit
from Rn-2.
• A sign reversal occurs if the bit in Rn-1 changes in
value after the shift. This happens if the
multiplication by 2 causes an overflow.
• An overflow occurs after an arithmetic shift left if
initially, before the shift, Rn-1 is not equal to Rn-2.

91. Arithmetic Shift
• An overflow flip-flop VS, can be used to detect an
arithmetic shift-left overflow.
• If VS = 0, there is no overflow, but if VS = I, there is
an overflow and a sign reversal after the shift.
• VS must be transferred into the overflow flip-flop
with the same clock pulse that shifts the register.

92. Hardware Implementation
• The 4-bit shifter has four
data inputs, A0 through A3,
and four data outputs, H0
through H3.
• There are two serial inputs,
one for shift left (IL) and the
other for shift right (IR).
Fig: 4-bit combinational circuit shifter

93. Hardware Implementation
• When the selection input
S=0 the input data are
shifted right (down in the
diagram).
• When S = 1, the input data
are shifted left (up in the
diagram).
• A shifter with n data inputs
and outputs requires n
multiplexers.
Fig: 4-bit combinational circuit shifter

94. 4-bit Combinational Circuit Shifter

95. Arithmetic Logic Shift Unit
• Instead of having individual registers performing the
microoperations directly, computer systems employ a
number of storage registers connected to a common
operational unit called an arithmetic logic unit,
abbreviated ALU.
• The shift microoperations are often performed in a
separate unit, but sometimes the shift unit is made
part of the overall ALU.
• The arithmetic, logic, and shift circuits can be
combined into one ALU with common selection
variables.

96. Arithmetic Logic Shift Unit

97. Arithmetic Logic Shift Unit

98. Common Bus System
&
Computer Instructions

99. Registers for the Basic Computer

100. Common Bus System
• Path must be provided to transfer information form
one register to another register and between
memory and registers.
• The number of wires will be excessive if connections
are made between the outputs of each register and
the inputs of the other registers.
• A more efficient scheme for transferring information
in a system with many registers is to use a common
bus system.

101. Basic computer registers connected to a common bus

102. Common Bus System
• S2S1S0: Selects the
register/memory that
would use the bus.
• LD (load): When
enabled, the
particular register
receives the data
from the bus during
the next clock pulse
transition.
• The memory receives
the contents of the
bus when its write
input is activated.

103. Common Bus System
• The memory places its
16-bit output onto the
bus when the read
input is activated and
S2S1S0=111.
• DR, AC, IR, and TR have
16 bits each.
• AR and PC: have 12 bits
each since they hold a
memory address

104. • When the contents
of AR or PC are
applied to the 16-bit
common bus, the
four most significant
bits are set to zeros.
• When AR or PC
receives information
from the bus, only
the 12 least
significant bits are
transferred into the
register.
Common Bus System

105. • INPR and OUTR:
communicate with the
eight least significant
bits in the bus.
• INPR: Receives a
character from the
input device
(keyboard,…etc) which
is then transferred to
AC.
• OUTR: Receives a
character from AC and
delivers it to an output
device (say a Monitor).
Common Bus System

106. • The common bus receive
information from six
registers and the
memory unit. The bus
lines are connected to
the inputs of six registers
and the memory.
• Five registers have three
control inputs: LD (load),
INR (increment), and CLR
(clear). This type of
register is equivalent to a
binary counter with
parallel load and
synchronous clear.
Common Bus System

107. • The increment
operation is achieved
by enabling the count
input of the counter.
• Two registers have
only a LD input.
Common Bus System

108. • The input data and
output data of the
memory are
connected to the
common bus.
• But the memory
address is connected
to AR.
Common Bus System

109. • Therefore, AR must
always be used to
specify a memory
address.
• By using a single
register for the
address, we eliminate
the need for an
address bus that
would have been
needed otherwise.
Common Bus System

110. • Register  Memory:
Write operation
• Memory  Register:
Read operation (note
that AC cannot
directly read from
memory)
• The 16-bit inputs of
AC come from an
adder and logic
circuit. The circuit has
three sets of inputs.
Common Bus System

111. • One set of 16-bit
inputs come from the
outputs of AC.
• They are used to
implement register
micro-operations
such as complement
AC and shift AC.
• The inputs from DR
and AC are used for
arithmetic and logic
micro-operations,
such as add DR to AC,
etc.
Common Bus System

112. • The result of an addition
is transferred to AC and
the end carry-out of the
addition is transferred
to flip-flop E (extended
AC bit).
• The third set of 8-bit
inputs come from the
input register INPR.
Common Bus System

113. • The content of any
register can be applied
onto the bus and an
operation can be
performed in the adder
and logic circuit during
the same clock cycle
Common Bus System

114. Computer Instructions
• An Instruction is a group of bits that instructs the
computer to perform a specific operation.
• The most basic part of an instruction is its operation
code part.
• The operation code of an instruction is a group of
bits that defines certain operations such as add,
subtract, shift, and complement.

115. Computer Instructions
• The number of bits required for the operation code
depends on the total number of operations
available in the computer.
• 2n
(or little less) distinct operations
n bit operation code

116. Fig: Basic computer instruction formats
Computer Instructions
The basic computer has three instruction code formats
• Each format has 16 bits.

117. Fig: Basic computer instruction formats
Computer Instructions
A memory-reference instruction uses one bit to specify
the addressing mode I. I = 0 for direct, 1=Indirect

118. Fig: Basic computer instruction formats
Computer Instructions
A register-reference instruction specifies an operation
on AC, other 12 bits are used to specify the operation

119. Fig: Basic computer instruction formats
Computer Instructions
An IO instruction does not need a reference to memory,
remaining 12 bits are used to specify the type of IO operation

120. Basic computer instructions
Tab: Basic computer instructions

121. Computer Instructions
Control Unit with Timing,
Instruction Cycle and
Determine the Type of Instruction

122. Fig: Basic Computer Instruction code format
Computer Instructions

123. Computer Instructions
• Each format has 16 bits.
• The operation code (opcode) part of the instruction
contains three bits and the meaning of the remaining
13 bits depends on the operation code encountered.
• A memory-reference instruction uses 12 bits to
specify an address and one bit to specify the
addressing mode I. I is equal to 0 for direct address
and to 1 for indirect address.

124. Computer Instructions
• The register-reference instructions are recognized by
the operation code 111 with a 0 in the leftmost bit (bit
15) of the instruction. A register-reference instruction
specifies an operation on or a test of the AC register.
An operand from memory is not needed; therefore,
the other 12 bits are used to specify the operation or
test to be executed.
• An input-output instruction does not need a reference
to memory and is recognized by the operation code
111 with a 1 in the leftmost bit of the instruction. The
remaining 12 bits are used to specify the type of
input-output operation or test performed.

125. Basic Computer Instructions
The type of instruction is recognized by the
computer control from the four bits in positions
12 through 15 of the instruction.
• Memory-reference: If the three opcode bits in
position 12 through 14 are not equal to 111.
• Bit 15 is taken as the addressing mode I.
If the 3 bits opcode is equal to 111, control then
inspects the bit in position 15.
• Register-reference: If 15 bit is 0.
• Input-output: If 15 bit is 1.

126. Basic Computer Instructions

127. Basic Computer Instructions
The 16 bits of an instruction code is reduced to
equivalent four digits hexadecimal digits.
• Memory-reference: the address part is
denoted by three x’s and stand for the three
hexadecimal digits.
• Register-reference: The leftmost four bits are
always 0111, which is equivalent to
hexadecimal 7.
• Input-output: The last four bits are always
1111, equivalent to hexadecimal F.

128. Control Unit with Timing
• The timing for all registers in the basic computer is
controlled by a master clock generator.
• The clock pulses are applied to all flip-flops and
registers in the system, including the flip-flops and
registers in the control unit.
• The clock pulses do not change the state of a register
unless the register is enabled by a control signal (i.e.,
Load)

129. • The control signals are generated in the control unit
and provide control inputs for the multiplexers in the
common bus, control inputs in processor registers,
and micro-operations for the accumulator
There are two major types of control organization:
 Hardwired control
 Micro-programmed control
Control Unit with Timing

130. • Hardwired Organization: the control logic is
implemented with gates, flip-flops, decoders, and
other digital circuits.
• Micro-programmed Organization: the control
information is stored in a control memory (if the
design is modified, the micro-program in control
memory has to be updated)
Control Unit with Timing

131. Control Unit of basic computer
Fig: Block diagram of the hardwired control unit

132. Control Unit of basic computer
Fig: Block diagram of the hardwired control unit
• It consists of two
decoders, a sequence
counter, and a number
of control logic gates.
• An instruction read
from memory is placed
in the instruction
register (IR)

133. Control Unit of basic computer
Fig: Block diagram of the hardwired control unit
• The opcode in bits are
decoded with a 3 x 8
decoder. The eight
outputs of the decoder
are designated by the
symbols D0 through D7.
• Bit 15 of the
instruction is
transferred to a flip-
flop I.
• Bits 0 through 11 are
applied to the control
logic gates.

134. Control Unit of basic computer
Fig: Block diagram of the hardwired control unit
• The 4-bit sequence
counter can count in
binary from 0 through
15.
• The outputs of the
counter are decoded
into 16 timing signals
T0 through T15.
• The sequence counter
SC can be incremented
or cleared
synchronously.

135. Control Unit of basic computer
Fig: Block diagram of the hardwired control unit
• The counter is
incremented to
provide the sequence
of timing signals out of
the 4 x 16 decoder.

136. Control Timing Signals

137. Control Timing Signals
Fig: Diagram of Control Timing Signals
• The timing diagram
shows the time
relationship of the
control signals.
• The sequence counter
SC responds to the
positive transition of
the clock.

138. Control Timing Signals
Fig: Diagram of Control Timing Signals
• Initially, the CLR input
of SC is active. The
first positive
transition of the clock
clears SC to 0, which
in turn activates the
timing signal T0 out of
the decoder. T0 is
active during one
clock cycle.

139. Control Timing Signals
Fig: Diagram of Control Timing Signals
• SC is incremented
with every positive
clock transition,
unless its CLR input is
active.
• This produces the
sequence of timing
signals T0, T1, T2, T3, T4
and so on, as shown
in the diagram.

140. Control Timing Signals
Fig: Diagram of Control Timing Signals
• The last three
waveforms in diagram
show how SC is
cleared when D3T4 =
1.
• Output D3 from the
operation decoder
becomes active at the
end of timing signal
T2.

141. Control Timing Signals
Fig: Diagram of Control Timing Signals
• When timing signal T4
becomes active, the
output of the AND
gate that implements
the control function
D3T4 becomes active.
• This signal is applied
to the CLR input of
SC. On the next
positive clock
transition (the one
marked T4 in the
diagram) the counter

142. Control Timing Signals
Fig: Diagram of Control Timing Signals
• This causes the timing
signal T0 to become
active instead of T5
that would have been
active if SC were
incremented instead
of cleared.

143. Instruction Cycle
• A program is a sequence of instructions stored in
memory.
• The program is executed in the computer by going
through a cycle for each instruction (in most cases).
• Each instruction in turn is subdivided into a sequence
of sub-cycles or phases.

144. Instruction Cycle Phases
• In the basic computer each instruction cycle consists
of the following phases:
 1- Fetch an instruction from memory
 2- Decode the instruction
 3- Read the effective address from memory if the
instruction has an indirect address
 4- Execute the instruction
• This cycle repeats indefinitely unless a HALT
instruction is encountered

145. Fetch and Decode
• Initially, the Program Counter (PC) is loaded with the
address of the first instruction in the program.
• The sequence counter SC is cleared to 0, providing a
decoded timing signal T0.
• After each clock pulse, SC is incremented by one, so
that the timing signals go through a sequence T0, T1,
T2, and so on.

146. Fetch and Decode
 T0: AR←PC (this is essential!!)
The address of the instruction is moved to AR.
 T1: IR←M[AR], PC←PC+1
The instruction is fetched from the memory to IR ,
and the PC is incremented.
 T2: D0,…, D7←Decode IR(12-14), AR←IR(0-11),
I←IR(15)

147. Fig: Register transfer for the fetch phase.
Register transfer for the fetch phase

148. Fig: Register transfer for the fetch phase.
Register transfer for the fetch phase
• Figure shows how
the first two register
transfer statements
are implemented in
the bus system.

149. Fig: Register transfer for the fetch phase.
Register transfer for the fetch phase
T0. (T0: AR←PC)
• To transfer the from
PC to AR we must
apply timing signal
• Place the content of
PC onto the bus by
making the bus
selection inputs S2,
S1, S0 equal to 010.
Transfer the
content of the bus
to AR by enabling
the LD input of AR.

150. Fig: Register transfer for the fetch phase.
Register transfer for the fetch phase
T1: IR←M[AR],
PC←PC+1
• To implement the
second statement,
we need timing
signal T1.
Enable the read
input of memory.
Place the content
of memory onto
the bus by making
S2S1S0=111.

151. Fig: Register transfer for the fetch phase.
Register transfer for the fetch phase
Transfer the
content of the bus
to IR by enabling
the LD input of IR.
Increment PC by
enabling the INR
input of PC.

152. Fig: Register transfer for the fetch phase.
Register transfer for the fetch phase
• The bus system
shows how T0 and
T1 are connected to
the control inputs of
the registers, the
memory, and the
bus selection inputs.
• Multiple input OR
gates are included
because there are
other control
functions that will
initiate similar
operations.

153. Determine the Type of Instruction
How the control determines the instruction cycle type
after the decoding.

154. Determine the Type of Instruction
• The flowchart
shows the
initial
configurations
for the
instruction
cycle and also
how the control
determines the
instruction
cycle type after
the decoding.
Fig: Flowchart for instruction cycle

155. Determine the Type of Instruction
• The timing
signal that is
active after the
decoding is T3.
• During time T3,
the control
unit determine
the type of
instruction
that was read
from the
memory.
Fig: Flowchart for instruction cycle

156. Determine the Type of Instruction
• If D7=1, the
instruction
must be a
register-
reference or
input-output
type.
• If D7 = 0, the
instruction
must be a
memory-
reference
instruction.
Fig: Flowchart for instruction cycle

157. Determine the Type of Instruction
• when D7 = 0,
the operation
code must be
one of the
other seven
values 000
through 110.
Fig: Flowchart for instruction cycle

158. Determine the Type of Instruction
• Control then
inspects the
value of the
first bit of the
instruction,
which is now
available in
flip-flop I.
Fig: Flowchart for instruction cycle

159. Determine the Type of Instruction
• If D7 = 0 and I =
1, indicates a
memory-
reference
instruction
with an
indirect
address. So it
is then
necessary to
read the
effective
address from
memory. Fig: Flowchart for instruction cycle

160. Determine the Type of Instruction
• If D7 = 0 and I =
0, indicates a
memory-
reference
instruction
with a direct
address.
Fig: Flowchart for instruction cycle

161. Determine the Type of Instruction
• If D7 = 1 and I =
0, indicates a
register-
reference
instruction.
• If D7 = 1and I =
1, indicates an
input-output
instruction.
Fig: Flowchart for instruction cycle

162. Determine the Type of Instruction
• The three
instruction
types are
subdivided into
four separate
paths.
• The selected
operation is
activated with
the clock
transition
associated with
timing signal T3.
Fig: Flowchart for instruction cycle

163. Determine the Type of Instruction
Symbolized:-
• D'7IT3: AR
M[AR]
• D'7I'T3:
Nothing
• D7I'T3:
Execute a
register-
reference instr.
• D7IT3:
Execute an
input-output
instr.
Fig: Flowchart for instruction cycle

164. Determine the Type of Instruction
• A register-
reference or
input-output
instruction can
be executed
with the clock
associated
with timing
signal T3.
Fig: Flowchart for instruction cycle

165. Determine the Type of Instruction
• The execution
of the
memory-
reference
instruction can
be continued
with timing
variable T4,
when
instruction
with I=0.
Fig: Flowchart for instruction cycle

166. Determine the Type of Instruction
After the instruction is executed, SC is cleared to 0 and
control returns to the fetch phase with T0=1.

167. Memory-reference instruction

168. Register-reference instruction

169. Input-output instruction

170. Input-Output and Interrupt
Input-Output Configuration,
Program Interrupt, and
Interrupt cycle

171. Input-Output and Interrupt
• Instructions and data stored in memory come from
some input device.
• Computational results must be transmitted to the
user through some output device.

172. Input-Output Configuration
• The terminal sends and receives serial information.
• Each quantity of information has eight bits of an
alphanumeric code.
• The serial information from the keyboard is shifted
into the input register INPR.

173. Input-Output Configuration
• The serial information for the printer is stored in the
output register OUTR.
• These two registers communicate with a
communication interface serially and with the AC in
parallel.

174. Input-Output Configuration
• The input register INPR consists of eight bits and
holds alphanumeric input information.
• The 1-bit input flag FGI is a control flip-flop.

175. Input-Output Configuration
• The flag bit is set to 1 when new information is
available in the input device and is cleared to 0 when
the information is accepted by the computer.
• The output register OUTR works similarly but the
direction of information flow is reversed.

176. Input-Output Configuration
• Initially, the input flag FGI is cleared to 0.
• When a key is struck in the keyboard, an 8-bit
alphanumeric code is shifted into INPR and input flag
FGI is set to 1.

177. Input-Output Configuration
• As long as the flag is set, the information in INPR
cannot be changed by striking another key.

178. Input-Output Configuration
• Initially, the output flag FGO is set to 1.
• The computer checks the flag bit; if it is 1, the
information from AC is transferred in parallel to
OUTR and FGO is cleared to 0.

179. Input-Output Configuration
• The output device accepts the coded information,
prints the corresponding character, and when the
operation is completed, it sets FGO to 1.
• The computer does not load a new character into
OUTR when FGO is 0.

180. Input-Output Instructions
• Input and output instructions are needed for
transferring information to and from AC register, for
checking the flag bits, and for controlling the
interrupt facility.
• Input-output instructions have an operation code
1111 and are recognized by the control when D7 = 1
and I = 1.
• The remaining bits of the instruction specify the
particular operation.

181. Input-Output Instructions
• These instructions are executed with the clock
transition associated with timing signal T3.
• Each control function needs a Boolean relation D7IT3,
which we designate for convenience by the symbol p.

182. Input-Output Instructions
• The control function is distinguished by one of the
bits in IR (6-11).
• By assigning the symbol Bi to bit i of IR, all control
functions can be denoted by pBi for i = 6 though 11.

183. Input-Output Instructions
• The sequence counter SC is cleared to 0 when
p=D7IT3=1.
• The last two instructions set and clear an interrupt
enable flip-flop IEN.

184. Program Interrupt
• The computer keeps checking the flag bit, and when it
finds it set, it initiates an information transfer.
• The difference of information flow rate between the
computer and that of the input—output device makes
this type of transfer inefficient.
• An alternative to the programmed controlled
procedure is to let the external device inform the
computer when it is ready for the transfer.
• In the meantime the computer can be busy with other
tasks. This type of transfer uses the interrupt facility.
• While the computer is running a program, it does not
check the flags.

185. Program Interrupt
• When a flag is set, the computer is momentarily
interrupted from the current program.
• The computer deviates momentarily from what it is
doing to perform of the input or output transfer.
• It then returns to the current program to continue
what it was doing before the interrupt.
• The interrupt enable flip-flop IEN can be set and
cleared with two instructions.
When IEN is cleared to 0 (with the IOF instruction),
the flags cannot interrupt the computer.
When IEN is set to (with the ION instruction), the
computer can be interrupted.

186. Program Interrupt
• An interrupt flip-flop
R is included in the
computer. When R =
0, the computer goes
through an
instruction cycle.
• During the execute
phase of the
instruction cycle IEN
is checked by the
control.

187. Program Interrupt
• If IEN is 0, it indicates
that the programmer
does not want to use the
interrupt, so control
continues with the next
instruction cycle.
• If IEN is 1, control checks
the flag bits. If both flags
are 0, it indicates that
neither the input nor the
output registers are
ready for transfer of
information. In this case,
control continues with
the next instruction cycle.

188. Program Interrupt
• If either flag is set to
1 while IEN = 1, flip-
flop R is set to 1. At
the end of the
execute phase,
control checks the
value of R, and if it is
equal to 1, it goes to
an interrupt cycle
instead of an
instruction cycle.

189. Interrupt Cycle
• The interrupt cycle is a hardware implementation of
a branch and save return address operation.
• The return address available in PC is stored in a
specific location.
• This location may be a processor register, a memory
stack, or a specific memory location.

190. Interrupt Cycle
• When an interrupt
occurs and R is set to
1 while the control is
executing the
instruction at address
255.
• At this time, the
returns address 256
is in PC.
• The programmer has previously placed an input—
output service program in memory starting from
address 1120 and a BUN 1120 instruction at address 1.
Fig: Demonstration of the interrupt cycle

191. Interrupt Cycle
• When control reaches
timing signal T0 and
finds that R = 1, it
proceeds with the
interrupt cycle.
• The content of PC
(256) is stored in
memory location 0,
PC is set to 1, and R is
cleared to 0.
• The branch instruction at address 1 causes the
program to transfer to the input—output service
program at address 1120.
Fig: Demonstration of the interrupt cycle

192. Interrupt Cycle
• This program checks
the flags, determines
which flag is set, and
then transfers the
required input or
output information.
• Once this is done, the
instruction ION is
executed to set IEN
to 1 (to enable
further interrupts),
and the program returns to the location where it was
interrupted.
Fig: Demonstration of the interrupt cycle

193. BUN: Branch Unconditionally
• BUN: Branch Unconditionally is an Memory-
Reference Instructions.
• The BUN instruction allows the programmer to
specify an instruction out of sequence and we say
that the program branches (or jumps)
unconditionally.
• The instruction is executed with one microoperation:
• This instruction transfers the program to the
instruction specified by the effective address.

194. Central Processing Unit
Organization
Register Organization and Stack
Organization

195. Central Processing Unit
• The CPU is made up of three major parts
• 1) Register Set
• 2) ALU
• 3) Control Unit
Fig: Major components of CPU.

196. Central Processing Unit
• The register set stores intermediate data used during
the execution of the instructions.
• The arithmetic logic unit (ALU) performs the required
microoperations for executing the instructions.
• The control unit supervises the transfer of
information among the registers and instructs the
ALU as to which operation to perform.
Fig: Major components of CPU.

197. General Register Organization
• Earlier, we used memory locations to store pointers,
counters, return address, temporary results, and
partial products during multiplication, etc.
• Memory access is the most time-consuming
operation in a computer
• More convenient and efficient way is to store
intermediate values in processor registers
• When a large number of registers are included in the
CPU, it is most efficient to connect them through a
common bus system

198. General Register Organization
Fig: Register set with common ALU

199. General Register Organization
• Fig shows Bus organization for 7 CPU registers
• 2 MUX : select one of 7 register or external data
input by SELA and SELB
• BUS A and BUS B : form the inputs to a common ALU
• ALU : OPR determine the arithmetic or logic
microoperation
• 3 X 8 Decoder : select the register (by SELD) that
receives the information from ALU
• The result of the microoperation is available for
external data output and also goes into the inputs of
all the registers

200. General Register Organization
For example, to perform the operation
Binary selector inputs:
• MUX A selector (SELA) : to place the content of R2
into BUS A
• MUX B selector (SELB) : to place the content of R3
into BUS B
• ALU operation selector (OPR) : to provide the
arithmetic addition R2 + R3
• Decoder selector (SELD) : to transfer the content of
the output bus into R1

201. General Register Organization
For example, to perform the operation

202. General Register Organization
• Control word is a combination of 4 fields and consists
14 bit
• SELA (3 bits) : select a source register for the A input
of the ALU
• SELB (3 bits) : select a source register for the B input
of the ALU
• SELD (3 bits) : select a destination register using the 3
X 8 decoder
• OPR (5 bits) : select one of the operations in the ALU

203. General Register Organization
For example, to perform the operation

205. General Register Organization
• The increment and transfer microoperations do not
use the B input of the ALU. For these cases, the B
field is marked with a dash.
• We assign 000 to any unused field when formulating
the binary control word
• The direct transfer from input to output is
accomplished with a control word of all 0's.

206. Stack Organization
• A stack is a storage device that stores information in
such a manner that the item stored last is the first
item retrieved.
• Stack or LIFO(Last-In, First-Out)
• Stack Pointer (SP)
The register that holds the address for the stack
SP always points at the top item in the stack
• Two Operations of a stack : Insertion and Deletion of
Items
PUSH : Push-Down = Insertion
POP : Pop-Up = Deletion

207. Stack Organization
• Stack can be implemented by using two ways:
• Register Stack
A finite number of memory words or register.
• Memory Stack
A portion of a large memory

208. Register Stack
• A stack can be placed in a portion of a large memory
or it can be organized as a collection of a finite
number of memory words or registers.
• The stack pointer register SP contains a binary
number whose value is equal to the address of the
word

209. Register Stack
• Initially, SP is cleared to
0, EMTY is set to 1, and
FULL is cleared to 0, so
that SP points to the
word at address 0 and
the stack is marked
empty and not full.
• In this diagram, three
items are placed in the
stack: A, B, and C, in that
order. Item C is on top of
the stack so that the
content of SP is now 3.

210. Register Stack- Push
• To insert a new item,
the stack is pushed by
incrementing SP and
writing a word in the
next-higher location in
the stack.

211. Register Stack- Push
• When 63 is
incremented by 1, the
result is 0 since 111111
+ 1 = 1000000 in
binary, but SP can
accommodate only the
six least significant bits.

212. Register Stack- Pop
• To remove the top
item, the stack is
popped by reading the
memory word at
address 3 and
decrementing the
content of SP
• A new item is deleted
from the stack if the
stack is not empty (if
• EMTY = 0).

213. Register Stack- Pop
• To remove the top
item, the stack is
popped by reading the
memory word at
address 3 and
decrementing the
content of SP

214. Memory Stack
Stack
• Register Stack
• Memory Stack

215. Memory Stack
• A Stack can be implemented in a random-access
memory.
• The implementation of a stack in the CPU is done by
assigning a portion of memory to a stack operation
and using a processor register as a stack pointer.
• The stack pointer SP points at the top of the stack.
• SP is used to push or pop or pop items into or from
the stack.

216. Memory Stack
• The initial value of SP is 4001
and the stack grows with
decreasing addresses.
• Thus the first item stored in
the stack is at address 4000,
the second item is stored at
address3999, and the last
address that can be used for
the stack is 3000.

217. Memory Stack
• A new item is inserted with
the push operation as
follows:
• A new item is deleted with a
pop operation as follows:

218. Memory Stack
• Most computers do not
provide hardware to check
for stack overflow (full stack)
or underflow (empty stack).
• The stack limits can be
checked by using two
processor registers:
• One to hold the upper limit
(3000 in this case), and
• The other to hold the lower
limit (4001 in this case).

219. Memory Stack
• The stack may be constructed to grow by increasing
the memory address.
• In such a case, SP is incremented for the push
operation and decremented for the pop operation.
• A stack may be constructed so that SP points at the
next empty location above the top of the stack.
• In this case the sequence of microoperations must
be interchanged

220. Microprogrammed Control Unit

221. Microprogrammed Control Unit
• Major functional parts in a digital computer
1) CPU
2) Memory
3) I/O
• The CPU is made up of three major parts
1) Register Set
2) ALU
3) Control Unit

222. Microprogrammed Control Unit
Hardwired Control Unit:
• When the control signals are generated by hardware
using conventional logic design techniques, the control
unit is said to be hardwired.
• The control logic is implemented with gates, flip-flops,
decoders, and other digital circuits.
Micro programmed control unit:
• the control information is stored in a control memory (if
the design is modified, the micro-program in control
memory has to be updated)
• A control unit whose binary control variables are stored
in memory is called a micro programmed control unit.

223. Hardwired Control Unit
Fig: Block diagram of the hardwired control unit

224. Microprogrammed Control Unit
Limitations of hardwired Control Unit:
 Complete Boolean circuit
 Difficult to implement for complex systems.
 Impossible to add an instruction after implementing
the circuit.
• Alternate
• Miro-programmed control unit:
• The function of the control unit in a digital computer
is to initiate sequences of microoperations.
• The control signals associated with operations are
stored in special memory units as Control Words.

225. Microprogrammed Control Unit
Control Word:
• The control variables at any given time can be
represented by a control word string of 1 's and 0's.
• A control word is a word whose individual bits represent
various control signals.
Micro-instruction :
• Individual control words in the control sequence are
referred to as microinstructions.
Micro-program :
• A sequence of micro-instructions which is stored in a
Control Memory (ROM or RAM).
• Control Memory is used to store the microprogram.
control memory is a part of a control unit

226. Microprogrammed Control Unit
Microoperations:
• micro-operations are detailed low-level instructions
used in some designs to implement complex machine
instructions.
Micro instruction:
• A symbolic microprogram can be translated into its
binary equivalent by means of an assembler.
• Each line of the assembly language microprogram
defines a symbolic microinstruction.
• The microinstruction specifies one or more
microperations.

227. Microprogrammed Control Unit
• The control memory is assumed to be a ROM, within
which all control information is permanently stored.
• The control memory address register specifies the
address of the microinstruction, and the control data
register holds the microinstruction read from
memory.

228. Microprogrammed Control Unit
• The microinstruction contains a control word that
specifies one or more microoperations for the data
processor. Once these operations are executed, the
control must determine the next address.
• The location of the next microinstruction may be the
one next in sequence, or it may be located
somewhere else in the control memory.

229. Microprogrammed Control Unit
• While the microoperations are being executed, the next
address is computed in the next address generator
circuit and then transferred into the control address
register to read the next microinstruction.
• Thus a microinstruction contains bits for initiating
microoperations in the data processor part and bits that
determine the address sequence for the control
memory.

230. Microprogrammed Control Unit
• The next address generator is sometimes called a micro-
program sequencer, as it determines the address
sequence that is read from control memory.
• Typical functions of a micro-program sequencer are
incrementing the control address register by one,
loading into the control address register an address from
control memory, transferring an external address, or
loading an initial address to start the control operations.

231. Microprogrammed Control Unit
• The control data register holds the present
microinstruction while the next address is computed
and read from memory.
• The data register is sometimes called a pipeline
register.
• It allows the execution of the microoperations
specified by the control word simultaneously with
the generation of the next microinstruction.

232. Microprogrammed Control Unit
• This configuration requires a two-phase clock, with
one clock applied to the address register and the
other to the data register.
• The main advantage of the micro programmed
control is the fact that once the hardware
configuration is established; there should be no need
for further hardware or wiring changes.
• If we want to establish a different control sequence
for the system, all we need to do is specify a different
set of microinstructions for control memory.

233. Microprogrammed Control Unit
• This configuration requires a two-phase clock, with
one clock applied to the address register and the
other to the data register.
• The main advantage of the micro programmed
control is the fact that once the hardware
configuration is established; there should be no need
for further hardware or wiring changes.
• If we want to establish a different control sequence
for the system, all we need to do is specify a different
set of microinstructions for control memory.

234. Address Sequencing
• Microprogram sequencer determines the address
sequence that is read from control memory.
• The address of the next microinstruction can be specified
in several ways, depending on the sequencer inputs.
• Typical functions of a microprogram sequencer are
incrementing the control address register by one, loading
into the control address register an address from control
memory.
• Transferring an external address, or loading an initial
address to start the control operations.

235. Address Sequencing
• Microinstructions are stored in control memory in
groups, with each group specifying a routine.
• Each computer instruction has its own microprogram
routine in control memory to generate the
microoperations that execute the instruction.
• The hardware that controls the address sequencing
of the control memory must be capable of
sequencing the microinstructions within a routine
and be able to branch from one routine to another.

236. Address Sequencing
• An initial address is loaded into the control address
register when power is turned on in the computer.
• This address is usually the address of the first
microinstruction that activates the instruction fetch
routine.
• The address sequencing capabilities required in a
control memory are:

237. Address Sequencing
1)Incrementing of
the control
address register.
• The incrementer
increments the
content of the
control address
register by one,
to select the next
microinstruction
in sequence.
Fig: Selection of address for control memory.

238. Address Sequencing
2)Unconditional
branch or
conditional
branch, depending
on status bit
conditions.
• Branching is
achieved by
specifying the
branch address in
one of the fields
of the
microinstruction.
Fig: Selection of address for control memory.

239. Address Sequencing
2)Unconditional
branch or
conditional branch,
depending on
status bit
conditions.
• Conditional
branching is
obtained by using
part of the
microinstruction to
select a specific
status bit in order
to determine its
condition.
Fig: Selection of address for control memory.

240. Address Sequencing
3)A mapping
process from the
bits of the
instruction to an
address for
control memory.
• An external
address is
transferred into
control memory
via a mapping
logic circuit.
Fig: Selection of address for control memory.

241. Address Sequencing
4)A facility for
subroutine call
and return.
• The return address
for a subroutine is
stored in a special
register whose
value is then used
when the
microprogram
wishes to return
from the
subroutine.
Fig: Selection of address for control memory.

242. Address Sequencing
Conditional Branching:
• The branch logic provides decision-making capabilities in
the control unit.
• The status conditions are special bits in the system that
provide parameter information such as the carry-out of
an adder, the sign bit of a number, the mode bits of an
instruction, and input or output status conditions.
• Information in these bits can be tested and actions
initiated based on their condition: whether their value is
1 or 0.
• The status bits, together with the field in the
microinstruction that specifies a branch address, control
the conditional branch decisions generated in the
branch logic.

243. Address Sequencing
• The simplest way
is to test the
specified
condition and
branch to the
indicated address
if the condition is
met
• otherwise, the
address register
is incremented.
Fig: Selection of address for control memory.

244. Address Sequencing
• If the selected
status bit is in the 1
state, the output of
the multiplexer is 1;
otherwise, it is 0.
• A 1 output in the
multiplexer
generates a control
signal to transfer
the branch address
from the
microinstruction
into the control
address register.
Fig: Selection of address for control memory.

245. Address Sequencing
• A 0 output in the
multiplexer
causes the
address register
to be
incremented.
Fig: Selection of address for control memory.

246. Address Sequencing
• An unconditional
branch
microinstruction can
be implemented by
loading the branch
address from control
memory into the
control address
register.
• This can be
accomplished by
fixing the value of one
status bit at the input
of the multiplexer, so
it is always equal to 1.
Fig: Selection of address for control memory.

247. Address Sequencing
Mapping of Instruction:
• The status bits for this type of branch are the bits in
the operation code part of the instruction.

248. Address Sequencing
• For example, a computer with a simple instruction
format as shown in Fig. has an operation code of four
bits which can specify up to 16 distinct instructions.
• Assume further that the control memory has 128
words, requiring an address of seven bits. For each
operation code there exists a microprogram routine in
control memory that executes the instruction.
Fig: Mapping from instruction code to microinstruction address.

249. Address Sequencing
• One simple mapping process that converts the 4-bit
operation code to a 7-bit address for control memory
is shown in Fig.
• This mapping consists of placing a 0 in the most
significant bit of the address, transferring the four
operation code bits, and clearing the two least
significant bits of the control address register.
Fig: Mapping from instruction code to microinstruction address.

250. RISC and CISC
Reduced Instruction Set Architecture
&
Complex Instruction Set Architecture

251. RISC Processor
• Reduced Instruction Set Computer
Key features or major characteristics :
• It is a type of microprocessor
• It has a limited number of instructions.
• It has a simple instructions (fixed length and easy to
decode).
• It can execute the instructions very fast
• Large number of general purpose registers
• It has ability to execute one instruction per dock
cycle.
• Hardwired rather than microprogrammed controlled.

252. RISC Processor
• Register-to-register operations
• Only simple load and store operations for memory
access.
• Each operand is brought into a processor register with a
load instruction.
• Only a few addressing modes (such as immediate
operands and relative mode)
• All operations or computations are done among the
data stored in processor registers.
• Results are transferred to memory by means of store
instructions.
• Less Data types.
• Code size is large

253. CISC Processor
• Complex Instruction Set Architecture
• The design of an instruction set for a computer must
take into consideration not only machine language
constructs, but also the requirements imposed on the
use of high-level programming languages.
• The translation from high-level to machine language
programs is done by means of a compiler program.
• One reason for the trend to provide a complex
instruction set is the desire to simplify the compilation
and improve the overall computer performance.
• The task of a compiler is to generate a sequence of
machine instructions for each high-level language
statement.

254. CISC Processor
• Complex Instruction Set Architecture
Key features or major characteristics :
• A large number of instructions-typically from 100 to
250 instructions
• Some instructions that perform specialized tasks and
are used infrequently.
• A large variety of addressing modes-typically from 5 to
20 different modes (Complex Addressing Modes)
• Variable-length instruction formats
• Direct manipulation of operands residing in memory
• Instructions that manipulate operands in memory
• More Data types.
• Code size is small

255. RISC Processor
• A large number of registers is useful for storing
intermediate results.
• The advantage of register storage is that registers can
transfer information to other registers much faster
than the transfer of information to and from
memory.
• Thus register-to-memory operations can be
minimized by keeping the most frequent accessed
operands in registers.
• The use of overlapped register windows when
transferring program control after a procedure call
can improve the performance for RISC architecture.

256. RISC Overlapped Register Windows
• Procedure call and return occurs quite often in high-
level programming languages.
• When translated into machine language, a procedure
call produces a sequence of instructions that save
register values, pass parameters needed for the
procedure, and then calls a subroutine to execute the
body of the procedure.
• After a procedure return, the program restores the old
register values, passes results to the calling program,
and returns from the subroutine.
• Saving and restoring registers and passing of
parameters and results involve time consuming
operations.

257. RISC Overlapped Register Windows
• Some computers provide multiple-register banks,
and each procedure is allocated its own bank of
registers.
• This eliminates the need for saving and restoring
register values.
• Some computers use the memory stack to store the
parameters that are needed by the procedure
• But this requires a memory access every time the
stack is accessed.
• RISC processors use of overlapped register windows
to provide the passing of parameters and avoid the
need for saving and restoring register values.

258. RISC Overlapped Register Windows
• Each procedure call results in the allocation of a new
window consisting of a set of registers.
• Each procedure call activates a new register window
by incrementing a pointer.
• While the return statement decrements the pointer
and causes the activation of the previous window.
• Windows for adjacent procedures have overlapping
registers that are shared to provide the passing of
parameters and results.

259. RISC Overlapped Register Windows
• The overlapped register
windows system has a total of
74 registers.
• Registers RO through R9 are
global registers that hold
parameters shared by all
procedures.
• The other 64 registers are
divided into four windows to
accommodate procedures A,
B, C, and D.
• Each register window consists
of 10 local registers and two
sets of six registers common to
adjacent windows. Fig: Overlapped register windows

260. RISC Overlapped Register Windows
• Local registers are used for
local variables.
• Common registers are used for
exchange of parameters and
results between adjacent
procedures.
• The common overlapped
registers permit parameters to
be passed without the actual
movement of data.
• Only one register window is
activated at any given time
with a pointer indicating the
active window.
Fig: Overlapped register windows

261. RISC Overlapped Register Windows
• Each procedure call
activates a new register
window by incrementing
the pointer.
• The high registers of the
calling procedure overlap
the low registers of the
called procedure
• Therefore the parameters
automatically transfer from
calling to called procedure.
Fig: Overlapped register windows

262. RISC Overlapped Register Windows
• For example, the procedure A
calls procedure B.
• Registers R26 through R31 are
common to both procedures.
• Therefore, procedure A stores
the parameters for procedure
B in these registers.
• Procedure B uses local
registers R32 through R41 for
local variable storage.
Fig: Overlapped register windows

263. RISC Overlapped Register Windows
• If procedure B calls procedure
C, it will pass the parameters
through registers R42 through
R47.
• When procedure B is ready to
return at the end of its
computation.
• The program stores results of
the computation in registers
R26 through R31 and transfers
back to the register window of
procedure A.
Fig: Overlapped register windows

264. RISC Overlapped Register Windows
• Note that registers R1O
through R 15 are common to
procedures A and D because
the four windows have a
circular organization with A
being adjacent to D.
• Other fixed-size register
window schemes are possible,
and each may differ in the size
of the register window and
the size of the total register
file.
Fig: Overlapped register windows

265. RISC Overlapped Register Windows
• Number of global registers = G
• Number of local registers in each window = L
• Number of registers common to two windows = C
• Number of windows = W
• The number of registers available for each window is
calculated as follows:
window size = L + 2C + G
• The total number of registers needed in the processor is
register file = (L + C)W + G
• In the running example, we have G = 10, L = 10, C = 6, and W
= 4.
• The window size is 10 + 12 + 10 = 32 registers
• register file consists of (10 + 6) x 4 + 10 = 74 registers.

266. Logic Gates

267. Basic logic gates
• Not
• And
• Or
• Nand
• Nor
• Xor
x
xy
xy
x
x
y
x
y
x
y
xy
xy
x
y
x
y
x
y

268. Inversion (NOT)
A Q
0 1
1 0
Logic: Q 
A

269. OR Gate
Current flows if either switch is closed
– Logic notation A + B = C
A B C
0 0 0
0 1 1
1 0 1
1 1 1

270. AND Gate
In order for current to flow, both switches must
be closed
– Logic notation AB = C
(Sometimes AB = C)
A B C
0 0 0
0 1 0
1 0 0
1 1 1

271. Properties of AND and OR
• Commutation
o A + B = B + A
o A  B = B  A
Same as
Same as

272. Commutation Circuit
A + B B +
A
A  B B  A

273. Properties of AND and OR
• Associative Property
A + (B + C) = (A + B) + C
A  (B  C) = (A  B) 
C
=

274. Distributive Property
(A + B)  (A + C) A B C Q
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1, 1 1 1

275. Circuit for XOR
A  B  AB  A B

276. Circuits
• Combinational Circuit:
A combinational circuit consists of logic gates
whose outputs, at any time, are determined by
combining the values of the inputs.
• Sequential Circuit:
Sequential circuit is the type of circuit where
output not only relies on the current input but also
depends on the previous output.
• The combinational circuit does not use any memory.
• Sequential circuit has memory.

277. Combinational vs. Sequential Circuits
Combinational
Circuit
n-inputs m-outputs
(Depend only on inputs)
Combinational
Circuit
n-inputs m-outputs
Storage
Elements
Next
state
Present
state
Sequential Circuit
Combinational Circuit

278. Classification of Combinational Logic

279. Classification of Sequential Logic
There are two main types of sequential circuits:
• Synchronous
• Asynchronous
• Example of sequential circuits:
o Flip-Flops
o Counters
o Shift registers

280. Microprocessor Architecture
Microprocessor 8085 Architecture &
Pin Configuration

281. Microprocessor Architecture
• A microcomputer system consists of four components,
the microprocessor, memory and Input and Output
devices.
• The microprocessor manipulates data, controls the
timing of various operations, and communicates with
peripherals , memory and I/O.
Fig: A microcomputer system

282. Microprocessor Architecture
• The internal logic design of the microprocessor called
its architecture, determines how and when various
operations are performed by the microprocessor.
Fig: A microcomputer system

283. Microprocessor Architecture
• The microprocessor can be divided into three
segments, ALU, Register Array and Control Unit
Fig: A microcomputer system

284. Microprocessor Architecture
• ALU performs arithmetical and logical operations on the
data received from the memory or an input device.
• Register array consists of registers identified by letters
like B, C, D, E, H, L and accumulator.
• These registers are primarily used to store data
temporarily during the execution of a program.
• Some of the registers are accessible to the user through
instructions.
• The control unit controls the flow of data and
instructions within the computer.
• The control unit provides the necessary timing and
control signals to all the operations in the
microcomputer.

285. Microprocessor Architecture
• ALU performs arithmetical and logical operations on the
data received from the memory or an input device.
• Register array consists of registers identified by letters
like B, C, D, E, H, L and accumulator.
• These registers are primarily used to store data
temporarily during the execution of a program.
• Some of the registers are accessible to the user through
instructions.
• The control unit controls the flow of data and
instructions within the computer.
• The control unit provides the necessary timing and
control signals to all the operations in the
microcomputer.

286. Microprocessor Architecture
• The bus carries bits (data) between the
microprocessor and the memory and peripheral
devices.
Fig: Bus structure

287. Microprocessor Architecture
• The address bus is unidirectional- bits flow in one
directions- from microprocessor to peripheral devices.
Fig: Bus structure

288. Microprocessor Architecture
• The data bus is bidirectional- data flow in both
directions.
Fig: Bus structure

289. Microprocessor Architecture
• The control bus is contained of various single lines that
carry synchronization signals.
Fig: Bus structure

290. Microprocessor Architecture
• The fig. shows the internal registers and the
accumulator.
Fig: Registers

291. Microprocessor Architecture
• Accumulator: It is an 8-bit register used to perform
arithmetic, logical, I/O & LOAD/STORE operations. It is
connected to internal data bus & ALU.
Fig: Registers

292. Microprocessor Architecture
• General purpose register: There are 6 general purpose
registers in 8085 processor, i.e. B, C, D, E, H & L. Each
register can hold 8-bit data.
Fig: Registers

293. Microprocessor Architecture
• General purpose register: These registers can work in
pair to hold 16-bit data and their pairing combination
is like B-C, D-E & H-L.
Fig: Registers

294. Microprocessor Architecture
• Stack pointer: It is also a 16-bit register works like
stack, which is always incremented/decremented by 2
during push & pop operations.
Fig: Registers

295. Microprocessor Architecture
• Program counter: It is a 16-bit register used to store
the memory address location of the next instruction to
be executed.
Fig: Registers

296. Microprocessor Architecture
• Flag register: It is an 8-bit register having five 1-bit flip-
flops, which holds either 0 or 1 depending upon the
result stored in the accumulator.
Fig: Registers

297. Microprocessor Architecture
• Flag register:
• These are the set of 5 flip-flops:
Sign (S)
Zero (Z)
Auxiliary Carry (AC)
Parity (P)
Carry (C)
• Flag register reflect the results of computations (add,
subtract, multiply, divided) executed by the processor.
Fig: Flag Register

298. Microprocessor Architecture
• Carry (C): After addition the result is stored in the
accumulator. All flags are affected.
Fig: Flag Register

299. Microprocessor Architecture
• Carry (C): After subtraction the result is stored in the
A-register. All flags are affected.

300. Microprocessor Architecture
• if CF =1, then the result is positive and if CF =0, then
the result is negative.
• Since, the 8085 processor complements the carry after
subtraction, here if CF = 0, then the result is positive
and if CF = 1, then the result is negative.
• If the result is negative, then it will be in 2's
complement form.

301. Microprocessor Architecture
• if CF =1, then the result is positive and if CF =0, then
the result is negative.
• Since, the 8085 processor complements the carry after
subtraction, here if CF = 0, then the result is positive
and if CF = 1, then the result is negative.
• If the result is negative, then it will be in 2's
complement form.

302. Microprocessor Architecture

303. Microprocessor Architecture
Instruction register and decoder
• When an instruction is fetched from memory then it is
stored in the Instruction register. Instruction decoder
decodes the information present in the Instruction
register.

304. Microprocessor Architecture
Timing and control unit
• It provides timing and control signal to the
microprocessor to perform operations. Following are
the timing and control signals, which control external
and internal circuits −
 Control Signals: READY, RD’, WR’, ALE
 Status Signals: S0, S1, IO/M’
 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT

305. Microprocessor Architecture
Interrupt control
• As the name suggests it controls the interrupts during
a process. When a microprocessor is executing a main
program and whenever an interrupt occurs, the
microprocessor shifts the control from the main
program to process the incoming request. After the
request is completed, the control goes back to the
main program.
• There are 5 interrupt signals in 8085 microprocessor:
INTR, (INTA)’ RST 7.5, RST 6.5, RST 5.5, TRAP.

306. Microprocessor Architecture
Serial Input/output control
• It controls the serial data communication by using
these two instructions: SID (Serial input data) and SOD
(Serial output data).

307. Microprocessor Architecture-Pin Configuration

308. Address Bus and Data Bus
• A8 - A15 (Output):
• These are address bus and are used for the most
significant bits of the memory address or 8-bits of I/O
address. A8 –A15 are unidirectional buses.
• AD0 - AD7 (Input/output):
• These are time multiplexed address/data bus i.e. they
serve dual purpose.
• They are used for the least significant 8 bits of the
memory address or I/O address during the first cycle.
• Again they are used for data during 2nd and 3rd clock
cycles.
Microprocessor Architecture-Pin Configuration

309. Control and Status Signals
• ALE (Output): (Address Latch Enable). ALE goes high
during first clock cycle of a machine cycle and enables
the lower 8-bits of the address to be latched either into
the memory or external latch.
• IO/M (Output): It is a status signal which distinguishes
whether the address is for memory or I/O device.
• S0, S1 (Output): These are status signals sent by the
microprocessors to distinguish the various types of
operation:
Microprocessor Architecture-Pin Configuration
S1 S0 Operations
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH

310. Control and Status Signals
• RD (Output): RD is a signal to control READ operation.
When it goes low, the selected I/O device or memory
is read.
• WR (Output): WR is a signal to control WRITE
operation. When it goes low, the data bus' data is
written into the selected memory or I/O location.
• READY (Input): It is used by the microprocessor to
sense whether a peripheral is ready to transfer a data
or not. If READY is high, the peripheral is ready. If it is
low the micro processor waits till it goes high.
Microprocessor Architecture-Pin Configuration

311. Interrupts and Externally Initiated Signals
• HOLD (INPUT): HOLD indicates that another device is
requesting for the use of the address and data bus.
The processor relinquishes the uses of the buses as
soon as the current cycle is completed.
• HLDA (OUTPUT): HLDA is a signal for HOLD
acknowledgement which indicates that the HOLD
request has been received. After the removal of this
request the HLDA goes low.
• INTR (Input): INTR is an Interrupt Request Signal.
Among interrupts it has the lowest priority. The INTR is
enabled or disabled by software.
Microprocessor Architecture-Pin Configuration

312. Interrupts and Externally Initiated Signals
• INTA (Output): INTA is an interrupt
acknowledgement sent by the microprocessor after
INTR is received.
• RST 5.5, 6.5, 7.5 and TRAP (Inputs): These all are
interrupts.
• The TRAP has the highest priority among interrupts.
The order of priority of interrupts is as follows:
 TRAP (Highest priority)
 RST 7.5
 RST 6.5
 RST 5.5
 INTR (Lowest priority).
Microprocessor Architecture-Pin Configuration

313. Reset Signals
• RESET IN (Input): It resets the program counter (PC) to
0. It also resets interrupt enable and HLDA flip-flops.
• RESET OUT (Output): RESET OUT indicates that the
CPU is being reset. The signal can be used to reset
other devices.
Microprocessor Architecture-Pin Configuration

314. Clock Signals
• X1, X2 (Input): X1 and X2 are terminals to be connected
to an external crystal oscillator which drives an
internal circuitry of the microprocessor.
• It is used to produce a suitable clock for the operation
of microprocessor.
• CLK (Output): CLK is a clock output for user, which can
be used as the system clock for other digital ICs. Its
frequency is same at which processor operates.
Microprocessor Architecture-Pin Configuration

315. Serial I/O Signals
• SID (Input): SID is data line for serial input. The data
on this line is loaded into the seventh bit of the
accumulator when RIM instruction is executed.
• SOD (Output): SOD is a data line for serial output. The
seventh bit of the accumulator is output on SOD line
when SIM instruction is executed.
Power Supply
• Vcc : +5 Vlots supply
• Vss : ground reference
Microprocessor Architecture-Pin Configuration

316. Microprocessor - Classification
• A microprocessor can be classified into three
categories −
• RISC Processor: RISC (Reduced Instruction Set
Computer), Hardwired control unit
• CISC Processor: CISC (Complex Instruction Set
Computer), Programmed control unit
Fig: classification of microprocessor

317. Microprocessor - Classification
• Special Processors: These are the processors which are
designed for some special purposes.
• Input/Output Processor (DMA - direct Memory
Access)
• Coprocessor (math-coprocessor)
• Digital Signal Processor
Fig: classification of microprocessor

318. Modern Computing Architecture
Von Neumann Architecture
&
Flynn's classification

319. Von Neumann Architecture
• Von Neumann architecture was first published
by John von Neumann in 1945.
• Neumann architecture design consists of
 Control Unit,
 Arithmetic and Logic Unit (ALU),
 Memory Unit,
 Registers and
 Inputs/Outputs.
• Uses a single processor
• Uses one memory for both instructions and data.
• Executes programs following the fetch-decode-
execute cycle.

320. Von Neumann Architecture
• Von Neumann architecture is based on the stored-
program computer concept, where instruction data
and program data are stored in the same memory.
• Fixed Program Computers– Their function is very
specific and they couldn’t be programmed, e.g.
Calculators.
• Stored Program Computers– These can be
programmed to carry out many different tasks,
applications are stored on them. Programs and data
are stored in memory.

321. Von Neumann Architecture

322. Von Neumann Architecture
Registers
• Registers are high speed storage areas in the CPU. All
data must be stored in a register before it can be
processed.
MAR
Memory Address
Register
Holds the memory location of data that needs
to be accessed
MDR Memory Data Register
Holds data that is being transferred to or
from memory
AC Accumulator
Where intermediate arithmetic and logic results
are stored
PC Program Counter
Contains the address of the next instruction to
be executed
CIR
Current Instruction
Register
Contains the current instruction during
processing

323. Von Neumann Architecture
• Memory stores both the data values and the
program instructions.
• During execution, an instruction is read from the
memory and decoded, appropriate operands are
fetched from the memory, and, finally, the
instruction is executed.
• The main disadvantage is that memory bandwidth
becomes the bottleneck in such an architecture.
• Several memory buses and on-chip memories are
therefore used so that reads and writes to different
memory units can take place concurrently.

324. Von Neumann Architecture
• Two separate memories are used

325. Flynn's classification
• The most popular taxonomy of computer
architecture was defined by Flynn in 1966.
• Flynn's classification scheme is based on the notion
of a stream of information.
• Two types of information flow into a processor:
instructions and data.
• The instruction stream is defined as the sequence of
instructions.
• The data stream is defined as the sequence of data
and exchanged between the memory and the
processing unit.

326. Flynn's classification
• Instructions are decoded by the control unit and then
control unit send the instructions to the processing
units for execution.
• Data Stream flows between the processors and
memory bi directionally.
• A sequential computer which exploits no parallelism
in either the instruction or data streams.

327. Flynn's classification
• According to Flynn's classification, either of the
instruction or data streams can be single or multiple.
• Computer architecture can be classified into the
following four distinct categories:
1) Single Instruction Single Data Streams (SISD)
2) Single Instruction Multiple Data Streams (SIMD)
3) Multiple Instruction Single Data Streams (MISD)
4) Multiple Instruction Multiple Data Streams (MIMD)

328. Flynn's classification
1) Single Instruction Single Data Streams (SISD)
• A serial (non-parallel) computer
• Single Instruction: Only one instruction stream is
being acted on by the CPU during any one clock cycle
• Single Data: Only one data stream is being used as
input during any one clock cycle

329. Flynn's classification
1) Single Instruction Single Data Streams (SISD)
• This is the oldest type of computer
• Examples: older generation mainframes,
minicomputers, workstations and single
processor/core PCs.

330. Flynn's classification
2) Single Instruction Multiple Data Streams (SIMD)
• A type of parallel computer
• Single Instruction: All processing units execute the
same instruction at any given clock cycle
• Multiple Data: Each processing unit can operate on a
different data element

331. Flynn's classification
2) Single Instruction Multiple Data Streams (SIMD)
• Best suited for specialized problems characterized by
a high degree of regularity, such as graphics/image
processing.
• Two varieties: Processor Arrays and Vector Pipelines

332. Flynn's classification
2) Single Instruction Multiple Data Streams (SIMD)
• Processor Arrays: Thinking Machines CM-2, MasPar MP-1 & MP-2,
ILLIAC IV
• Vector Pipelines: IBM 9000, Cray X-MP, Y-MP & C90, Fujitsu VP, NEC
SX-2, Hitachi S820, ETA10
• Most modern computers, particularly those with graphics processor
units (GPUs) employ SIMD instructions and execution units.

333. Flynn's classification
3) Multiple Instruction Single Data Streams (MISD)
• A type of parallel computer
• Multiple Instruction: Each processing unit operates on
the data independently via separate instruction streams.
• Single Data: A single data stream is fed into multiple
processing units.

334. Flynn's classification
3) Multiple Instruction Single Data Streams (MISD)
• Few (if any) actual examples of this class of parallel computer
have ever existed.
• Some conceivable uses might be:
• multiple frequency filters operating on a single signal stream
• multiple cryptography algorithms attempting to crack a single
coded message.

335. Flynn's classification
4) Multiple Instruction Multiple Data Streams (MIMD)
• A type of parallel computer
• Multiple Instruction: Every processor may be executing a
different instruction stream
• Multiple Data: Every processor may be working with a
different data stream

336. Flynn's classification
4) Multiple Instruction Multiple Data Streams (MIMD)
• Execution can be synchronous or asynchronous,
deterministic or non-deterministic
• Currently, the most common type of parallel
computer - most modern supercomputers fall into
this category.

337. Flynn's classification
4) Multiple Instruction Multiple Data Streams (MIMD)
• Examples: most current supercomputers, networked
parallel computer clusters and "grids", multi-
processor SMP computers, multi-core PCs.
• Note: many MIMD architectures also include SIMD
execution sub-components

338. Flynn's classification
• Parallel computers are either SIMD or MIMD

339. Associative Memory

340. Associative Memory
• A memory unit accessed by content is called an
associative memory or content addressable memory
(CAM).
• This type of memory is accessed simultaneously and in
parallel on the basis of data content rather than by
specific address or location.
• The time required to find an item stored in memory can
be reduced considerably if stored data can be identified
for access by the content of the data itself rather than by
an address.
• When a word is written in an associative memory, no
address is given.

341. Associative Memory
• When a word is to be read from an associative memory,
the content of the word, or part of the word, is specified.
• The memory locates all words which match the specified
content and marks them for reading.
• An associative memory is more expensive than a RAM
because each cell must have storage capability as well as
logic circuits for matching its content with an external
argument.
• For this reason, associative memories are used in
applications where the search time is very critical and
must be very short.

342. Associative Memory
• The block diagram of an
associative memory is shown
in Fig. consists of a memory
array and logic for m words
with n bits per word.
• The argument register A and
key register K each have n bits,
one for each bit of a word.
• The match register M has m
bits, one for each memory
word.
Fig: Block diagram of associative memory.

343. Associative Memory
• Each word in memory is
compared in parallel with the
content of the argument
register.
• The words that match the bits
of the argument register set a
corresponding bit in the match
register.
• After the matching process,
those bits in the match register
that have been set indicate the
fact that their corresponding
words have been matched. Fig: Block diagram of associative memory.

344. Associative Memory
• The key register provides a
mask for choosing a particular
field or key in the argument
word.
• The entire argument is
compared with each memory
word if the key register
contains all 1's.
• Otherwise, only those bits in
the argument that have 1's in
their corresponding position
of the key register are
compared. Fig: Block diagram of associative memory.

345. Associative Memory
• For example, suppose that the
argument register A and the
key register K have the bit
configuration shown below.
• Only the three leftmost bits of
A are compared with memory
words because K has 1's in
these positions.
Fig: Block diagram of associative memory.

346. Associative Memory
• Reading is accomplished by a
sequential access to memory
for those words whose
corresponding bits in the
match register have been set.
Fig: Block diagram of associative memory.

347. Associative Memory
• The relation between the memory array and external registers
in an associative memory is shown in Fig.
• The cells in the array are marked by the letter C with two
subscripts. The first subscript gives the word number and the
second specifies the bit position in the word.
Fig: Associative memory of m word, n cells per word

348. Associative Memory
• The cell Cij is the cell for bit j in word i. A bit Aj in the
argument register is compared with all the bits in
column j of the array provided that Kj = 1. This is done
for all columns j = 1, 2, . . . , n.
Fig: Associative memory of m word, n cells per word

349. Associative Memory
• If a match occurs between all the unmasked bits of the argument
and the bits in word i, the corresponding bit M1 in the match
register is set to 1.
• If one or more unmasked bits of the argument and the word do
not match, M1 is cleared to 0.
Fig: Associative memory of m word, n cells per word

350. Associative Memory
• The internal organization of a typical cell Cij is shown in Fig.
• It consists of a flip-flop storage element Fij and the circuits for
reading, writing, and matching the cell.
• The input bit is transferred into the storage cell during a write
operation.
Fig: One cell of associative memory

351. Associative Memory
• The bit stored is read out during a read operation.
• The match logic compares the content of the storage cell
with the corresponding unmasked bit of the argument and
provides an output for the decision logic that sets the bit in
Mi.
Fig: One cell of associative memory

352. Associative Memory
• The match logic for each word can be derived from the
comparison algorithm for two binary numbers.
• First, we neglect the key bits and compare the
argument in A with the bits stored in the cells of the
words.
• Word i is equal to the argument in A if Ai = Fij for j = 1, 2,
. . . , n .
• Two bits are equal if they are both 1 or both 0.
• The equality of two bits can be expressed logically by
the Boolean function
• where xj = 1 if the pair of bits in position j are equal;
otherwise, xj = 0.

353. Associative Memory
• For a word i to be equal to the argument in A we must
have all xj variables equal to 1.
• This is the condition for setting the corresponding
match bit M, to 1.
• The Boolean function for this condition is

354. Associative Memory
• We now include the key bit Kj in the comparison logic.
• The requirement is that if Kj = 0, the corresponding bits
of Aj and Fij need no comparison.
• Only when Kj = 1 must they be compared. This
requirement is achieved by ORing each term with K’j
thus:
• When Kj = 1, we have K’j = 0 and xj + 0 = xj .
• When Kj = 0, then K’j = 1 and xj + 1 = 1.
• A term (xj + K’j) will be in the 1 state if its pair of bits is
not compared.

355. Associative Memory
• The match logic for word i in an associative memory
can now be expressed by the following Boolean
function:
• Each term in the expression will be equal to 1 if its
corresponding Kj = 0.
• If Kj = 1, the term will be either 0 or 1 depending on the
value of xj.
• A match will occur and Mi will be equal to 1 if all terms
are equal to 1 .

356. Associative Memory
• If we substitute the original definition of xj, the Boolean
function can be expressed as follows:

357. Associative Memory
• READ Operation:
• If more than one word in memory matches the
unmasked argument field, all the matched words will
have 1's in the corresponding bit position of the match
register.
• It is then necessary to scan the bits of the match
register one at a time.
• The matched words are read in sequence by applying a
read signal to each word line whose corresponding M,
bit is a 1.

358. Associative Memory
• READ Operation:
• In most applications, the associative memory stores a
table with no two identical items under a given key.
• In this case, only one word may match the unmasked
argument field.
• By connecting output Mi directly to the read line in the
same word position (instead of the M register)
• The content of the matched word will be presented
automatically at the output lines and no special read
command signal is needed.

359. Associative Memory
• WRITE Operation:
• An associative memory must have a write capability for
storing the information to be searched.
• Writing in an associative memory can take different
forms, depending on the application.
• If unwanted words have to be deleted and new words
inserted one at a time, there is a need for a special
register to distinguish between active and inactive
words.
• This register, sometimes called a tag register, would
have as many bits as there are words in the memory.
• For every active word stored in memory, the
corresponding bit in the tag register is set to 1.

360. Associative Memory
• WRITE Operation:
• A word is deleted from memory by clearing its tag bit to
0.
• Words are stored in memory by scanning the tag
register until the first 0 bit is encountered.
• This gives the first available inactive word and a
position for writing a new word.

361. Data Transfer Modes
Programmed I/O, Interrupt-initiated I/O
&
Direct memory access (DMA)

362. Data Transfer Modes
• Data transfer between the central computer and I/O
devices may be handled in a variety of modes.
1) Programmed I/O
2) Interrupt-initiated I/O
3) Direct memory access (DMA)

363. Programmed I/O
• In the programmed I/O method, the I/O device does
not have direct access to memory.
• Each data item transfer is initiated by an instruction
in the program.
• Usually, the transfer is to and from a CPU register and
peripheral.
• Transferring data under program control requires
constant monitoring of the peripheral by the CPU.
• Once a data transfer is initiated, the CPU is required
to monitor the interface to see when a transfer can
again be made.

364. Programmed I/O
• The device transfers bytes of data one at a time as
they are available.
• When a byte of data is available, the device places it
in the I/O bus and enables its data valid line.
• The interface accepts the byte into its data register
and enables the data accepted line.
• The interface sets a bit in the status register that we
will refer to as an F or "flag" bit.
Fig: Data transfer from I/O device to CPU

365. Programmed I/O
• The I/O device can now disable the data valid line,
but it will not transfer another byte until the data
accepted line is disabled by the interface.
• CPU checks the flag in the status register to
determine if a byte has been placed in the data
register by the I/O device.
• This is done by reading the status register into a CPU
register and checking the value of the flag bit.
Fig: Data transfer from I/O device to CPU

366. Programmed I/O
• If the flag is equal to 1, the CPU reads the data from
the data register.
• When the flag is cleared, the interface disables the
data accepted line and the device can then transfer
the next data byte.
• The programmed I/O method is particularly useful in
small low-speed computers or in systems that are
dedicated to monitor a device continuously.
Fig: Data transfer from I/O device to CPU

367. Programmed I/O
• The transfer of each byte
requires three instructions:
1.Read the status register.
2.Check the status of the flag
bit and branch to step 1 if
not set or to step 3 if set.
3.Read the data register
• Each byte is read into a CPU
register and then transferred
to memory with a store
instructions.
Fig: Flowchart for CPU program to input data

368. Programmed I/O
• This type of transfer is inefficient because of the
difference in information transfer rate between the
CPU and the I/O device.
• CPU stays in a program loop until the I/O unit
indicates that it is ready for data transfer.
• This is a time-consuming process since it keeps the
processor busy needlessly.

369. Interrupt-initiated I/O
• Interrupt-initiated I/O can overcome the limitations
of Programmed I/O.
• It uses an interrupt facility and special commands to
inform the interface to issue an interrupt request
signal when the data are available from the device.
• In the meantime the CPU can proceed to execute
another program.
• The interface meanwhile keeps monitoring the
device.
• When the interface determines that the device is
ready for data transfer, it generates an interrupt
request to the CPU.

370. Direct Memory Access
• Transfer of data under programmed I/O is between
CPU and peripheral.
• In direct memory access (DMA), the interface
transfers data into and out of the memory unit
through the memory bus.
• The transfer of data between a fast storage device
such as magnetic disk and memory is often limited
by the speed of the CPU.
• Removing the CPU from the path and letting the
peripheral device manage the memory buses
directly would improve the speed of transfer.

371. Direct Memory Access
• During the DMA transfer, the CPU is idle and has no
control of the memory buses.
• A DMA Controller takes over the buses to manage
the transfer directly between the I/O device and
memory.
• Two control signals in the CPU that facilitates the
DMA transfer.
• The Bus Request (BR) input is used by the DMA
controller to request the CPU.

372. Direct Memory Access
• When BR input is active, the CPU terminates the
execution of the current instruction and places the
address bus, data bus and read write lines into a
high Impedance state.
• High Impedance state means that the output is
disconnected.
Fig: CPU bus signals for DMA transfer

373. Direct Memory Access
• The CPU activates the Bus Grant (BG) output to inform the
external DMA that the Bus Request (BR) can now take
control of the buses to conduct memory transfer without
processor.
• When the DMA terminates the transfer, it disables the Bus
Request (BR) line.
• The CPU disables the Bus Grant (BG), takes control of the
buses and return to its normal operation.
Fig: CPU bus signals for DMA transfer

374. Direct Memory Access
The transfer can be made in several ways that are:
i. DMA Burst
ii. Cycle Stealing
i) DMA Burst :- In DMA Burst transfer, a block sequence
consisting of a number of memory words is
transferred in continuous burst while the DMA
controller is master of the memory buses.
ii) Cycle Stealing :- Cycle stealing allows the DMA
controller to transfer one data word at a time, after
which it must returns control of the buses to the
CPU.

375. Direct Memory Access Controller
• The DMA controller has three registers:
i. Address Register: contains an address to specify the
desired location in memory.
ii. Word Count Register: holds the number of words to
be transferred. The register is increment/decrement
by one after each word transfer and internally tested
for zero.
iii. Control Register: specifies the mode of transfer
• When the BG (Bus Grant) input is 0, the CPU can
communicate with the DMA registers through the data
bus to read from or write to the DMA registers.
• When BG =1, the DMA can communicate directly with
the memory by specifying an address in the address
bus and activating the RD or WR control.

376. Direct Memory Access Controller
• The CPU communicates with the DMA through the
address and data buses as with any interface unit.
The DMA has its own address, which activates the DS
and RS lines.
Fig: Block diagram of DMA Controller

377. Direct Memory Access Controller
• The CPU initializes the DMA through the data bus.
• Once the DMA receives the start control command, it
can transfer between the peripheral and the memory.
Fig: Block diagram of DMA Controller

378. Sequential circuits

379. Sequential circuits
• Sequential Circuit Models
• Latches
• Flip-Flops

380. Sequential circuits
• The main characteristic of combinational
logic circuits is that their output values
depend on their present input values.
• Sequential logic circuits differ from
combinational logic circuits because they
contain memory elements so that their
output values depend on both present and
past input values.

381. Sequential circuits
Sequential circuits can be Synchronous or
Asynchronous.
Synchronous sequential circuits change their
states and output values at fixed points of time,
i.e. clock signals.
Asynchronous sequential circuits change their
states and output values whenever a change in
input values occurs.
– Asynchronous sequential circuit: circuit output
can change at any time (clockless).

382. Latch vs flip-flop
• A Latch or Flip-flop is use to store one bit of
information.
Latches: Latches are “transparent” (= any change on the
inputs is seen at the outputs immediately).
This causes synchronization problems.
A latch has two stages set and reset.
Set stage sets the output to 1.
Reset stage set the output to 0 (Clear to 0).
Flip-flops : A flip-flop is a memory device that has
clock signals control the state of the device.
Clocked sequential circuit (Synchronous).

383. Types of Flip flops
• SR Flip-Flop
• D Flip-Flop
• JK Flip-Flop
• T Flip-Flop

384. SR (Set-Reset) Flip-flop
• SR Flip-Flop has three inputs, S (for set), R
(for reset), and C (for Clock).
• It has an output Q.
Fig: Graphic symbol
Fig: Characteristic Table
• Rarely used due to indeterminate condition.

385. D (Data) Flip-flop
• D Flip-Flop is a slight modification of SR
flip-flop.
• D Flip-Flop is created by inserting an
inverter between S and R.
Fig: SR flip-flop Fig: D flip-flop
D

386. D (Data) Flip-flop
Fig: Characteristic Table
Fig: Graphic symbol
• The output of the D flip-flop is determined by input D.
• The output can be expressed by
Q(t+1)=D
• No input condition exists for unchanged and
indeterminate.

387. JK (Jack-Kilby) Flip-flop
• JK Flip-Flop is a refinement of SR flip-flop.
• When inputs J and K are both equal to 1, it
complement the state.
Fig: Graphic symbol Fig: Characteristic Table

388. T(Toggle) Flip-flop
• T Flip-Flop is a slight modification of JK flip-flop.
• Input JK are connected to provide a single input by T.
• Only has two input conditions T=0 (J=K=0) and T=1
(J=K=1).
• The output can be expressed by Q(t+1)=Q(t)  T.
Fig: Graphic symbol Fig: Characteristic Table

389. Combinational Circuits

390. Circuits
• Combinational Circuit:
output of this circuit mainly depends on the
input terminals at any time.
• n binary input variables come and m binary output
variables go out.
• This circuit doesn’t include any memory.

391. Adder
An adder is a digital logic circuit that is used
for the addition of numbers.
Adders are basically classified into two
types:
• Half-Adder
• Full-Adder.

392. Half-Adder
Half Adder performs the arithmetic addition
of two bits.
• The half adder accepts two binary digits
on its inputs and produce two binary digits
outputs, sum (S) and carry (C) bit.
• The carry (C) output is 0 unless both the
inputs are 1.
• S represents the least significant bit of the
sum.

393. Half-Adder
Logical Expression of Half-Adder:
Sum (S) = AB + AB = A  B
Carry (C) = A B = A AND B
A B C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Table: Truth Table Fig: Block diagram of Half-Adder

394. Half-Adder
Logical Expression of Half-Adder:
Sum (S) = AB + AB = A  B
Carry (C) = A B = A AND B
A B C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Table: Truth Table Fig: Logic diagram of Half-Adder

395. Full-Adder
Full Adder performs the arithmetic sum of
three bits.
• The Full-Adder accepts three inputs and
produce two outputs.
• The S output is equal to 1 when only one
input is equal to 1 or when all three inputs
are equal to 1.
• The C output has carry of 1 if two or three
inputs are equal to 1.

396. Full-Adder
Logical Expression of Full-Adder:
Sum (S) = ABCi n +AB Ci n  AB
Ci n + ABCi n = A  B 
Ci n
Carry (Cout) = A B +A Ci n + B Ci n
Table: Truth Table
Fig: Block diagram of Full-Adder
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

397. Full-Adder
Logical Expression of Full-Adder:
Sum (S) = ABCi n +AB Ci n  AB Ci n +
ABCi n = A  B  Ci n
Carry(Cout)=AB+ACi n +BCi n =A B+
(AB+AB)Cin
Table: Truth Table
Fig: Logic diagram of Full-Adder
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
=A B+(A  B )Cin

398. Subtractor
Subtractor: each subtrahend bit of the number
is subtracted from its corresponding significant
minuend bit to form a difference bit.
• If the minuend bit is smaller than the
subtrahend bit, a 1 is borrowed from the next
significant position.
• Half-Subtractor
• Full-Subtractor.

399. Half-Subtractor
A half-subtractor is a circuit that subtracts two
bits and produces their difference.
• The half-subtractor needs two outputs.
One output generates the difference (D).
The second output for borrow (B).
• To perform x-y, we have to check the
relative magnitudes of x and y. If x>= y, we
have three possibilities:
0-0=0, 1-0=1 and 1-1=0.
• If x<y, we have 0-1 and it is necessary to
borrow a 1 from the next higher stage.

400. Half- Subtractor
Logical Expression of Half-Subtractor:
Difference (D) = xy +xy = A  B
Borrow (B) = xy = x AND y
x y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
Table: Truth Table
Fig: Block diagram of Half-Subtractor

401. Half- Subtractor
Logical Expression of Half-Subtractor:
Difference (D) = xy +xy = A  B
Borrow (B) = xy = x AND y
x y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
Table: Truth Table Fig: Logic diagram of Half-Subtractor

402. Full-Subtractor
A Full-subtractor performs a subtraction
between two bits and taking into account the
borrow bit.
• This circuit has three inputs and two outputs
• The three inputs x, y and Bin, where Bin is
previous borrow.
• The two outputs, D and Bout represent the
difference and output borrow, respectively.

403. Full-Subtractor
Logical Expression of Full-Subtractor:
Difference (D) = xy Bin +xy Bin 
xy Bin + xy Bin = x 
y  Bin
Borrow (Bout) = x y +x Bin + y Bin
Table: Truth Table
Fig: Block diagram of Full-Subtractor
x y Bin Bout D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

404. Full-Subtractor
Logical Expression of Full-Subtractor:
Difference (D) = xy Bin +xy Bin  xy Bin
+ xy Bin = x  y  Bin
Borrow (Bout) = x y+( x  y)Bin
Table: Truth Table
Fig: Logic diagram of Full-Subtractor
x y Bin Bout D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

405. Combinational Circuits
(Decoder and Encoder)

406. Decoder
• The name Decoder means to translate or decode
coded information from one format into another.
• A decoder is a combinational circuit that converts
binary information from n input lines to a
maximum of 2n
unique output lines.
• n inputs
• 2n
outputs
• If a binary decoder receives n inputs it activates one
and only one of its 2n
outputs based on that input
with all other outputs deactivated.
• A decoder has n inputs and m outputs is referred to
as an n × m decoder

407. Decoder

408. Decoder

409. Decoder with Enable input
• Decoders include one or more enable inputs to
control the operation of the circuit.
• The decoder is enabled when E is equal to 1 and
disabled when E is equal to 0.
En A B W X Y Z
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 x x 0 0 0 0
enabled
disabled
high-level
enable
Enable
B W
X
Y
Z
I0
I1
A
Out0
Out1
Out2
Out3
En

410. Decoder with Enable input
En A B W X Y Z
0 0 0 1 0 0 0
0 0 1 0 1 0 0
0 1 0 0 0 1 0
0 1 1 0 0 0 1
1 x x 0 0 0 0
enabled
disabled
Enable
B W
X
Y
Z
I0
I1
A
Out0
Out1
Out2
Out3
En
low-level
enable

411. 3-to-8 line Decoder

412. Encoder
• Encoder is a combinational circuit that perform the
inverse operation of the decoder.
• An encoder has 2n
input lines and n output lines.
• Encoders assume that only one input line is active
at a time.

413. 4 × 2 Encoder

414. 8 × 3 Encoder

415. Encoder Design Issues
There are two ambiguities associated with the design
of a simple encoder:
• Only one input can be active at any given time. If
two inputs are active simultaneously, the output
produces an undefined combination (for example, if
D3 and D6 are 1 simultaneously, the output of the
encoder will be 111.
• An output with all 0's can be generated when all the
inputs are 0's,or when D0 is equal to 1.

416. Priority Encoder
• Multiple asserted inputs are allowed; one has
priority over all others.
• Separate indication of no asserted inputs.
• A priority encoder is a special type of encoder that
includes the priority function.
• If two or more inputs are equal to 1 at the same
time, the input having the highest priority will take
precedence.

417. Priority Encoder

418. Valid-output indicator
A valid-output indicator, designed by V, is set to 1 only
when one or more of the inputs are equal to 1. If all
inputs are 0, V is equal to 0 and the other outputs of
the circuit are not used.

419. Combinational Circuits
(Multiplexer and De-
Multiplexer )

420. Multiplexer
• A Multiplexer is a combinational circuit that selects
binary information from one of many input lines
and directs it to a single output line.
• 2n
input lines
• 1 output line
• n selection lines: combinations determine which
input is selected.
• Multiplexers are also known as parallel to serial
convertor, data selector and many to one circuit.
• often abbreviated as MUX.

421. 4-to-1-line Multiplexer
• Input lines = 4
• Selection lines = 2
Table: Truth table
Fig: Block diagram

422. 4-to-1-line Multiplexer
Table: Truth table
Fig: Logical diagram
• Similarly, you can implement 8x1
Multiplexer and 16x1 multiplexer by
following the same procedure.

423. Multiplexer with enable input
• As in decoders, multiplexer circuits may have an
enable input to control the operation.
• When the enable input is in the inactive state, the
outputs are disabled.
• When it is in the active state, the circuit functions as
a normal multiplexer.

424. Implement of higher-order Multiplexers using
lower-order Multiplexers.
 Implement 8x1 Multiplexer using 4x1 Multiplexers and
2x1 Multiplexer.
• We know that 4x1 Multiplexer has 4 data inputs, 2
selection lines and one output. Whereas, 8x1
Multiplexer has 8 data inputs, 3 selection lines and
one output.
• So, we require two 4x1 Multiplexers.
• Each 4x1 Multiplexer produces one output, we require
a 2x1 Multiplexer considering the outputs of 4x1
Multiplexers as inputs and to produce the final output.

425. Implement of higher-order Multiplexers using
lower-order Multiplexers.
 Implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1
Multiplexer. Selection Inputs Outp
ut
S2 S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

426. Applications of Multiplexer
• Signal routing
• Data communications (Time Division Multiplexing)
• Data bus control
Advantage of Multiplexer
• Only one serial data line is required instead of
multiple parallel data lines.

427. Demultiplexer
• A demultiplexer is a circuit that receives information
on a single line and transmits this information on
one of the 2n
possible output lines.
• Reverse of the Multiplexer
• 1 input line
• 2n
output lines
• n selection lines: combinations determine which
output line is selected.
• Demultiplexers are also known as serial to parallel
convertor, Data Distributor and one to many
circuit.
• often abbreviated as Demux.

428. 1-to-4-line Demultiplexer
• Output lines = 4
• Selection lines = 2
Table: Truth table
Fig: Block diagram
A B Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

429. 1-to-4-line Demultiplexer
Table: Truth table
A B Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Fig: Logical diagram • Similarly, you can implement 1x8
Demultiplexer and 1x16
Demultiplexer by following the same
procedure.

430. Demultiplexer with enable output
• Demultiplexer circuits may have an enable output
to control the operation.
• When the enable output is in the inactive state, the
outputs are disabled.
• When it is in the active state, the circuit functions as
a normal Demultiplexer.

431. Difference between of Multiplexer and Demultiplexer
MULTIPLEXER DEMULTIPLEXER
Multiplexer processes the digital
information from various sources into a
single source.
Demultiplexer receives digital information
from a single source and converts it into
several sources
It is known as Data Selector It is known as Data Distributor
It follows combinational logic type It also follows combinational logic type
It has n data input It has single data input
It has a single data output It has n data outputs
It works on many to one operational
principle
It works on one to many operational
principle
In time division Multiplexing, multiplexer
is used at the transmitter end
In time division Multiplexing,
demultiplexer is used at the receiver end

432. Sequential Logic Circuit
(Shift Register)

433. Register
• Flip-flop: A flip-flop can store one-bit of
information.
• Register: Group of flip-flops are used to store the
binary data. To store multiple bits of information,
we need multiple flip-flops.
• n-bit register has a group of n flip-flops and is
capable of storing of information of n bits.
 Storage.

434. Register
Fig: 4-bit Register
• Load: Transfer of new
information into a register.
• Clear: Clear the register to all
0’s .
• Clock pulse: Applied to all
flip-flops.
• Load all four inputs in
parallel.

435. Shift Register
• Shift Register: The Shift Register is another type of
sequential logic circuit that can be used for the
storage or the transfer of binary data.
• Shift Register: A register capable of shifting its binary
information either to the right or to the left.
 Storage or the transfer
• Shift Register loads the data present on its inputs and
then moves or “shifts” it to its output once every clock
cycle.
• The logical configuration of a shift register consists of
a chain of flip-flops connected in cascade, with the
output of one flip-flop connected to the input of the
next flip-flop.

436. Shift Register
• Direction or Date shifting
 Left shift
 Right shift
 Rotate (right or left)
 Bidirectional

437. Shift Operation
• A single shift is multiplication by 2
• Consider the operation 6 x 2 = 12
0110
x 0010
0000
0110
01100

438. Shift Operation
In binary number we can move or shift the binary
point:
 Right by 1 position to multiply by 2
 Left by 1 position to divide by 2
Move or shift the binary point:
Left by 1 position to multiply by 2
1110 x 2  11100.
Right by 1 position to divide by 2
11100 ¸ 2  1110.

439. Types of Shift Register
• Shift registers operate in one of four different
modes with the basic movement of data.
 Serial-in, Serial-out
 Serial-in, Parallel-out
 Parallel-in, Serial-out
 Parallel-in, Parallel-out

440. Serial-In Serial-Out
• Data bits come in one at a time and leave one at a
time.
• One Flip-Flop is used to handle each bit.
• The output of a Flip-Flop is connected to the D input
of the Flip-Flop at its right.

441. Example
• The 4-bit data word “1011”
is to be shifted into a 4-bit
shift register.
• One shift per clock pulse.
• Data is shown entering at
left and shifting right.

442. Serial-In Parallel -Out
• Serial-in to Parallel-out (SIPO) - the register is loaded
with serial data, one bit at a time, with the stored data
being available at the output in parallel form.
• Shift the data contents of each stage one place.
• Data value can now be read directly from the outputs.

443. Parallel-In Serial-Out
• Parallel-in to Serial-out (PISO)- the parallel data is
loaded into the register simultaneously and is shifted
out of the register serially one bit at a clock pulse.
• Act in the opposite way to the serial-in parallel-out
• Data is loaded in a parallel format in which all the data
bits enter their inputs simultaneously.
• The data is then read out sequentially in the normal
shift-right mode.

444. Parallel -In Parallel -Out
• Parallel-in to Parallel-out (PIPO)- the parallel data is
loaded simultaneously into the register, and
transferred together to their respective outputs by the
same clock pulse.
• One clock pulse loads and unloads the register.
• No interconnections between the individual flip-flops
since no serial shifting of the data is required.

445. Universal Shift Register
• Universal shift register can do any combination of
parallel and serial input/output operations.
• Can be used in either serial-to-serial, serial-to-parallel,
parallel-to-serial, or as a parallel-to-parallel data
shifting.
• Requires additional inputs to specify desired function.
• Universal shift registers are frequently used in
arithmetic operations to shift data to the left or right
for multiplication or division.

446. Sequential Logic Circuit
(Counters)

447. Counters
• Counter is a sequential circuit.
• Counter is a digital circuit used for counting purpose,
they can count specific event happening in the
circuit.
• Counters calculate or note down the number that
how many times an event occurred.
• Counting means incrementing or decrementing the
values of an operator, with respect to its previous
state value.
• Counters are well known as Timers.
• Counter is the widest application of flip-flops.

448. Types of counters
Depending on the type of clock inputs, counters are of
two types:
 Asynchronous counters
 Synchronous counters
Depending on the way in which the counting
progresses, the synchronous or asynchronous
counters are classified as follows −
 Up counters
 Down counters
 Up/Down counters or Bidirectional Counters

449. Up-Counter:
• An up-counter counts events in increasing order.
• The binary count is incremented by 1 with every input
clock pulse.
Down-Counter:
• A down-counter counts events in the decreasing order.
• A binary counter with a reverse count. In a down-
counter, the binary count is decremented by 1 with
every input clock pulse.
Up-Down-Counter:
• An up-down counter is a combination of an up-counter
and a down-counter. It can count in both directions,
increasing as well as decreasing.

450. Asynchronous Counters
• Clock input of the flip-flops are not all driven by the
same clock signal, therefore called Asynchronous
Counters.
• The counters in which the change in transition
doesn’t depend upon the clock signal input is
known as “Asynchronous counters”.
• Asynchronous Counters use flip-flops which are
serially connected together so that the input clock
pulse appears to ripple through the counter.
• Asynchronous counters don’t use universal clock,
only first flip flop is driven by main clock.

451. Asynchronous Counters
• All J and K inputs are equal to 1.
• The lowest-order bit A1 must be complemented with
each count pulse. Every time A1 goes from 1 to 0, it
complements A2. Every time A2 goes from 1 to 0, it
complements A3, and so on.
• The flip-flops change one at a time in rapid succession,
and the signal propagates through the counter in a
ripple fashion So asynchronous counters are also called Fig: 4-bit Ripple counter

452. Asynchronous Counters
Fig: Timing Diagram

453. Synchronous Counters
• All flip flops in the synchronous counters are
triggered by same clock signal.
• Synchronous Counters are so called because the
clock input of all the individual flip-flops within the
counter are all clocked together at the same time
by the same clock signal.
• Synchronous Counter, the external clock signal is
connected to the clock input of EVERY individual
flip-flop within the counter so that all of the flip-
flops are clocked together simultaneously (in
parallel) at the same time giving a fixed time
relationship.

454. Synchronous Counters
• The flip-flop in the lowest-order position is
complemented with every pulse.
• A flip-flop in any other position is
complemented with a pulse provided all
the bits in the lowest-order position are
equal to 1, because the lowest-order bits
(when all 1's) will change to 0's on the next
count pulse.
• Synchronous binary counters have a
regular pattern and can easily be
constructed with complementing flip-flops
and gates.
• Synchronous Counters are faster and more
reliable as they use the same clock signal
for all flip-flops.
Fig: 4-bit Synchronous Counter

455. Asynchronous Vs Synchronous Counters
SYNCHRONOUS COUNTERS ASYNCHRONOUS COUNTERS
All flip-flops are given the same
clock simultaneously
The flip-flops are not given the same
clock
There is no connection between
the output of a flip-flop and the
clock input of the next flip-flop.
The output of a flip-flop is given as
the clock input to the next flip-flop
These are faster than that of ripple
counters.
These are slow in operation.
Large number of logic gates are
required to design
Less number of logic gates required.
It is known as a parallel counter It is known as a serial counter
Synchronous circuits are easy to
design.
Complex to design.
Standard logic packages available
for synchronous.
For asynchronous counters, Standard
logic packages are not available.

456. Application of counters
• Digital clock
• Time measurement
• Frequency counters
• Analog to digital convertors.
• Frequency divider circuits
• Digital triangular wave generator.
• In time measurement. That means calculating time
in timers such as electronic devices like ovens and
washing machines.

457. (Instruction Codes, Registers, Common bus system,
Computer Instructions, Control Unit with Timing
and
Instruction Cycle,)
Basic Computer Organization

458. Instruction Codes
• The organization of the computer is defined by its
internal registers, the timing and control structure,
and the set of instructions that it uses.
• The Internal organization of a digital system is
defined by the sequence of micro-operations it
performs on data stored in its registers.
• The user of a computer can control the process by
means of a program.
• A program is a set of instructions that specify the
operations, operands, and the processing
sequence.

459. Instruction Codes
• A computer instruction is a binary code that
specifies a sequence of micro-operations for the
computer. Each computer has its unique instruction
set.
• Instruction codes and data are stored in memory.
• The computer reads each instruction from memory
and places it in a control register.
• The control unit interprets the binary code of the
instruction and proceeds to execute it by issuing a
sequence of micro-operations.

460. Instruction Codes
• An Instruction code is a group of bits that instructs
the computer to perform a specific operation.
• The most basic part of an instruction code is its
operation code part.
• The operation code of an instruction is a group of
bits that defines certain operations such as add,
subtract, shift, and complement.

461. Instruction Codes
• The number of bits required for the operation code
depends on the total number of operations
available in the computer.
• 2n
(or little less) distinct operations
n bit operation code

462. Instruction Codes
• An operation must be performed on some data
stored in processor registers or in memory.
• An instruction code must therefore specify not only
the operation, but also the location of the operands
(in registers or in the memory), and where the result
will be stored (registers/memory)

463. Instruction Codes
• An instruction code is usually divided into operation
code, operand address and addressing mode.
• The simplest way to organize a computer is to have
one processor register (Accumulator AC) and an
instruction code format with two parts (op code,
address)

464. Stored Program Organization
Opcode Address
Instruction Format
Binary Operand
Operands
(data)
Processor register
(Accumulator AC)
Memory
4096x16
15 12 11 0
15 0
Instructions
(program)
15 0
0
15

465. Indirect Address
• There are three Addressing Modes used for
address portion of the instruction code:
Immediate: the operand is given in the address
portion.
Direct: the address points to the operand stored in
the memory.
Indirect: the address points to the pointer (another
address) stored in the memory that references the
operand in memory.
• One bit of the instruction code can be used to
distinguish between direct & indirect addresses

466. Indirect Address
Opcode Address
Instruction Format
15 14 12 0
I
11
0 ADD 457
22
Operand
457
1 ADD 300
35
1350
300
Operand
1350
+
AC
+
AC
Direct Address Indirect address

467. Indirect Address
• Effective address: the address of the operand in a
computation-type instruction or the target address in
a branch-type instruction
• The pointer can be placed in a processor register
instead of memory.

468. Computer Registers
• Computer instructions are normally stored in
consecutive memory locations and executed
sequentially one at a time.
• The control reads an instruction from a specific address
in memory and executes it.
• This type of sequencing needs a counter to calculate
the address of the next instruction after execution of
the current instruction is completed.
• It is also necessary to provide a register in the control
unit for storing the instruction code after it is read from
memory.
• The computer needs processor registers for
manipulating data and a register for holding a memory
address.

469. Registers for the Basic Computer

470. Computer Registers
• The memory unit has a capacity of 4096 words and
each word contains 16 bits.
• 12 bits of an instruction word are needed to specify
the address of an operand.
• This leaves three bits for the operation part of the
instruction and a bit to specify a direct or indirect
address.
• The data register (DR) holds the operand read from
memory.
• The accumulator (AC) register is a general-purpose
processing register.
• The instruction read from memory is placed in the
instruction register (IR).

471. Computer Registers
• The temporary register (TR) is used for holding
temporary data during the processing.
• The memory address register (AR) has 12 bits since
this is the width of a memory address.
• The program counter (PC) also has 12 bits and it
holds the address of the next instruction to be read
from memory after the current instruction is
executed.
• The PC goes through a counting sequence and
causes the computer to read sequential instructions
previously stored in memory.
• Instruction words are read and executed in
sequence unless a branch instruction is
encountered.

472. Computer Registers
• Two registers are used for input and output.
• The input register (INPR) receives an 8-bit character
from an input device.
• The output register (OUTR) holds an 8-bit character
for an output device.

473. Common Bus System
• The basic computer has eight registers, a memory
unit, and a control unit
• Path must be provided to transfer information form
one register to another register and between
memory and registers.
• The number of wires will be excessive if connections
are made between the outputs of each register and
the inputs of the other registers.
• A more efficient scheme for transferring information
in a system with many registers is to use a common
bus system.
• A common bus can be constructed using multiplexers
or three-state-buffer gates.

474. Basic computer registers connected to a common bus

475. Common Bus System
• S2S1S0: Selects the
register/memory that
would use the bus.
• LD (load): When
enabled, the
particular register
receives the data
from the bus during
the next clock pulse
transition.
• The memory receives
the contents of the
bus when its write
input is activated.

476. Common Bus System
• The memory places its
16-bit output onto the
bus when the read
input is activated and
S2S1S0=111.
• DR, AC, IR, and TR have
16 bits each.
• AR and PC: have 12 bits
each since they hold a
memory address

477. • When the contents
of AR or PC are
applied to the 16-bit
common bus, the
four most significant
bits are set to zeros.
• When AR or PC
receives information
from the bus, only
the 12 least
significant bits are
transferred into the
register.
Common Bus System

478. • INPR and OUTR:
communicate with the
eight least significant
bits in the bus.
• INPR: Receives a
character from the
input device
(keyboard,…etc) which
is then transferred to
AC.
• OUTR: Receives a
character from AC and
delivers it to an output
device (say a Monitor).
Common Bus System

479. • The common bus receive
information from six
registers and the
memory unit. The bus
lines are connected to
the inputs of six registers
and the memory.
• Five registers have three
control inputs: LD (load),
INR (increment), and CLR
(clear). This type of
register is equivalent to a
binary counter with
parallel load and
synchronous clear.
Common Bus System

480. • The increment
operation is achieved
by enabling the count
input of the counter.
• Two registers have
only a LD input.
Common Bus System

481. • The input data and
output data of the
memory are
connected to the
common bus.
• But the memory
address is connected
to AR.
Common Bus System

482. • Therefore, AR must
always be used to
specify a memory
address.
• By using a single
register for the
address, we eliminate
the need for an
address bus that
would have been
needed otherwise.
Common Bus System

483. • Register  Memory:
Write operation
• Memory  Register:
Read operation (note
that AC cannot
directly read from
memory)
• The 16-bit inputs of
AC come from an
adder and logic
circuit. The circuit has
three sets of inputs.
Common Bus System

484. • One set of 16-bit
inputs come from the
outputs of AC.
• They are used to
implement register
micro-operations
such as complement
AC and shift AC.
• The inputs from DR
and AC are used for
arithmetic and logic
micro-operations,
such as add DR to AC,
etc.
Common Bus System

485. • The result of an addition
is transferred to AC and
the end carry-out of the
addition is transferred
to flip-flop E (extended
AC bit).
• The third set of 8-bit
inputs come from the
input register INPR.
Common Bus System

486. • The content of any
register can be applied
onto the bus and an
operation can be
performed in the adder
and logic circuit during
the same clock cycle
Common Bus System

487. Computer Instructions
• An Instruction is a group of bits that instructs the
computer to perform a specific operation.
• The most basic part of an instruction is its operation
code part.
• The operation code of an instruction is a group of
bits that defines certain operations such as add,
subtract, shift, and complement.

488. Computer Instructions
• The number of bits required for the operation code
depends on the total number of operations
available in the computer.
• 2n
(or little less) distinct operations
n bit operation code

489. Fig: Basic computer instruction formats
Computer Instructions
The basic computer has three instruction code formats
• Each format has 16 bits.

490. Fig: Basic computer instruction formats
Computer Instructions
A memory-reference instruction uses one bit to specify
the addressing mode I. I = 0 for direct, 1=Indirect

491. Fig: Basic computer instruction formats
Computer Instructions
A register-reference instruction specifies an operation
on AC, other 12 bits are used to specify the operation

492. Fig: Basic computer instruction formats
Computer Instructions
An IO instruction does not need a reference to memory,
remaining 12 bits are used to specify the type of IO operation

493. Basic computer instructions

494. Basic Computer Instructions
The 16 bits of an instruction code is reduced to
equivalent four digits hexadecimal digits.
• Memory-reference: the address part is
denoted by three x’s and stand for the three
hexadecimal digits.
• Register-reference: The leftmost four bits are
always 0111, which is equivalent to
hexadecimal 7.
• Input-output: The last four bits are always
1111, equivalent to hexadecimal F.

495. Control Unit with Timing
• The timing for all registers in the basic computer is
controlled by a master clock generator.
• The clock pulses are applied to all flip-flops and
registers in the system, including the flip-flops and
registers in the control unit.
• The clock pulses do not change the state of a register
unless the register is enabled by a control signal (i.e.,
Load)

496. • The control signals are generated in the control unit
and provide control inputs for the multiplexers in the
common bus, control inputs in processor registers,
and micro-operations for the accumulator
There are two major types of control organization:
 Hardwired control
 Micro-programmed control
Control Unit with Timing

497. • Hardwired Organization: the control logic is
implemented with gates, flip-flops, decoders, and
other digital circuits.
• Micro-programmed Organization: the control
information is stored in a control memory (if the
design is modified, the micro-program in control
memory has to be updated)
Control Unit with Timing

498. Control Unit of basic computer
Fig: Block diagram of the hardwired control unit

499. Control Unit of basic computer
Fig: Block diagram of the hardwired control unit
• It consists of two
decoders, a sequence
counter, and a number
of control logic gates.
• An instruction read
from memory is placed
in the instruction
register (IR)

500. Control Unit of basic computer
Fig: Block diagram of the hardwired control unit
• The opcode in bits are
decoded with a 3 x 8
decoder. The eight
outputs of the decoder
are designated by the
symbols D0 through D7.
• Bit 15 of the
instruction is
transferred to a flip-
flop I.
• Bits 0 through 11 are
applied to the control
logic gates.

501. Control Unit of basic computer
Fig: Block diagram of the hardwired control unit
• The 4-bit sequence
counter can count in
binary from 0 through
15.
• The outputs of the
counter are decoded
into 16 timing signals
T0 through T15.
• The sequence counter
SC can be incremented
or cleared
synchronously.

502. Control Unit of basic computer
Fig: Block diagram of the hardwired control unit
• The counter is
incremented to
provide the sequence
of timing signals out of
the 4 x 16 decoder.

503. Control Timing Signals

504. Control Timing Signals
Fig: Diagram of Control Timing Signals
• The timing diagram
shows the time
relationship of the
control signals.
• The sequence counter
SC responds to the
positive transition of
the clock.

505. Control Timing Signals
Fig: Diagram of Control Timing Signals
• Initially, the CLR input
of SC is active. The
first positive
transition of the clock
clears SC to 0, which
in turn activates the
timing signal T0 out of
the decoder. T0 is
active during one
clock cycle.

506. Control Timing Signals
Fig: Diagram of Control Timing Signals
• SC is incremented
with every positive
clock transition,
unless its CLR input is
active.
• This produces the
sequence of timing
signals T0, T1, T2, T3, T4
and so on, as shown
in the diagram.

507. Control Timing Signals
Fig: Diagram of Control Timing Signals
• The last three
waveforms in diagram
show how SC is
cleared when D3T4 =
1.
• Output D3 from the
operation decoder
becomes active at the
end of timing signal
T2.

508. Control Timing Signals
Fig: Diagram of Control Timing Signals
• When timing signal T4
becomes active, the
output of the AND
gate that implements
the control function
D3T4 becomes active.
• This signal is applied
to the CLR input of
SC. On the next
positive clock
transition (the one
marked T4 in the
diagram) the counter

509. Control Timing Signals
Fig: Diagram of Control Timing Signals
• This causes the timing
signal T0 to become
active instead of T5
that would have been
active if SC were
incremented instead
of cleared.

510. Instruction Cycle
• A program is a sequence of instructions stored in
memory.
• The program is executed in the computer by going
through a cycle for each instruction (in most cases).
• Each instruction in turn is subdivided into a sequence
of sub-cycles or phases.

511. Instruction Cycle Phases
• In the basic computer each instruction cycle consists
of the following phases:
 1- Fetch an instruction from memory
 2- Decode the instruction
 3- Read the effective address from memory if the
instruction has an indirect address
 4- Execute the instruction
• This cycle repeats indefinitely unless a HALT
instruction is encountered

512. Fetch and Decode
• Initially, the Program Counter (PC) is loaded with the
address of the first instruction in the program.
• The sequence counter SC is cleared to 0, providing a
decoded timing signal T0.
• After each clock pulse, SC is incremented by one, so
that the timing signals go through a sequence T0, T1,
T2, and so on.

513. Fetch and Decode
 T0: AR←PC (this is essential!!)
The address of the instruction is moved to AR.
 T1: IR←M[AR], PC←PC+1
The instruction is fetched from the memory to IR ,
and the PC is incremented.
 T2: D0,…, D7←Decode IR(12-14), AR←IR(0-11),
I←IR(15)

514. Fig: Register transfer for the fetch phase.
Register transfer for the fetch phase

515. Fig: Register transfer for the fetch phase.
Register transfer for the fetch phase
• Figure shows how
the first two register
transfer statements
are implemented in
the bus system.

516. Fig: Register transfer for the fetch phase.
Register transfer for the fetch phase
T0. (T0: AR←PC)
• To transfer the from
PC to AR we must
apply timing signal
• Place the content of
PC onto the bus by
making the bus
selection inputs S2,
S1, S0 equal to 010.
Transfer the
content of the bus
to AR by enabling
the LD input of AR.

517. Fig: Register transfer for the fetch phase.
Register transfer for the fetch phase
T1: IR←M[AR],
PC←PC+1
• To implement the
second statement,
we need timing
signal T1.
Enable the read
input of memory.
Place the content
of memory onto
the bus by making
S2S1S0=111.

518. Fig: Register transfer for the fetch phase.
Register transfer for the fetch phase
Transfer the
content of the bus
to IR by enabling
the LD input of IR.
Increment PC by
enabling the INR
input of PC.

519. Fig: Register transfer for the fetch phase.
Register transfer for the fetch phase
• The bus system
shows how T0 and
T1 are connected to
the control inputs of
the registers, the
memory, and the
bus selection inputs.
• Multiple input OR
gates are included
because there are
other control
functions that will
initiate similar
operations.

520. Determine the Type of Instruction
How the control determines the instruction cycle type
after the decoding.

521. Determine the Type of Instruction
• The flowchart
shows the
initial
configurations
for the
instruction
cycle and also
how the control
determines the
instruction
cycle type after
the decoding.
Fig: Flowchart for instruction cycle

522. Determine the Type of Instruction
• The timing
signal that is
active after the
decoding is T3.
• During time T3,
the control
unit determine
the type of
instruction
that was read
from the
memory.
Fig: Flowchart for instruction cycle

523. Determine the Type of Instruction
• If D7=1, the
instruction
must be a
register-
reference or
input-output
type.
• If D7 = 0, the
instruction
must be a
memory-
reference
instruction.
Fig: Flowchart for instruction cycle

524. Determine the Type of Instruction
• when D7 = 0,
the operation
code must be
one of the
other seven
values 000
through 110.
Fig: Flowchart for instruction cycle

525. Determine the Type of Instruction
• Control then
inspects the
value of the
first bit of the
instruction,
which is now
available in
flip-flop I.
Fig: Flowchart for instruction cycle

526. Determine the Type of Instruction
• If D7 = 0 and I =
1, indicates a
memory-
reference
instruction
with an
indirect
address. So it
is then
necessary to
read the
effective
address from
memory. Fig: Flowchart for instruction cycle

527. Determine the Type of Instruction
• If D7 = 0 and I =
0, indicates a
memory-
reference
instruction
with a direct
address.
Fig: Flowchart for instruction cycle

528. Determine the Type of Instruction
• If D7 = 1 and I =
0, indicates a
register-
reference
instruction.
• If D7 = 1and I =
1, indicates an
input-output
instruction.
Fig: Flowchart for instruction cycle

529. Determine the Type of Instruction
• The three
instruction
types are
subdivided into
four separate
paths.
• The selected
operation is
activated with
the clock
transition
associated with
timing signal T3.
Fig: Flowchart for instruction cycle

530. Determine the Type of Instruction
Symbolized:-
• D'7IT3: AR
M[AR]
• D'7I'T3:
Nothing
• D7I'T3:
Execute a
register-
reference instr.
• D7IT3:
Execute an
input-output
instr.
Fig: Flowchart for instruction cycle

531. Determine the Type of Instruction
• A register-
reference or
input-output
instruction can
be executed
with the clock
associated
with timing
signal T3.
Fig: Flowchart for instruction cycle

532. Determine the Type of Instruction
• The execution
of the
memory-
reference
instruction can
be continued
with timing
variable T4,
when
instruction
with I=0.
Fig: Flowchart for instruction cycle

533. Determine the Type of Instruction
After the instruction is executed, SC is cleared to 0 and
control returns to the fetch phase with T0=1.

534. Memory-reference instruction

535. Register-reference instruction

536. Input-output instruction

537. Design of Accumulator Logic
Adder and logic circuit,
&
Control gates

538. Design of Accumulator Logic
• Accumulator is the personal register for CPU.
• It is used to hold intermediate values.

539. Design of Accumulator Logic
• The circuits associated with the AC register are shown in Fig.
• The adder and logic circuit has three sets of inputs.
• One set of 16 inputs comes
from the outputs of AC .
• Another set of 16 inputs
comes from the data register
DR .
• A third set of eight inputs
comes from the input
register INPR .

540. Design of Accumulator Logic
• The outputs of the adder and logic circuit provide the data inputs for the
register.
• It is necessary to include
logic gates for controlling the
LD, INR, and CLR in the
register and for controlling
the operation of the adder
and logic circuit.

541. Basic computer registers
connected to a common bus

542. Design of Accumulator Logic
• In order to design the logic associated with AC, it is necessary to go
over the register transfer statements

545. Design of Accumulator Logic
• Extracted all the statements that change the content of AC.
• From this list we can derive the control logic gates and the adder and
logic circuit.

546. Gate structure for controlling
LD, lNR, and CLR
• The control function for the
clear microoperation is rB11,
where r = D7l'T3 and B11 =
IR(11).
• The output of the AND gate
that generates this control
function is connected to the
CLR input of the register.

547. Gate structure for controlling
LD, lNR, and CLR
• Similarly, the output of the
gate that implements the
increment micro-operation is
connected to the INR input
of the register.
• The other seven micro-
operations are generated in
the adder and logic circuit
and are loaded into AC at the
proper time.

548. Adder and Logic Circuit
• One stage of the adder and
logic circuit consists of seven
AND gates, one OR gate and a
full-adder (FA).
• The inputs of the gates with
symbolic names come from the
outputs of gates marked with
the same symbolic name in
“Gate structure for controlling
LD, lNR, and CLR”.
• For example, the input marked
ADD in this Fig. is connected to
the output marked ADD in Fig.
“Gate…”.

549. Internal construction of
4-bit register
• The internal construction of 4-
bit register is as shown in Fig.
Each stage has a JK flip-flop, two
OR gates, and two AND gates.
• The load (LD) input is connected
to the inputs of the AND gates.
• When clear equal to I, the clear
input sets all the K inputs to I,
thus clearing all flip-flops with
the next clock transition.

550. Internal construction of
4-bit register
• The input load control when
equal to I, disables the count
operation and causes a transfer
of data from the four parallel
inputs into the four flip-flops
(provided that the clear input is
0).
• If the clear and load inputs are
both 0 and the increment input
is I, the circuit operates as a
binary counter.

551. Internal construction of
4-bit register
• The input data are loaded into
the flip-flops when the load
control input is equal to 1
provided that the clear is
disabled, but the increment
input can be 0 or 1.
• The register is cleared to 0 with
the clear control regardless of
the values in the load and
increment inputs

552. Adder and Logic Circuit
• The AND operation is
achieved by ANDing AC(i)
with the corresponding bit in
the data register DR(i). The
ADD operation is obtained
using a binary adder.
• One stage of the adder uses
a full-adder with the
corresponding input and
output carries.
• The transfer from INPR to AC
is only for bits 0 through 7.

553. Adder and Logic Circuit
• The complement micro-
operation is obtained by
inverting the bit value in AC.
• The shift-right operation
transfers the bit from AC(i +
1), and the shift-left
operation transfers the bit
from AC(i - 1).
• The complete adder and
logic circuit consists of 16
stages connected together.

554. Memory Unit
Primary memory,
secondary memory,
associative memory, sequential access
&
direct access storage devices.

555. Memory Unit
• Main memory is the central storage unit in a computer system.
• The memory stores binary information in groups of bits called words .
• A word in memory is an entity of bits that move in and out of storage as a
unit.
• The internal structure of a memory unit is specified by the number of
words it contains and the number of bits in each word.
• Special input lines called address lines select one particular word.
• Each word in memory is assigned an identification number, called an
address which starts from 0.
• The size of memory is specified by the number of words (or bytes) with
one of the letters K (kilo), M (mega), or G (giga).
• K is equal to 210
, M is equal to 220
, and G is equal to 230
.
• Thus 64K = 216
, 2M = 221
, and 4G = 232
.

556. Memory Unit
• Two major types of memories are used in computer systems:
Random Access Memory (RAM), and
Read Only Memory (ROM).

557. Random Access Memory
• Communication between a memory and its environment is achieved
through data input and output lines, address selection lines, and control
lines.
• The n data input lines provide the
information to be stored in memory,
and the n data output lines supply
the information coming out of
memory.
• The k address lines provide a binary
number of k bits that specify a
particular word chosen among the 2k
available inside the memory. The
two control inputs specify the
direction of transfer desired.

558. Random Access Memory
• The two operations that a random-access memory can perform are the
write and read operations. The write signal specifies a transfer-in
operation and the read signal specifies a transfer-out operation.
• Steps for transferring a new word to
be stored into memory.
1. Apply the binary address of the
desired word into the address
lines.
2. Apply the data bits that must be
stored in memory into the data
input lines.
3. Activate the write input.

559. Random Access Memory
• The two operations that a random-access memory can perform are the
write and read operations. The write signal specifies a transfer-in
operation and the read signal specifies a transfer-out operation.
• Steps for transferring a stored word
out of memory.
1. Apply the binary address of the
desired word into the address
lines.
2. Activate the read input.

560. Random Access Memory
• RAM and ROM chips are available in a variety of sizes.
• If the memory needed for the computer is larger than the capacity of
one chip.
• It is necessary to combine a number of chips to form the required
memory size.
• To demonstrate the chip interconnection, we will show an example of a
1024 x 8 memory constructed with 128 x 8 RAM chips and 512 x 8 ROM
chips.

561. Random Access Memory
• The block diagram of a RAM chip is shown below.
• The capacity of the memory is 128 words of 8 bits (one byte) per word.
• This requires a 7-bit address and an 8-bit bidirectional data bus.
• The read and write inputs specify the memory operation and the two
chips select (CS) control inputs are for enabling the chip only when it is
selected by the microprocessor.

562. Random Access Memory
• The unit is in operation only when CS1 = 1 and CS2 = 0.
• If the chip select inputs are not enabled, or if they are enabled but the
read or write inputs are not enabled, the memory is inhibited and its
data bus is in a high-impedance state.

563. Random Access Memory
• When the WR input is enabled, the memory stores a byte from the data
bus into a location specified by the address input lines.
• When the RD input is enabled, the content of the selected byte is
placed into the data bus.

564. Memory Unit
• Two major types of memories are used in computer systems:
Random Access Memory (RAM), and
Read Only Memory (ROM).

565. Read Only Memory
• Read Only Memory (ROM) is a memory unit that performs the read
operation only; it does not have a write capability.
• This implies that the binary information stored in a ROM is made
permanent during the hardware production of the unit and cannot be
altered by writing different words into it.
• ROM is restricted to reading words that are permanently stored within
the unit.
• ROMs come with special internal electronic fuses that can be
"programmed" for a specific configuration.
• Once the pattern is established, it stays within the unit even when
power is turned off and on again.

566. Read Only Memory
• An m x n ROM is an array of binary cells organized into m words of n
bits each.
• ROM has k address input lines to select one of 2k
= m words of memory,
and n output lines, one for each bit of the word.
• The ROM does not need a read-control line since at any given time, the
output lines automatically provide the n bits of the word selected by
the address value.

567. Read Only Memory
• The block diagram of a ROM chip is shown.
• A ROM chip is organized externally in a similar manner as organized
RAM.
• However, since a ROM can only read, the data bus can only be in an
output mode. The nine address lines in the ROM chip specify any one of
the 512 bytes stored in it.

568. Read Only Memory
• The two chip select inputs must be CS1 = 1 and CS2 = 0 for the unit to
operate. Otherwise, the data bus is in a high-impedance state.
• There is no need for a read or write control because the unit can only
read.
• Thus when the chip is enabled by the two select inputs, the byte
selected by the address lines appears on the data bus.