unit 5, IC Technology, RTU 8th sem ECE, Failure analysis and characterization techniques.

1. Fault Diagnosis and
characterization
Neha Sharma
Assistant professor
Department of electronics and communication
Engineering College Jhalawar

2. Failure Analysis
https://nptel.ac.in/courses/103106075/
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

3. Parametric testing
Will all the wagers and chips go for testing ?
No
● Superficial testing
● Kerfs and scrub lines
● Batch
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

4. Shorts and open test
Snake structure for open test
Comb structure for short test
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

5. Van-der-Pauw
Thickness / sheet resistance of
deposited material.
Called as Greek cross
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

6. Complete test
● Programming test for DUT
● Alignment test
● CV test
● IV test
● TDDB (temp dependent dielectric breakdown)
● NBTI (negative bias temperature instability)
● IDDQ ( quiescent supply current)
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

7. Binning / Sort test
Test chips separated based on
failure modes
● Hard bin
● Soft bin
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

8. Other tests
BIST
(built in self test)
Checks logical functioning of
the circuit under test (CUT)
by giving test vectors.
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

9. Memory testing
● Failed bit map
In the memory region, the bits are
arranged in rows and columns. If one
or two bits fail randomly in a chip,
then it is difficult to identify the cause
of the failure. However, if a row of
bits have failed, based on the design,
the engineer will be able to conclude
that M1 line has shorted (as an
example). If a column of bits have
failed, the engineer can conclude that
a particular metal line is open (i.e. the
line is broken). The ‘row’s are
called word lines and the columns are
called bit lines as shown in the
schematic.
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

10. Memory repair
R1
R2
R3
R4
R5
C1 C2 C3 C4
C1 C2 C3 C4
R1
R2
R3
R4
R5
Pre fuse
test
Post
fuse test
Fuse connections to extra bit
Remove connections by laser to
defected bits
PASSFAIL
Extra bits are removed by laser
Extra bits
Defected row
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

11. High temperature test
The chip will be subjected to high temperature and tested. In case of military
applications, the chip may be subjected to low temperature and tested also.
(e.g. the chips used in satellites or missiles will have to encounter both high and
low temperatures and hence these chips should be tested at harsh conditions
before they are packaged and used).
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

12. Optical testing
● The optical tests are used at various stages of processing, (i.e. before the chip is
completely fabricated). Specifically, they are used to determine if there are any
defects on the wafers.
● Defects may arise due to dust particles falling on wafer, or due to poor process.
● It must be noted that the features present in the chip, such as interconnect
copper lines, are also of similar size. Hence the equipment must be capable of
distinguishing between the desired features (such as interconnect lines) and
unwanted ones, such as dusts.
● One way of handling this is to image two neighbouring chips simultaneously and
compare them. If both images are the same, then it can be assumed that there
are no defects. When they are different, the presence of defect can be
identified.
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

13. Characterisation
Techniques
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

14. Semiconductor Characterisation
● To predict how device/material behave under certain conditions.
● These quantities fall into three categories when it comes to characterization
methods:
1) Electrical Characterization
2) Optical Characterization
3) Physical/Chemical Characterization
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

15. Electrical Characterization Techniques
Electrical Characterization can be used to determine resistivity, carrier
concentration, mobility, contact resistance, barrier height, depletion width, oxide
charge, interface states, carrier lifetimes, and deep level impurities.
Two-Point Probe, Four-Point Probe, Differential Hall Effect, Capacitance-
Voltage Profiling, DLTS, Electron beam-induced current, and DLCP.
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

16. Optical Characterization
Optical Characterization may
include microscopy, ellipsometry, photoluminescence, transmission
spectroscopy, absorption spectroscopy, raman
spectroscopy, reflectance modulation, cathodoluminescence, to name a few.
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

17. Physical/Chemical Characterization
Electron Beam Techniques -
SEM, TEM, AES, EMP, EELS
Ion Beam Techniques - Sputtering, SIMS, RBS
X-Ray Techniques - XRF, XPS, XRD, X-ray
topography Neutron Activation
Analysis (NAA) Chemical Etching
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

18. Characterization Report
1. A copy of the characterization plan.
2. A detailed discussion of the characterization methods used
3. A listing of parameters and conditions used in characterization.
4. Characterization data analysis and conclusions.
5. Document simulation results including brief explanations on methods
applied – for parameters that are not measurable and/or tested in production
and covered by design simulation only.
6. Identify part weaknesses and reliability concerns and define corrective
actions.
NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR

19. NEHA SHARMA | ECE | ENGINNERING COLLEGE JHALAWAR