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This presentation gives you easier way to study 8086 i.e. 16 bit microprocessor. 8086 microprocessor's architecture contains two basic functional units namely Bus Interface Unit and Execution Unit. BIS fetches the instructions from memory. It reads/writes instructions to/from memory. Input/Output of data to/from I/O peripheral ports. Address generation of memory reference. Queing instructions. Thus, BIU handles all transfer of data and address. Tasks of EU: Decodes the instructions. Executes the decoded instructions. Tells BIU from where to fetch the instruction. EU takes care of performing operation on the data. EU is also known as heart of the data.

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Microprocessors & Microcontrollers: Interrupt controller 8259; The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor. In 8085 and 8086 there are five hardware interrupts and two hardware interrupts respectively. Bu adding 8259, we can increase the interrupt handling capability. This chip combines the multi-interrupt input source to single interrupt output. This provides 8-interrupts from IR0 to IR7. Let us see some features of this microprocessor. This chip is designed for 8085 and 8086. It can be programmed either in edge triggered, or in level triggered mode We can mask individual bits of Interrupt Request Register. By cascading 8259 chips, we can increase interrupts up to 64 interrupt lines Clock cycle is not needed. 8259 microprocessor can be programmed according to given interrupts condition and it can be provided either with level or edge-triggered interrupt level. It can be programmed to either work in 8085 or in 8086 microprocessors. Individual interrupt bits can be masked. By cascading Nine 8259’s in Master-Slave Configuration we can handle up to 64 interrupt pins. It contains 3 registers commonly known as ISR, IRR, IMR & there is 1 priority resolver (PR). Interrupt Request Register (IRR): It stores those bits which are requested for their interrupt services. Interrupt Service Register (ISR): It stores the interrupt levels which is currently being served. Interrupt Mask Register (IMR): It stores interrupt levels that have to be masked. These interrupt levels are already accepted by the 8259 microprocessor. Priority Resolver (PR): It examines all the 3 registers and sets the priority of interrupts and sets the interrupt levels in ISR which has the highest priority and the rest of the interrupt bit is IRR which is already accepted. SP/EN (low active pin): If its value is 1 it works in master mode & if its value=e is 0 then it works in slave mode. Cascade Buffer: It is used to cascade more number of Programmable Interrupt Controller to increase the interrupts handling capability up to 64 levels. Advantages: Interrupt management: The 8259 microprocessor is a specialized chip that is dedicated to managing interrupts, which can help to improve system performance and reduce the workload on the main CPU. Programmability: The 8259 microprocessor is programmable, which means that it can be customized to handle specific types of interrupts and to prioritize different interrupt requests. Compatibility: The 8259 microprocessor is compatible with a wide range of microprocessors, making it a popular choice for interrupt management in many different systems. Multiple interrupt inputs: The 8259 microprocessor can handle multiple interrupt inputs, which makes it a useful peripheral for managing complex systems with multiple devices. Ease of use: The 8259 microprocessor includes simple interface pins and registers, making it relatively easy to use and program.

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