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STP40NF03L
N - CHANNEL 30V - 0.020 Ω - 40A TO-220
STripFET POWER MOSFET
■ TYPICAL RDS(on) = 0.020 Ω
■ LOW THRESHOLD DRIVE
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronics unique ”Single Feature
Size” strip-based process. The resulting
transistor shows extremely high packing density
for low on-resistance, rugged avalanche
characteristics and less critical alignment steps
therefore a remarkable manufacturing
reproducibility.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SOLENOID AND RELAY DRIVERS
■ MOTOR CONTROL, AUDIO AMPLIFIERS
■ DC-DC & DC-AC CONVERTERS

INTERNAL SCHEMATIC DIAGRAM
October 1999
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VDS Drain-source Voltage (VGS = 0) 30 V
VDGR Drain- gate Voltage (RGS = 20 kΩ) 30 V
VGS Gate-source Voltage ± 20 V
ID Drain Current (continuous) at Tc = 25 o
C 40 A
ID Drain Current (continuous) at Tc = 100 o
C 28 A
IDM(•) Drain Current (pulsed) 160 A
Ptot Total Dissipation at Tc = 25 o
C 70 W
Derating Factor 0.46 W/o
C
EAS(1) Single Pulse Avalanche Energy 250 m/J
Tstg Storage Temperature -65 to 175
o
C
Tj Max. Operating Junction Temperature 175 o
C
(•) Pulse width limitedby safe operating area ( 1) starting Tj = 25 o
C, ID =20A , VDD = 15V
TYPE VDSS RDS(on) ID
STP40NF03L 30 V < 0.022 Ω 40 A
1
2
3
TO-220
1/8
THERMAL DATA
Rthj-case
Rthj-amb
Tl
Thermal Resistance Junction-case Max
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering Purpose
2.1
62.5
300
o
C/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS (Tcase = 25 o
C unless otherwisespecified)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source
Breakdown Voltage
ID = 250 µA VGS = 0 30 V
IDSS Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
VDS = Max Rating Tc =125 o
C
1
10
µA
µA
IGSS Gate-body Leakage
Current (VDS = 0)
VGS = ± 20 V ± 100 nA
ON (∗)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 µA 1 1.7 2.5 V
RDS(on) Static Drain-source On
Resistance
VGS = 10 V ID = 20 A
VGS = 4.5 V ID = 20 A
0.018
0.028
0.022
0.035
Ω
Ω
ID(on) On State Drain Current VDS > ID(on) x RDS(on)max
VGS = 10 V
40 A
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs (∗) Forward
Transconductance
VDS > ID(on) x RDS(on)max ID =20 A 20 S
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS = 25 V f = 1 MHz VGS = 0 830
230
92
pF
pF
pF
STP40NF03L
2/8
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on)
tr
Turn-on Delay Time
Rise Time
VDD = 15 V ID = 20 A
RG = 4.7 Ω VGS = 4.5 V
(Resistive Load, see fig. 3)
35
205
ns
ns
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 24 V ID = 40 A VGS = 5 V 18
7
8
23 nC
nC
nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(off)
tf
Turn-off Delay Time
Fall Time
VDD = 15 V ID = 20 A
RG = 4.7 Ω VGS = 4.5 V
(Resistive Load, see fig. 3)
90
240
ns
ns
td(off)
tf
tc
Off-voltage Rise Time
Fall Time
Cross-over Time
Vclamp = 24 V ID = 20 A
RG = 4.7 Ω VGS = 4.5 V
(Inductive Load, see fig. 5)
150
155
340
ns
ns
ns
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ISD
ISDM (•)
Source-drain Current
Source-drain Current
(pulsed)
40
160
A
A
VSD (∗) Forward On Voltage ISD = 40 A VGS = 0 1.5 V
trr
Qrr
IRRM
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
ISD = 40 A di/dt = 100 A/µs
VDD = 15 V Tj = 150 o
C
(see test circuit, fig. 5)
65
72
2
ns
nC
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area Thermal Impedance
STP40NF03L
3/8
Output Characteristics
Transconductance
Gate Charge vs Gate-sourceVoltage
Transfer Characteristics
Static Drain-source On Resistance
Capacitance Variations
STP40NF03L
4/8
Normalized Gate Threshold Voltage vs
Temperature
Source-drainDiode Forward Characteristics
Normalized On Resistance vs Temperature
STP40NF03L
5/8
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 2: Unclamped Inductive Waveform
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
STP40NF03L
6/8
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
L6
A
C
D
E
D1
F
G
L7
L2
Dia.
F1
L5
L4
H2
L9
F2
G1
TO-220 MECHANICAL DATA
P011C
STP40NF03L
7/8
Information furnished is believed to be accurate and reliable. However, STMicroelect
ronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third part
ies which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectro
nics. Specificationmentioned in this publication are
subject tochange without notice. This publication supersedes and replaces all informat
ion previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems with
out express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japa
n - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
.
STP40NF03L
8/8

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STP40NF03L.pdf

  • 1. STP40NF03L N - CHANNEL 30V - 0.020 Ω - 40A TO-220 STripFET POWER MOSFET ■ TYPICAL RDS(on) = 0.020 Ω ■ LOW THRESHOLD DRIVE DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique ”Single Feature Size” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SOLENOID AND RELAY DRIVERS ■ MOTOR CONTROL, AUDIO AMPLIFIERS ■ DC-DC & DC-AC CONVERTERS  INTERNAL SCHEMATIC DIAGRAM October 1999 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 30 V VDGR Drain- gate Voltage (RGS = 20 kΩ) 30 V VGS Gate-source Voltage ± 20 V ID Drain Current (continuous) at Tc = 25 o C 40 A ID Drain Current (continuous) at Tc = 100 o C 28 A IDM(•) Drain Current (pulsed) 160 A Ptot Total Dissipation at Tc = 25 o C 70 W Derating Factor 0.46 W/o C EAS(1) Single Pulse Avalanche Energy 250 m/J Tstg Storage Temperature -65 to 175 o C Tj Max. Operating Junction Temperature 175 o C (•) Pulse width limitedby safe operating area ( 1) starting Tj = 25 o C, ID =20A , VDD = 15V TYPE VDSS RDS(on) ID STP40NF03L 30 V < 0.022 Ω 40 A 1 2 3 TO-220 1/8
  • 2. THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 2.1 62.5 300 o C/W o C/W o C ELECTRICAL CHARACTERISTICS (Tcase = 25 o C unless otherwisespecified) OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA VGS = 0 30 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating Tc =125 o C 1 10 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20 V ± 100 nA ON (∗) Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 µA 1 1.7 2.5 V RDS(on) Static Drain-source On Resistance VGS = 10 V ID = 20 A VGS = 4.5 V ID = 20 A 0.018 0.028 0.022 0.035 Ω Ω ID(on) On State Drain Current VDS > ID(on) x RDS(on)max VGS = 10 V 40 A DYNAMIC Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (∗) Forward Transconductance VDS > ID(on) x RDS(on)max ID =20 A 20 S Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V f = 1 MHz VGS = 0 830 230 92 pF pF pF STP40NF03L 2/8
  • 3. ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 15 V ID = 20 A RG = 4.7 Ω VGS = 4.5 V (Resistive Load, see fig. 3) 35 205 ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 24 V ID = 40 A VGS = 5 V 18 7 8 23 nC nC nC SWITCHING OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf Turn-off Delay Time Fall Time VDD = 15 V ID = 20 A RG = 4.7 Ω VGS = 4.5 V (Resistive Load, see fig. 3) 90 240 ns ns td(off) tf tc Off-voltage Rise Time Fall Time Cross-over Time Vclamp = 24 V ID = 20 A RG = 4.7 Ω VGS = 4.5 V (Inductive Load, see fig. 5) 150 155 340 ns ns ns SOURCE DRAIN DIODE Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) 40 160 A A VSD (∗) Forward On Voltage ISD = 40 A VGS = 0 1.5 V trr Qrr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A di/dt = 100 A/µs VDD = 15 V Tj = 150 o C (see test circuit, fig. 5) 65 72 2 ns nC A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance STP40NF03L 3/8
  • 4. Output Characteristics Transconductance Gate Charge vs Gate-sourceVoltage Transfer Characteristics Static Drain-source On Resistance Capacitance Variations STP40NF03L 4/8
  • 5. Normalized Gate Threshold Voltage vs Temperature Source-drainDiode Forward Characteristics Normalized On Resistance vs Temperature STP40NF03L 5/8
  • 6. Fig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 2: Unclamped Inductive Waveform Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times STP40NF03L 6/8
  • 7. DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 D1 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 L4 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 L6 A C D E D1 F G L7 L2 Dia. F1 L5 L4 H2 L9 F2 G1 TO-220 MECHANICAL DATA P011C STP40NF03L 7/8
  • 8. Information furnished is believed to be accurate and reliable. However, STMicroelect ronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third part ies which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectro nics. Specificationmentioned in this publication are subject tochange without notice. This publication supersedes and replaces all informat ion previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems with out express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics  1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japa n - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com . STP40NF03L 8/8