Unit 4.docx

UNIT - IV
DIGITAL ELECTRONICS
4.1 NUMBER SYSTEM
 There are infinite ways to represent a number. The four commonly associated with
modern computers and digital electronics are:
 Decimal
 Binary
 Octal
 Hexa decimal.
 Decimal (base 10) is the way most human beings represent numbers. Decimal is
sometimes abbreviated as dec.
Decimal counting goes:
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, and so on
 Binary (base 2) is the natural way most digital circuits represent and manipulate
numbers. Binary numbers are sometimes represented by preceding the value with as in
1011. Binary is sometimes abbreviated as bin.
Binary counting goes:
0, 1, 10, 11, 100, 101, 110, 111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111,
10000, 10001, and so on.
 Octal (base 8) was previously a popular choice for representing digital circuit numbers
in a form that is more compact than binary. Octal is sometimes abbreviated as oct.
Octal counting goes:
0, 1, 2, 3, 4, 5, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 20, 21, and so on.
 Hexadecimal (base 16) is currently the most popular choice for representing digital
circuit numbers in a form that is more compact than binary. Hexadecimal numbers are
sometimes represented by preceding the value with '0x', as in 0x1B84. Hexadecimal is
sometimes abbreviated as hex.
Hexadecimal counting goes:
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 10, 11, and so on.

4.2 Basic Electrical and Electronics Engineering
4.1.1 Binary Number Conversion
(A) Binary to Octal
 An easy way to convert from binary to octal is to group binary digits into sets of three,
starting with the least significant (rightmost) digits.
Binary: 11100101 = 11 100 101
011 100 101 Pad the most significant digits with zeros if
necessary to complete a group of three.
Then, look up each group in a table:
Binary: 000 001 010 011 100 101 110 111
Octal: 0 1 2 3 4 5 6 7
Binary = 011 100 101
Octal = 3 4 5 = 345 oct
(B) Binary to Hexadecimal
 An equally easy way to convert from binary to hexadecimal is to group binary digits
into sets of four, starting with the least significant (rightmost) digits.
Binary: 11100101 = 1110 0101
Binary: 0000 0001 0010 0011 0100 0101 0110 0111
Hexadecimal: 0 1 2 3 4 5 6 7
Binary: 1000 1001 1010 1011 1100 1101 1110 1111
Hexadecimal: 8 9 A B C D E F
Binary = 1110 0101
Hexadecimal = E 5 = E5 hex

Digital Electronics 4.3
(C ) Binary to Decimal
 A method to convert from binary to decimal which involves addition and multiplication
is.
 Start the decimal result at 0.
 Remove the most significant binary digit (leftmost) and add it to the result.
 If all binary digits have been removed, you’re done. Stop.
 Otherwise, multiply the result by 2.
 Go to step 2.
Here is an example of converting 11100000000 binary to decimal:
BINARY
DIGITS
OPERATION
DECIMAL
RESULT
OPERATION
DECIMAL
RESULT
11100000000 +1 1 × 2 2
1100000000 +1 3 × 2 6
100000000 +1 7 × 2 14
00000000 +0 14 × 2 28
0000000 +0 28 × 2 56
000000 +0 56 × 2 112
00000 +0 112 × 2 224
0000 +0 224 × 2 448
000 +0 448 × 2 896
00 +0 896 × 2 1792
0 +0 1792 done.
4.1.2 Decimal Number Conversion
 A repeated division and remainder algorithm can convert decimal to binary, octal,
or hexadecimal.
 Divide the decimal number by the desired target radix (2, 8, or 16).
 Append the remainder as the next most significant digit.
 Repeat until the decimal number has reached zero.

(a) Decimal to Binary
Here is an example of using repeated division to convert 1792 decimal to binary:
DECIMAL
NUMBER
OPERATION QUOTIENT REMAINDER
BINARY
RESULT
1792 ÷ 2 = 896 0 0
896 ÷ 2 = 448 0 00
448 ÷ 2 = 224 0 000
224 ÷ 2 = 112 0 0000
112 ÷ 2 = 56 0 00000
56 ÷ 2 = 28 0 000000
28 ÷ 2 = 14 0 0000000
14 ÷ 2 = 7 0 00000000
7 ÷ 2 = 3 1 100000000
3 ÷ 2 = 1 1 1100000000
1 ÷ 2 = 0 1 1100000000
0 done.
Decimal to Octal. Here is an example of using repeated division to convert 1792
decimal to octal:
DECIMAL
NUMBER
OCTAL
RESULT
1792 ÷ 8 = 224 0 0
224 ÷ 8 = 28 0 00
28 ÷ 8 = 3 4 400
3 ÷ 8 = 0 3 3400
0 done.

(b) Decimal to Hexadecimal
Here is an example of using repeated division to convert 1792 decimal to hexadecimal:
DECIMAL
NUMBER
HEXADECIMAL
RESULT
1792 ÷ 16 = 112 0 0
112 ÷ 16 = 7 0 00
7 ÷ 16 = 0 7 700
0 done.
The only addition to the algorithm when converting from decimal to hexadecimal is
that a table must be used to obtain the hexadecimal digit if the remainder is greater than
decimal 9.
Decimal: 0 1 2 3 4 5 6 7
Hexadecimal: 0 1 2 3 4 5 6 7
Decimal: 8 9 10 11 12 13 14 15
The addition of letters can make for funny hexadecimal values. For example, 48879
decimal converted to hex is:
DECIMAL
NUMBER
HEXADECIMAL
RESULT
48879 ÷ 16 = 3054 15 F
3054 ÷ 16 = 190 14 EF
190 ÷ 16 = 11 14 EEF
11 ÷ 16 = 0 11 BEEF
0 done.

4.1.3 Octal Number Conversion
(a) Octal to Binary
Converting from octal to binary is as easy as converting from binary to octal. Simply
look up each octal digit to obtain the equivalent group of three binary digits.
Octal: 0 1 2 3 4 5 6 7
Binary: 000 001 010 011 100 101 110 111
Octal = 3 4 5
Binary = 011 100 101 = 011100101 binary
(b) Octal to Hexadecimal
When converting from octal to hexadecimal, it is often easier to first convert the octal
number into binary and then from binary into hexadecimal. For example, to convert 345 octal
into hex:
(from the previous example)
Octal = 3 4 5
Binary = 011 100 101 = 011100101 binary
Drop any leading zeros or pad with leading zeros to get groups of four binary digits
(bits):
Binary 011100101 = 1110 0101
Then, look up the groups in a table to convert to hexadecimal digits.
Binary: 0000 0001 0010 0011 0100 0101 0110 0111
Hexadecimal: 0 1 2 3 4 5 6 7
Binary: 1000 1001 1010 1011 1100 1101 1110 1111
Binary = 1110 0101

Hexadecimal = E 5 = E5 hex
Therefore, through a two-step conversion process, octal 345 equals binary 011100101
equals hexadecimal E5.
(c) Octal To Decimal
Converting octal to decimal can be done with repeated division.
 Start the decimal result at 0.
 Remove the most significant octal digit (leftmost) and add it to the result.
 If all octal digits have been removed, you’re done. Stop.
 Otherwise, multiply the result by 8.
 Go to step 2.
OCTAL
DIGITS
OPERATION
DECIMAL
RESULT
OPERATION
DECIMAL
RESULT
345 +3 3 × 8 24
45 +4 28 × 8 224
5 +5 229 done.
The conversion can also be performed in the conventional mathematical way, by
showing each digit place as an increasing power of 8.
345 octal = (3 * 82) + (4 * 81) + (5 * 80) = (3 * 64) + (4 * 8) + (5 * 1) = 229 decimal

4.1.4 Hexadecimal Number Conversion
(a) Hexadecimal to Binary
Converting from hexadecimal to binary is as easy as converting from binary to
hexadecimal. Simply look up each hexadecimal digit to obtain the equivalent group of four
binary digits.
Hexadecimal: 0 1 2 3 4 5 6 7
Binary: 0000 0001 0010 0011 0100 0101 0110 0111
Binary: 1000 1001 1010 1011 1100 1101 1110 1111
Hexadecimal = A 2 D E
Binary = 1010 0010 1101 1110 = 1010001011011110 binary
(b) Hexadecimal to Octal
When converting from hexadecimal to octal, it is often easier to first convert the
hexadecimal number into binary and then from binary into octal. For example, to convert
A2DE hex into octal:
(from the previous example)
Hexadecimal = A 2 D E
Binary = 1010 0010 1101 1110 = 1010001011011110 binary
Add leading zeros or remove leading zeros to group into sets of three binary digits.
Binary: 1010001011011110 = 001 010 001 011 011 110
Binary:
000 001 010 011 100 101 110 111

Octal:
0 1 2 3 4 5 6 7
Binary = 001 010 001 011 011 100
Octal = 1 2 1 3 3 6 = 121336 octal
Therefore, through a two-step conversion process, hexadecimal A2DE equals binary
1010001011011110 equals octal 121336.
(c) Hexadecimal to Decimal
 Converting hexadecimal to decimal can be performed in the conventional mathematical
way, by showing each digit place as an increasing power of 16.
 Of course, hexadecimal letter values need to be converted to decimal values before
performing the math.
Hexadecimal: 0 1 2 3 4 5 6 7
Decimal: 0 1 2 3 4 5 6 7
Decimal: 8 9 10 11 12 13 14 15
A2DE hexadecimal:
= ((A) * 163) + (2 * 162) + ((D) * 161) + ((E) * 160)
= (10 * 163) + (2 * 162) + (13 * 161) + (14 * 160)
= (10 * 4096) + (2 * 256) + (13 * 16) + (14 * 1)
= 40960 + 512 + 208 + 14
= 41694 decimal

4.1.5 Problems on Number System Conversions:
(a) Convert each of the following binary numbers to octal, decimal, and hexadecimal
formats.
(111011101)2
To octal: 111 011 101 = (735)8
To decimal: = (1 x 28) + (1 x 27) + (1 x 26) + (1 x 24) + (1 x 23) + (1 x 22) + (1 x 20)
= 256 + 128 + 64 + 16 + 8 + 4 + 1
= (477)10
To hexadecimal: 0001 1101 1101 = (1DD)16
(10101010111)2
To octal: 010 101 010 111 = (2527)8
To decimal: = (1 x 210) + (1 x 28) + (1 x 26) + (1 x 24) + (1 x 22) + (1 x 21) + (1 x 20)
= 1024 + 256 + 64 + 16 + 4 + 2 + 1
= (1367)10
To hexadecimal: = 0101 0101 0111 (557)16
(111100000)2
To octal: = 111 100 000 (740)8
To decimal: =(1 x 28) + (1 x 27) + (1 x 26) + (1 x 25)
= 256 + 128 + 64 + 32
= (480)10
To hexadecimal: = 0001 1110 0000 (1E0)16

(b) Convert each of the following octal numbers to binary, decimal, and hexadecimal
formats.
(3754)8
To binary: = (11 111 101 100)2
To decimal: =(3x83) + (7x82) + (5x81) + (4x80)
= 1536 + 448 + 40 + 4
= (2028)10
To hexadecimal: = (0111 1110 1100)2 = (7EC)16
(7777)8
To binary: = (111 111 111 111)2
To decimal: =(7 x 83) + (7 x 82) + (7 x 81) + (7 x 80)
= 3584 + 448 + 56 + 7
= (4095)10
To hexadecimal: = (1111 1111 1111)2 = (FFF)16
(247)8
To binary: = (10 100 111)2
To decimal: =(2 x 82) + (4 x 81) + (7 x 80)
= 128 + 32 + 7
= (167)10
To hexadecimal: = (1010 0111)2 = (A7)16

(c) Convert each of the following decimal numbers to binary, octal, andhexadecimal
formats.
(3479)10
To binary: = 3479 ¸ 2 = 1739 rem = 1
1739¸ 2 = 869 rem = 1
869¸ 2 = 434 rem = 1
434¸ 2 = 217 rem = 0
217¸ 2 = 108 rem = 1
108¸ 2 = 54 rem = 0
54¸ 2 = 27 rem = 0
27¸ 2 = 13 rem = 1
13¸ 2 = 6 rem = 1
6¸ 2 = 3 rem = 0
3¸ 2 = 1 rem = 1
1¸ 2 = 0 rem = 1
reading bottom to top of remainders = (110110010111)2
To octal: = 3479 ¸ 8 = 434 rem = 7
434¸ 8 = 54 rem = 2
54¸ 8 = 6 rem = 6
6¸ 8 = 0 rem = 6
To hexadecimal: = 3479 ¸ 16 = 217 rem = 7
217¸ 16 = 13 rem = 9
13¸ 16 = 0 rem = 13 (D)
reading bottom to top of remainders = (D97)16

(642)10
To binary: = 642 ¸ 2 = 321 rem =0
321¸ 2 = 160 rem = 1
160¸ 2 = 80 rem = 0
80¸ 2 = 40 rem = 0
40¸ 2 = 20 rem = 0
20¸ 2 = 10 rem = 0
10¸ 2 = 5 rem = 0
5¸ 2 = 2 rem = 1
2¸ 2 = 1 rem = 0
1¸ 2 = 0 rem = 1
To octal: = 642 ¸ 8 = 80 rem = 2
80¸ 8 = 10 rem = 0
10¸ 8 = 1 rem = 2
1¸ 8 = 0 rem = 1
To hexadecimal: = 642¸ 16 = 40 rem = 2
40¸ 16 = 2 rem = 8
2¸ 16 = 0 rem = 2
(555)10
To binary: = 555 ¸ 2 = 277 rem = 1
277¸ 2 = 138 rem = 1
138¸ 2 = 69 rem = 0
69¸ 2 = 34 rem = 1
34¸ 2 = 17 rem = 0

17¸ 2 = 8 rem = 1
8¸ 2 = 4 rem = 0
4¸ 2 = 2 rem = 0
2¸ 2 = 1 rem = 0
Number Systems Practice Problems - 6
1¸ 2 = 0 rem = 1
To octal: = 555 ¸ 8 = 69 rem = 3
69¸ 8 = 8 rem = 5
8, 8 = 1 rem = 0
1¸ 8 = 0 rem = 1
To hexadecimal: = 555 ¸ 16 = 34 rem = 11 (B)
34¸ 16 = 2 rem = 2
2¸ 16 = 0 rem = 2
reading bottom to top of remainders = (22B)16
(d) Convert each of the following hexadecimal numbers to binary, octal, and decimal
formats.
(4FB2)16
To binary: (100 1111 1011 0010)2
To octal: (100 1111 1011 0010)2 = (47662)8
To decimal: = (4x163) + (15x162) + (11x161) + (2x160)
= (4x4096) + (15x256) + (11x16) + (2x1)
= 16384 + 3840 + 176 + 2
= (20402)10

(88BAE)16
To binary: (1000 1000 1011 1010 1110)2
To octal: (10 001 000 101 110 101 110)2 = (2105656)8
To decimal: = (8x164) + (8x163) + (11x162) + (10x161) + (14x160)
= (8x65536) + (8x4096) + (11x256) + (10x16) + (14x1)
= 16384 + 3840 + 176 + 14
= (560046)10
(DC4)16
To binary: (1101 1100 0100)2
To octal: (110 111 000 100)2 = (6704)8
To decimal: = (13x162) + (12x161) + (4x160)
= (13x256) + (12x16) + (4x1)
= 3328 + 192 + 4
= (3524)10
4.2 LOGIC GATES
4.2.1 Introduction
 A logic gate is an elementary building block of a digital circuit
 It is a circuit with one output and one or more inputs
 At any condition logic gates takes one of the two binary conditions low(0) or
high(1)
 The input signal takes the values ‘1’ or ‘0’ ,the output signal gives the value ‘1’ or
‘0’
 There are three fundamental logic gates namely AND,OR and Not
 We have other logic gates like NAND,NOR,XOR and XOR

 Out of these NAND and NOR gates are called the universal gates because we can
obtain any gate with them
4.2.2 AND GATE
 The AND gate is so called because ,if 0 is called “false” and 1 is called “true”
 It act in the same way as the logical “AND” operator
 The output of logic is represented by C where inputs are A and B
 Since there are two inputs variables here ,the truth table as four entries the truth
table as four possible inputs:00,01,10,11
SYMBOL:
TRUTH TABLE:
4.2.3 OR GATE
 The OR gate gets its name from the fact that it behave like logical inclusive “OR”
 The output is 1 when both the inputs are 1 or any one input is 1
 When both the inputs are 0 output is 0
SYMBOL:
A B AŸB=C
0 0 0
0 1 0
1 0 0
1 1 1

TRUTH TABLE:
4.2.4 NOT GATE
 The NOT gate ,called a logical inverter, has only one input it reverses the logical
state
 In other words the output C is always the complement of the input
SYMBOL:
TRUTH TABLE:
4.2.5 NOR GATE
 The NOR gate circuit is an OR gate followed by an inverter
 Its output is 1 when both the inputs are 0,otherwise the output is to be 0
SYMBOL:
A B A+B=C
0 0 0
0 1 1
1 0 1
1 1 1
INPUT OUTPUT
1 0
0 1

TRUTH TABLE:
INPUT
A B C
0 0 1
0 1 0
1 0 0
1 1 0
4.2.6 NAND GATE
 The NAND gate operates as an AND gate followed by a NOT gate
 It acts like logical operation “AND” followed by inversion
 The output is 0 if both inputs are 1otherewise the output is 1
SYMBOL:
TRUTH TABLE:
INPUT
A B C
0 0 1
0 1 1
1 0 1
1 1 0

4.2.7 XOR GATE
 The XOR(exclusive-OR) gate acts in same way as the logical “either/or”
 The output is 1 if any one input is 1
SYMBOL:
TRUTH TABLE:
INPUTS OUTPUT
A B
0 0 0
0 1 1
1 0 1
1 1 0
42.8 XNOR GATE
 The XNOR(exclusive NOR) gate is a combination XOR gate followed by an
inverter
 Its output is 1 when both the inputs are same otherwise the output is 0
SYMBOL:

TRUTH TABLE:
4.3 BOOLEAN ALGEBRA
4.3.1 Introduction
 George Boole invented a symbolic logic known as Boolean algebra in 1854.
 It is a mathematical technique used to solve problems in logic nature.
 Elements used are ‘0’ and ‘1’.
4.3.2 Basic Laws of Boolean Algebra
A + 0 = A A . 0 = 0
A + 1 = 1 A . 1 = A
A . (B + C) = A . B + A . C A+BC=(A+B).(A+C)
A + A = 1 A . A = 0
4.3.3 Theorems
A + A = A ; A . A = A (A + B) (A + B) = A
A (A+B) =AB AB + AB = A
(AI)I = A A + AB = A + B
INPUTS OUTPUT
A B C
0 0 1
0 1 0
1 0 0
1 1 1

4.3.4 Laws
(a) Commutative law
 A + B = B + A
 A . B = B . A
(b) Associative law
 A + (B + C) = (A + B) + C
 A . (B . C) = (A . B) . C
(c) Distributive law
 A.(B + C) = A.B+A.C
 (A + B) . (C +D) = A . C + B . C + A . D + B . D
4.4 DE-MORGON’S THEOREM
(a) FIRST LAW
 The complement of sum of the variables is equal to the product of their complements.
Truth table:
A B A+B
0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0
(b) SECOND LAW
 The complement of product of the variables is equal to the sum of their complements.
A B A . B
 
A B
 A B A . B
A.B A B
 

Truth table:
A B A.B A.B A B A+B
0 0 0 1 1 1 1
0 1 0 1 1 0 1
1 0 0 1 0 1 1
1 1 1 0 0 0 0
4.4.1 Duality Theorem
 It says that starting with a Boolean relation, we can derive another relation like,
 Changing each OR sign to an AND sign.
 Changing each AND sign to an OR sign.
 Complementing any 0 to 1 and 1 to 0 appearing in the expression.
Table shown:
S.NO BOOLEAN RELATION DUALITY RELATION
1. A + 0 = A A . 1 = A
2. A + 1 = 1 A . 0 = 0
3. A + A = A A . A = 1
4. A + = 1 A . = 0
Example of Simplification
A A
Y A BD A BD
 
A B(D D)
 
Y A B


4.5 KARNAUGH’S MAP
 Is a visual display of the fundamental products needed for a sum of products
solutions.
 We can easily simplify the Boolean equations in sum of product form.
(a) Two variables map: (Truth table)
INPUTS OUTPUT
Y
A B
0 0 1
0 1 1
1 0 0
1 1 0
Karnaugh map:
I0 I1
02 03
(b) Three variable map:
INPUT OUTPUT
Y
A B C
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

4.5.1 Looping
 The expression for the output that can be simplified properly by combining 1’s in
the karnaugh map is called as looping.
Pairs
 The pair eliminates only one variable and their complements.
= BC
Quads:
 The quad eliminates two variables and their complements.
Y= ABC + ABC + ABC + ABC
= AC (B + B) + AC(B + B)
= AC + AC
= C (A + A) = C
Octets:
 The octets are three variables and their complements.
4.5.2 Karnaugh Simplifications
 Truth table
 Overlapping groups
 Rolling the map
 Redundant group
4.5.3 Idea Noticed Before Looping
 We visualize all x’s are 1s and try to form largest groups that include the real 1’s.
 We visualize all remaining x’s as 0’s.
Y A BC A BC
 
 
A A BC
 

4.5.4 Simplification of Logic Functions
 Construct karnaugh map.
 Encircle (loop) the possible octets, quads and pairs.
 If any isolated ‘1’s remains, encircles each.
 Eliminates any redundant groups.
 Write the Boolean expression corresponding to the octet, quad and pair loops.
4.6 HALF ADDER AND FULL ADDER
4.6.1 Introduction
 In this set of adders, we present the two basic types of adders:
 Half adders
 Full adders.
 Each type of adder functions to add two binary bits. In order to understand the
functioning of either of these circuits, we must speak of arithmetic in terms that I
learned in the second grade.
 In the first grade, I learned by “plus tables”, specifically the sum of adding
any two one–digit numbers: 2 + 2 = 4, 2 + 3 = 5, etc.
 In the second grade, I learned how to add numbers that had more than one
digit each: 23 + 34 = 57, but 23 + 38 = 61.
 This adaptation of addition to multiple digit numbers gives rise to the full adder.
 In general all arithmetic are done as: 0 + 0 = 0, 0 + 1 = 1, and1 + 0 = 1.
 In decimal arithmetic: 1 + 1 = 2.
 In binary arithmetic what is 1 + 1?
 We have just noted that the decimal number 2 is represented in binary as 10.
 It must be the case that, in binary addition, we have the sum as
 1 + 1 = 10

 This reads as “the addition 1 + 1 results in a sum of 0 and a carry–out of 1”.
4.6.2 Half Adder
 The half adder adds two single binary digits A and B. It has two outputs, sum (S)
and carry (C).
 The carry signal represents an overflow into the next digit of a multi-digit addition.
The value of the sum is 2C + S. The simplest half-adder design, pictured on the left,
incorporates anXOR gate for S and an AND gate for C. With the addition of an OR
gate to combine their carry outputs, two half adders can be combined to make a full
adder.
 The half-adder adds two inputs bits and generate carry and sum which are the two
outputs of half-adder.
(a) Implementing Half Adder
 We need equations for each of the Sum and Carry. Because we have used a
truth table to specify these functions, we consider Boolean expressions.Note that
the carry is the logical AND of the two inputs: Carry = A B.
 The sum can be given in two equivalent expressions. Fig (a) represents the simplest
expression uses the exclusive OR function: Sum = A B. Fig(b) represents an
equivalent expression in terms of the basic AND, OR, and NOT is:
(b) Logic Diagram
Fig (a) Fig (b)
Sum A B A B
   

(c) Truth Table
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
4.6.3 Full Adder
 Schematic symbol for a 1-bit full adder with Cin and Cout drawn on sides of block to
emphasize their use in a multi-bit adder
 A full adder adds binary numbers and accounts for values carried in as well as out.
A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A
and B are the operands, and Cin is a bit carried in from the next less significant
stage.The full-adder is usually a component in a cascade of adders, which add 8, 16,
32, etc. bit wide binary numbers.
 The circuit produces a two-bit output, output carry and sum typically represented
by the signals Cout and S, where .
(a) Implementation of Full Adder
 A full adder can be implemented in many different ways such as with a custom
transistor-level circuit or composed of other gates. One example implementation is
with and .
 In this implementation, the final OR gatebefore the carry-out output may be
replaced by anXOR gate without altering the resulting logic. Using only two types
out
sum 2 C S
  
in
S A B C
   out in
C (A·B) (C ·(A B))
  

of gates is convenient if the circuit is being implemented using simple IC chips
which contain only one gate type per chip. In this light, Cout can be implemented as
.
 A full adder can be constructed from two half adders by connecting A and B to the
input of one half adder, connecting the sum from that to an input to the second
adder, connecting Ci to the other input and OR the two carry outputs. Equivalently,
S could be made the three-bit XOR of A, B, and Ci, and Cout could be made the
three-bit majority function of A, B, and Cin.
(b) Logic Diagram
(c) Truth Table
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
(d) One Circuit for the Full Adder
 Here is the traditional AND/OR/NOT circuitry for the full adder. The circuit above
implements the following two expressions, where C is the carry–in to the full adder.
out in
C (A·B) (C ·(A B))
  

 Suppose we let the carry–in C = 0. Then = 1.What we have then is as follows.
Carry = A B + A 0 + B 0
= A B
As expected, a full adder with carry–in set to zero acts likes a half adder.
The Full Adder with C = 0
4.6.4 The Full Adder and Half Adder as Circuit Elements
 When we build circuits with full adders or half adders, it is important to focus on
the functionality and not on the implementation details. For this reason, we denote
each circuit as a simple box with inputs and outputs.
A B C A B C A B C A B C
Sum           

Carry A B A C B C
     
C
A B 0 A B 1 A B 1 A B 0
Sum           

A B A B
   
  


 The figure on the left depicts a full–adder with carry–in as an input.
 The figure on the right depicts a half–adder with no carry–in as input.
 The figure in the middle depicts a full–adder acting as a half–adder.
(a) A Four Bit-Full Adder
 Here is a depiction of a four–bit full adder to add two binary numbers,
depicted as A3A2A1A0 and B3B2B1B0.Note that the carry–out from the unit’s stage
is carried into the two’s stage. In general, the carry is propagated from right to left,
in the same manner as we see in manual decimal addition. This is called a “ripple
carry adder”.
 Here is an example of its output. The 4–bit sum is truncated to 1001.
 1110
+ 1011
11001
 Note that the unit’s adder is implemented using a full adder.
(b) Propagating The Carry Bits
 Just as in standard arithmetic, when done by hand, the carry of one stage
is propagated as a carry–in to the next higher stage.

(c) CONCLUSION:
 Thus the set of binary adders i.e., half adder and full adder has been mentioned and
summarized as shown above.
4.7 FLIP FLOP
4.7.1 Introduction
 In electronics, a flip-flop or latch is a circuit that has two stable states and can be
used to store state information. A flip-flop is a bistable multivibrator.
 The circuit can be made to change state by signals applied to one or more control
inputs and will have one or two outputs. It is the basic storage element in sequential
logic.
 Flip-flops and latches are used as data storage elements. Such data storage can be
used for storage of state, and such a circuit is described as sequential logic.
 Flip-flops can be either simple ,the simple ones are commonly called latches.
 The word latch is mainly used for storage elements, while clocked devices are
described as flip-flops.
 A latch is level-sensitive, whereas a flip-flop is edge-sensitive.
Flip-flop types
Flip-flops can be divided into common types:
 SR ("set-reset"),
 D ("data" or "delay)
 T ("toggle")
 JK types

4.7.2 Simple Set-Reset Latches
SR NOR LATCH
 When using static gates as building blocks, the most fundamental latch is the
simple SR latch, where S and R stand for set and reset.
 It can be constructed from a pair of cross-coupled NOR logic gates.
 The stored bit is present on the output marked Q.
 While the S and R inputs are both low, feedback maintains the Q and Q outputs in a
constant state, with Q the complement of Q.
 If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced
high, and stays high when S returns to low; similarly, if R is pulsed high while S is
held low, then the Q output is forced low, and stays low when R returns to low.
SR latch operation
Characteristic table Excitation table
S R Qnext Action Q Qnext S R
0 0 Q hold state 0 0 0 X
0 1 0 Reset 0 1 1 0
1 0 1 Set 1 0 0 1
1 1 X not allowed 1 1 X 0

 The R = S = 1 combination is called a restricted combination or a forbidden
state because, as both NOR gates then output zeros, it breaks the logical equation Q
= not Q.
 The combination is also inappropriate in circuits where both inputs may go
low simultaneously (i.e. a transition from restricted to keep).
 The output would lock at either 1 or 0 depending on the propagation time relations
between the gates .
 To overcome the restricted combination, one can add gates to the inputs that would
convert (S,R) = (1,1) to one of the non-restricted combinations. That can be:
 Q = 1 (1,0) – referred to as an S (dominated)-latch
 Q = 0 (0,1) – referred to as an R (dominated)-latch
4.7.3 SR NAND latch
 Set and reset now become active low signals, denoted S and R respectively.
Otherwise, operation is identical to that of the SR latch.
 Historically, SR-latches have been predominant despite the notational
inconvenience of active-low inputs
SR latch operation
S R Action
0 0
Restricted
combination
0 1 Q = 1
1 0 Q = 0
1 1 No Change
Symbol for an SRNAND latch

4.7.4 JK latch
 The JK latch is much less frequently used than the JK flip-flop.
The JK latch follows the following state table:JK latch truth table
J K Qnext Comment
0 0 Q No change
0 1 0 Reset
1 0 1 Set
1 1 Q Toggle
 Hence, the JK latch is an SR latch that is made to toggle its output when passed the
restricted combination of 11.
 Unlike the JK flip-flop, the 11 input combination for the SR latch is not useful
because there is no clock that directs toggling.
4.7.5 Gated SR Latch
 A synchronous SR latch (sometimes clocked SR flip-flop) can be made by adding a
second level of NAND gates to the inverted SR latch
 With E high (enable true), the signals can pass through the input gates to the
encapsulated latch.
 All signal combinations except for (0,0) = hold then immediately reproduce on the
(Q,Q) output, i.e. the latch is transparent.
 E low (enable false) the latch is closed (opaque) and remains in the state it was left
the last time E was high.

Gated SR latch operation
E/C Action
0 No action (keep state)
1 The same as non-clocked SR latch
4.7.6 D FLIP-FLOP
 The D ﬂip-ﬂop is widely used. It is also known as a data or delay flip-flop.
 The D flip-flop captures the value of the D-input at a definite portion of the clock
cycle (such as the rising edge of the clock).
 That captured value becomes the Q output. At other times, the output Q does not
change.
Truth Table
Clock D Qnext
Rising edge 0 0
Rising edge 1 1
Non-Rising X Q

 Most D-type flip-flops in ICs have the capability to be forced to the set or reset state
(which ignores the D and clock inputs), much like an SR flip-flop.
 Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops.
 By setting S = R = 0, the flip-flop can be used as described above.
Truth Table
Inputs Outputs
S R D > Q Q'
0 1 X X 0 1
1 0 X X 1 0
1 1 X X 1 1
 These flip-flops are very useful, as they form the basis for shift registers, which are
an essential part of many electronic devices.
 An exception is that some flip-flops have a "reset" signal input, which will reset Q
(to zero), and may be either asynchronous or synchronous with the clock

Classical positive-edge-triggered D flip-flop
 This circuit consists of two stages implemented by SR NAND latches.
 If the clock is low, both the output signals of the input stage are high regardless of
the data input.
 The output latch is unaffected and it stores the previous state.
 When the clock signal changes from low to high, only one of the output voltages
goes low and sets/resets the output latch.
 if D = 0, the lower output becomes low; if D = 1, the upper output becomes low.
 If the clock signal continues staying high, the outputs keep their states regardless of
the data input and force the output latch to stay in the corresponding state as the
input logical zero remains active while the clock is high. Hence the role of the
output latch is to store the data only while the clock is low.
Master–slave edge-triggered D flip-flop
 A master–slave D flip-flop is created by connecting two gated D latches in series,
and inverting the enable input to one of them.
 It is called master–slave because the second latch in the series only changes in
response to a change in the first (master) latch.

A master–slave D flip-flop. It responds on the falling edge of the enable input
 For a positive-edge triggered master–slave D flip-flop, when the clock signal is low
(logical 0) the "enable" seen by the first or "master" D latch (the inverted clock
signal) is high (logical 1).
 This allows the "master" latch to store the input value when the clock signal
transitions from low to high.
 As the clock signal goes high (0 to 1) the inverted "enable" of the first latch goes
low (1 to 0) and the value seen at the input to the master latch is "locked".
 The twice inverted "enable" of the second or "slave" D latch transitions from low to
high (0 to 1) with the clock signal.
 This allows the signal captured at the rising edge of the clock by the now "locked"
master latch to pass through the "slave" latch.
 When the clock signal returns to low (1 to 0), the output of the "slave" latch is
"locked",
 The value seen at the last rising edge of the clock is held while the "master" latch
begins to accept new values in preparation for the next rising clock edge.
By removing the leftmost inverter in the circuit at side, a D-type flip-flop that strobes
on the falling edge of a clock signal can be obtained.

This has a truth table like this:
D Q > Qnext
0 X Falling 0
1 X Falling 1
4.7.7 T FLIP-FLOP
 If the T input is high, the T flip-flop changes state ("toggles") whenever the clock
input is strobes.
 If the T input is low, the flip-flop holds the previous value.
 This behavior is described by the characteristic
Truth Table
T flip-flop operation
Comment Comment
0 0 0 hold state (no clk) 0 0 0 No change
0 1 1 hold state (no clk) 1 1 0 No change

1 0 1 Toggle 0 1 1 Complement
1 1 0 Toggle 1 0 1 Complement
 When T is held high, the toggle flip-flop divides the clock frequency by two; that
is, if clock frequency is 4 MHz, the output frequency obtained from the flip-flop
will be 2 MHz.
 A T flip-flop can also be built using a JK flip-flop (J & K pins are connected
together and act as T) or D flip-flop (T input and Qprevious is connected to the D
input through an XOR gate).
4.7.8 JK FLIP-FLOP
 The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by
interpreting the S = R = 1 condition as a "flip" or toggle command.
 Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the
combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J
= K = 1 is a command to toggle the flip-flop.
 Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current
state.
 To synthesize a D flip-flop, simply set K equal to the complement of J.
 Similarly, to synthesize a T flip-flop, set K equal to J.
 The JK flip-flop is therefore a universal flip-flop, because it can be configured to
work as an SR flip-flop, a D flip-flop, or a T flip-flop.
 Setup time is the minimum amount of time the data signal should be held
steady before the clock event so that the data are reliably sampled by the clock.
This applies to synchronous input signals to the flip-flop.
 Hold time is the minimum amount of time the data signal should be held
steady after the clock event so that the data are reliably sampled. This applies to
synchronous input signals to the flip-flop.
 Recovery time is like setup time for asynchronous ports (set, reset). It is the time
available between the asynchronous signals going inactive and the active clock
edge.
 The characteristic equation of the JK flip-flop is:

JK flip-flop operation
J K Comment Qnext Q J K Comment Qnext
0 0 hold state Q 0 0 X No Change 0
0 1 Reset 0 0 1 X Set 1
1 0 Set 1 1 X 1 Reset 0
1 1 Toggle Q 1 X 0 No Change 1
 Removal time is like hold time for asynchronous ports (set, reset). It is the time
between active clock edge and asynchronous signal going inactive.
4.8 INTRODUCTION TO ANALOG TO DIGITAL AND DIGITAL TO
ANALOG CONVERTER
(a) Analog to Digital Conversion
 Digital system such as microprocessor use a binary system of ones and zeros, we
have to convert signal analog form to digital form.
 This circuit that performs conversion is called A/D convertor.
(b) Digital to Analog Conversion
 When a binary output from a digital system must be converted to some equivalent
analog voltage or current.
next
Q JQ KQ
 

(c) Advantages of Digital Signal
 High noise immunity
 Adjustable precision
 Ease of design (automation) and
 Fabrication, therefore, low cost
 Better Reliability
 Less need for calibration and maintenance
 Ease of diagnosis and repair
 Easy to duplicate similar circuits
 Easily controllable by computer
(d) Disadvantages of Digital Signals
 Lower speed
 Needs converters to communicate with real world, therefore more expensive And
less precision
e) Types of Analog to Digital Conversion:
 Single ramp or single slope
 Dual slope
 Successive approximation
 Flash
 Delta modulation
 Adaptive delta modulation
In this types analog to digital conversion classified in totwo general groups
One technique involves comparing a given analog signal with the internally generated
reference voltages.

In these technique involves,
 Successive approximation
 Flash
 Delta modulation
 Adaptive delta modulation
In another technique involves changing an analog signal into time or frequency,
 Single ramp or single slope
 Dual slope
4.8.1 Single Slope ADC
 It consists of a Ramp generator or swatooth generator and BCD or binary counter.
 Reset signal is provide to the ramp generator and the counters. Thus the counters
are resettled to zeros.
 Analog input voltage Uri is applied to the positive terminal of the comparator. As
this more positive than the negative input, the comparator goes high.
 The output of the ramp generator is applied to the negative terminal of the
comparator. The high output of comparator enables the AND gate which allows
clock to the counters and this output starts the ramp. The ramp voltage goes until
exceeds the input voltage. When it exceeds Uin, the comparator goes low.

 This disables AND gate which in turn stops the clock to the counters.the clock
circuitry provides the latch signal which is used to latch the counter data.
 The reset signal resets the counter to 0’s and also resets the ramp generator.the
latched data is then displayed using decoder and a display device.
Limitations Of Single Slop:
 Its resolutions are less. Hence for applications which requires resolution of 9 part in
20,000 or more this ADC is not stable.
 Variations in ramp generator due to time, temperature or input voltage sensitivity
also cause a lot of problems.
4.8.2 Dual Slope ADC
 This converter is an indirect method for A/D conversions where an analog voltage
and reference voltage are converted into time periods by an integrator, and then
measured by a counter. The speed of this conversion is slow but the accuracy is
high.
 It consists of integrator, comparator, binary counter, output latch and reference
voltage the ramp generator input is switched between the analog input voltage vi
and a reference voltage -Vref.
 The analog switch is controlled by the MSB of the counter. When the MSB is a
logic 0.the voltage between being measured is connected to the ramp generator to
the generator input. When MSB is logic 1, the negative is connected to the ramp
generator.

 At time t = 0,analog switch is connected to analog input voltage vi so that the
analog input voltage is integration .
Advantages of Dual Slope:
 It is highly accurate.
 Its cost is low.
 It is immune to temperature caused variations in R1 and C1.
Disadvantages
 Slow
 High precision external components required to achieve accuracy
t
0
1
Voi Vi dt
R1C1
  
it
R1C1

 
t1
Vi Vrt2 / R1C1
R1C1

t1
t2 Vi
r


counts
digital output t2
seconds
 
  
 
counts Vi
digital output t1
seconds Vr
   
    
   

4.8.3 Successive Approximation ADC
The DAC input code such that its output is within 1/2LSB of the analog input Vi to
be A/D converted. The code that achieves this represents the desired ADC output .It uses very
efficient code searching strategy called binary search.
It works,
 Sets MSB
 Converts MSB to analog using DAC
 Compares guess to input
 Set bit
 Test next bit
Where,
Tc=conversion time
 
Tc T n 1
 

T= clock period
n=number of bits
Advantages
 Capable of high speed
 Medium accuracy compared to other ADC types
 Good tradeoff between speed and cost
Disadvantages
 Higher resolution successive approximation ADCs will be slower
 Speed limited ~5Msps
4.8.4 Flash Type ADC

4.8.5 3-Bit Flash Type Converter
 “parallel A/D”
 Uses a series of comparators
 Each comparator compares Vin to a different reference voltage, starting w/ Vref =
1/2 lsb
 Comparators required to perform A/D conversion increases very rapidly, and it may
not be feasible to Use this approaches number of bits exceeds six or so. The greatest
advantage of this technique lies its capability to execute extremely fast analogue-to-
digital conversion.
Number of comparators =2n -1
Where,
Fmax = max input frequency
Tc = conversion time
N = numbers of bits
4.8.6 Sigma/Delta Modulation
 Oversampled input signal goes in the integrator
 Output of integration is compared to GND
  n
1
f max
2 Tc 2



 Iterates to produce a serial bit stream.
 Output is serial bit stream with of1’s proportional Vin
Advantages
 High resolution
 No precision external components needed
Disadvantages
 Slow due to oversampling
4.8.7 Types of D/A Converter
 Many types of DACs available.
 Usually switches, resistors, and op-amps used to implement conversion
Two Types:
 Binary Weighted Resistor
 R-2R Ladder
4.8.7.1 Binary Weighted Resistor
 Utilizes a summing op-amp circuit.
 Weighted resistors are used to distinguish each bit from the most significant to the
least significant.
 Transistors are used to switch between Vref and ground (bit high or low.
 Assume Ideal Op-amp.
 No current into op-amp.
 Virtual ground at inverting input.
 Vout = -IRf

 Voltages V1 through Vn are either Vref if corresponding bit is high or ground if
corresponding bit is low.
 V1 is most significant bit
 Vn is least significant bit
If Rf=R/2,
For example, a 4-Bit converter yields
Where b3 corresponds to Bit-3, b2 to Bit-2, etc.
Advantages:
 Simple Construction/Analysis
 Fast Conversion
3
1 2 n
out f f n-1
V
V V V
V IR R
R 2R 4R 2 R
 
      
 
 
3
1 2 n
out f n
V
V V V
V IR
2 4 8 2
 
      
 
 
out ref 3 2 1 0
1 1 1 1
V V b b b b
2 4 8 16
 
    
 
 

Disadvantages:
 Requires large range of resistors (2000:1 for 12-bit DAC) with necessary high
precision for low resistors
 Requires low switch resistances in transistors
 Can be expensive. Therefore, usually limited to 8-bit resolution.
4.8.7.2 R-2R Ladder
Each bit corresponds to switch:
 If the bit is high, the corresponding switch is connected to the inverting input of the
op-amp.
 If the bit is low, the corresponding switch is connected to ground

  
 
eq
2R 2R
R R
2R 2R
 

3 2 2
R 1
V V V
R R 2
 
 
 

 

Where b3 corresponds to bit 3,b2 to bit 2, etc.
If bit n is set, bn=1
If bit n is clear, bn=0
For a 4-Bit R-2R Ladder
For general n-Bit R-2R Ladder or Binary Weighted Resister DAC
Advantages
 Only two resistor values (R and 2R)
 Does not require high precision resistors
Disadvantage
 Lower conversion speed than binary weighted DAC
2 1
1
V V
2

out
V IR
 
1 ref
1
V V
2

3 ref 2 ref 1 ref
1 1 1
V V , V V , V V
8 4 2
  











R
V
b
R
V
b
R
V
b
R
V
b
R
V
16
8
4
2
ref
0
ref
1
ref
2
ref
3
out
out ref 3 2 1 0
1 1 1 1
V V b b b b
2 4 8 16
 
    
 
 
i
n
i
i
n
b
V
V
2
1
1
ref
out 





4.9 REGISTERS AND COUNTERS
4.9.1 Registers
 Registers are groups of flip-flops, where each flip-flop is capable of storing one bit
of information.
 An n-bit register is a group of n flip-flops. The basic function of a register is to hold
information in a digital system and make it available to the logic elements for the
computing process.
 Registers consist of a finite number of flip-flops. Since each flip-flop is capable of
storing either a "0" or a "1", there is a finite number of 0-1 combinations that can be
stored into a register. Each of those combinations is known as state or content of
the register.
 With flip-flops we can store data bitwise but usually data does not appear as single
bits. Instead it is common to store data words of n bit with typical word lengths of
4, 8, 16, 32 or 64 bit. Thus, several flip-flops are combined to form a register to
store whole data words.
 Registers are synchronous circuits thus all flip-flops are controlled by a common
clock line. As registers are often used to collect serial data they are also called
accumulators. There exist several types of registers as there are -
4.9.2 Shift Registers
 Information often comes bitwise i.e. one bit at every clock pulse. Shift registers are
used to store such data.
 A shift register has one input. Every clock pulse one bit is loaded into the first flip-
flop of the register while all the actual flip-flop contents are shifted and the “oldest”
bit got dropped. If the output of all flip-flops (and therefore the register’s complete
content) are read from the lines Q1 to Qn the register is used as Serial In – Parallel
Out (SIPO).

 A typical purpose for such a SIPO register is to collect data that is delivered bitwise
and that is needed in n-bit data words (e.g. to convert the signals from serial ports
of a computer: the line transports 1 bit a time, the computer uses 8, 16 or 32 bit data
words). Shifting bits are important for mathematical operations: if the output of the
whole register is interpreted as a binary number, shifting by one bit corresponds to
multiplying or dividing by 2 (depends on which flip-flop is interpreted as MSB).
4.9.3 Cyclic Registers
 Sometimes it is necessary to “recycle” the same values again and again. Thus the
bit that usually would get dropped is fed to the register input again to receive a
cyclic serial register
4.9.3.1 Parallel In-Serial Out
 As there is a need for serial – parallel conversion the inverse operation is equally
required. It is done by a Parallel In – Serial Out register (PISO) that allows loading
data as whole data words and serial shifting.

 For this operation it needs two control lines: one to trigger the shifting and one to
control when a new data word is loaded to the register . it is prepared by clearing all
the status of the flipflops output by using a clear function i.e. each flipflop is equals
to 0 then shifting it by taking a single bit of the given input that input is shifts the
present bits in the flipflop to the next flipflop
4.9.4 Barrel Shifters
 A barrel shifter is a digital circuit that can shift a data word by a specified number
of bits in one clock cycle. It can be implemented as a sequence of multiplexers
(mux.), and in such an implementation the output of one mux is connected to the
input of the next mux in a way that depends on the shift distance. For example, take
a 4-bit barrel shifter, with inputs A, B, C and D. The shifter can cycle the order of
the bits ABCD as DABC, CDAB, or BCDA; in this case, no bits are lost. That is, it
can shift all of the outputs up to three positions to the right (and thus make any
cyclic combination of A, B, C and D). The barrel shifter has a variety of
applications, including being a useful component in microprocessors (alongside the
ALU).
 A common usage of a barrel shifter is in the hardware implementation of floating-
point arithmetic.
 For a floating-point add or subtract operation, the significand of the two numbers
must be aligned, which requires shifting the smaller number to the right, increasing
its exponent, until it matches the exponent of the larger number.

 This is done by subtracting the exponents, and using the barrel shifter to shift the
smaller number to the right by the difference, in one cycle. If a simple shifter were
used, shifting by n bit positions would require n clock cycles.
4.9.5 Counters
 A counter is a sequential circuit that – counts. That means it proceeds through a
pre-defined sequence of states where the state of the circuit is determined by the
states of all its flip flops.
 As every state of the circuit can be given a number we can say that a counter
produces a sequence of numbers. A commonly used approach is to interpret a
circuits state as dual number, so if flip-flop A,B and C are all 0 the counter’s state is
0. if A is 1, B is 0 and C is 1 the counter’s state is 101 = 5 and so on.
 The most basic counters will simply increment by 1 with every clock pulse, so after
state 100 it will go to 101; the next pulse will let it switch to 110 etc. It is possible
to design counters with any needed counting sequence.
 Even though asynchronous sequential circuits are not subject of this course the
asynchronous counter is presented here exceptionally to give a slight impression.

(a) Counters
Are available in two categories
 Ripple counters(Asynchronous)
 Synchronous counters
4.9.5.1 Ripple Counters (Asynchronous)
 The flip-flop output transition serves as a source fortriggering other flip-flops.
 The C input of some or all flip-flops are triggered NOT by the common clock
pulses
Example:
 Binary ripple counters
 BCD ripple counters
4.9.5.2 Synchronous Counters
 The C inputs of all flip-flops receive the common clock pulses
Example:
 Binary counter
 Up-down Binary counter
 BCD Binary counter
 Ring counter
 Johnson counter
(a) Ripple Counters
 use complemented flip flop

Q (t + 1) = Q`(t)
(b) Binary Ripple Up Counter
 Consist of a series of connection of negative edge triggering complementing flip-flops
with the output of each flip-flop connected to the C input of the next high order flip
flop.
 The flip flop holding the LSB receives the input pulses.
 The count starts with binary 0 and increments by one with each count pulse
 The LSB A is complemented with each count pulse input. Transition of A from 1 to 0
complement B and so on
 For positive edge triggered flip-flops the counter countdown: e.g start from 15 to 14 to
13 to…….
 The diagram is same as the count up binary counter except that the flip-flop trigger on
the positive edge of the clock.

 If negative edge triggered flip-flops are used then the C input of each flip-flop must
be connected to the complement output of the previous flip-flop. So, when the true
output goes from 0 to 1, the complement will go from 1 to o and complement the
next flip flop as required

(c) Ripple Down Counter
(d) BCD Ripple Counter, Decade Counter
 This counter counts upwards on each negative edge of the input clock signal
starting from "0000" until it reaches an output "1001“.

 Both outputs qa and qd are now equal to logic "1" and the output from the nand
gate changes state from logic "1" to a logic "0" level when the clock goes to level
one and whose output is also j-k flip-flops
(e) Decade Counter Timing Diagram

(f) Decade Counters Applications
Synchronous Counters
(a) Binary Synchronous Counter

Logic Diagram Serial Gating
 The FF in the LSB in complemented with every pulse. A flip flop in other position
is complemented when all the bits in the lower significant positions are 1
 Synchronous counter have a regular pattern and can be constructed with
complementing flip flops and gates
(b) Up-Down Binary Counters
 It can progress in either direction (up or down)
(0 1 2 3 4 5) (4 3 2 )(3 4 5 6 7)(6 5)etc...
up dn up dn
 The count down counter can be constructed as follows, the inputs to the AND gates
must come from them complement outputs instead of the normal outputs of the
previous flip flops.
 The Up and down counters can be combined in one circuit to form a counter
capable of counting either up or down.
(c) Up Down Binary Count:

(d) Synchronous BCD Counter
 It does not have regular pattern as in binary counter, so procedure of sequential
design should be used.
Use k-map to find input functions to the T flipflops as:
 TQ1 = 1, TQ2 = Q’8Q1 TQ4 = Q2Q1; TQ8 = Q8Q1 + Q4Q2Q1
(e) JK Synchronous Decade Counter
(f) Binary Counter With Parallel Load
 It can be loaded with initial value to start counting.

 A counter with parallel load can be used to generate any count sequence.
 Figures below show two ways in which a counter with parallel load is used to
generate the BCD count.

REVIEW QUESTIONS
1. Convert (100001110.010)2 to decimal.
2. Give that (79)10 = (142)b determinethe value of b.
3. Perform the arithmetic operations 35+40 and (-3.5) + (-40) with binary number in
signed 2’s complement representation.
4. Convert (342.45)10 to binary and Octal.
5. Perform the following arithmetic operation using 1’s complement scheme. (4-8) ,(8-4),
(-2-3)
6. Convert the following: (369)10 = ( )8 =( )16 =( )2.
7. How many bits are required to represent the decimal numbers in the ranges from 0 to
999 using straight binary code? Using BCD codes?
8. Explain how addition and subtraction can be performed with 1’s complement and 2’s
complement representations with suitable examples.
9. State de-Morgan’s Law.
10. Why NAND gate is called as a universal gate?
11. Realize XOR function using only NAND gates.
12. How do you implement y = A + B using a 3 input OR gate?
13. Define distributive law.
14. What is mean by duality in Boolean algebra?
15. Simplify the following function using algebraic method.
a) F = C (B + C) (A + B +C)
40. Implement AND and OR using NAND and NOR gates.
41. Give the truth table for JK flip-flop?
42. Name the problem associated with the asynchronous counter.

43. What is a universal shift register?
44. Give the excitation table for JK flip-lop.
45. Draw the timing diagram for a 3 stage ring counter.
46. How do you construct D flip-flop and T Flip-lop using JK flip-flop.
47. Distinguish between Synchronous and asynchronous counter.
48. Draw the circuit of serial in and serial out shift register and explain its operation.
49. Name the two problems that may arise in the ripple counter.
50. Draw the circuit of up-down counter and explain its working.
51. What is mean by the term edge triggered?
52. Describe the operation of BCD counter.
53. Draw the logic for 4-stage ring counter using JK flip-flo0p?
54. Define the hold time requirement of a clocked FF?
55. Show the T flip-flop implementation from S-R flip-flop?
56. Give the logical expression for sum and carry for a half adder.
57. Obtain the expression for SUM and CARRY outputs of a full adder and implement the
same.

APPENDIX – A
TWO MARK QUESTIONS AND ANSWERS
1. Define binary logic?
Binary logic consists of binary variables and logical operations. The variables are
designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having
only two distinct values: 1 and 0. There are three basic logic operations: AND, OR, and
NOT.
2. Convert (634)8 to binary
6 3 4
110 011 100
Ans = 110011100
3. Convert (9B2 - 1A) H to its decimal equivalent.
N = 9 x 162 + B x 161 + 2 x 160 + 1 x 16-1 + A(10) x 16-2
= 2304 + 176 + 2 + 0.0625 + 0.039
= 2482.1
4. State the different classification of binary codes?
1. Weighted codes
2. Non - weighted codes
3. Reflective codes
4. Sequential codes
5. Alphanumeric codes
6. Error Detecting and correcting codes.
5. Convert 0.640625 decimal number to its octal equivalent.
0.640625 x 8 = 5.125

AA. 2 Basic Electrical and Electronics Engineering
0.125 x 8 = 1.0
= 0.640 625 10 = (0.51)8
6. Convert 0.1289062 decimal number to its hex equivalent.
0.1289062 x 16 = 2.0625
0.0625 x 16 = 1.0
= 0.2116
7. Convert 22.64 to hexadecimal number. (NOV 2005)
16 22 - 6
16 1 - 1
0
0.64 x 16 = 10.24
0.24 x 16 = 3.84
0.84 x 16 = 13.44
.44 x 16 = 7.04
Ans = (16. A 3 D 7)16
8. State the steps involved in Gray to binary conversion?
The MSB of the binary number is the same as the MSB of the gray code number. So
write it down. To obtain the next binary digit, perform an exclusive OR operation
between the bit just written down and the next gray code bit. Write down the result.
9. Convert gray code 101011 into its binary equivalent.
Gray Code: 1 0 1 0 1 1
Binary Code: 1 1 0 0 1 0
10. Substract (0 1 0 1)2 from (1011)2
1 0 1 0
0 1 0 1
Answer = 0 1 1 0

Two Mark Question and Answers AA.3
11. Add (1 0 1 0)2 and (0 0 1 1)2 (APR 2005)
1 0 1 0
0 0 1 1
Answer = (1 1 0 1)2
12. Using 10’s complement subtract 72532 - 3250
M = 72532
10’s complement of N = + 96750
Sum = 169282
Discard end carry
Answer = 69282
13. Find 2’S complement of (1 0 1 0 0 0 1 1)2
0 1 0 1 1 1 0 0 1 ( - 1’s Complement )
+0 0 0 0 0 0 0 1
0 1 0 1 1 1 0 1 0 ( - 2’s complement. )
14. Substract 1 1 1 0 0 12 from 1 0 1 0 1 12 using 2’s complement method
1 0 1 0 1 1
+ 0 0 0 1 1 1 - 2’s comp. of 1 1 1 0 0 1
1 1 0 0 1 0 in 2’s complement form
Answer (0 0 1 1 1 0 )2
15. Find the excess -3 code and 9’s complement of the number 40310(NOV 2006)
4 0 3
0 1 0 0 0 0 0 0 0 0 1 1
0 0 1 1 0 0 1 1 0 0 1 1 +
0 1 1 1 0 0 1 1 0 1 1 0 ----- excess 3 code
9’s complement 1 0 0 0 1 1 0 0 1 0 0 1

16. What is meant by bit?
A binary digit is called bit
17. Define byte?
Group of 8 bits.
18. List the different number systems?
i) Decimal Number system
ii) Binary Number system
iii) Octal Number system
iv) Hexadecimal Number system
19. State the abbreviations of ASCII and EBCDIC code? (DEC 2005)
ASCII-American Standard Code for Information Interchange.
EBCDIC-Extended Binary Coded Decimal Information Code.
20. What are the different types of number complements?
i. r’s Complement
ii. (r-1)’s Complement.
21. Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction
(a) X - Y and (b) Y - X using 2's complements.
a) X = 1010100
2's complement of Y = 0111101
Sum = 10010001
Discard end carry
Answer: X - Y = 0010001

b) Y = 1000011
2's complement of X = + 0101100
Sum = 1101111
There is no end carry, The MSB BIT IS 1.
Answer is Y-X = -(2's complement of 1101111) = - 0010001
22. Given the two binary numbers X = 1010100 and Y = 1000011, perform the
subtraction (a) X -Y and (b) Y - X using 1's complements.
a) X - Y = 1010100 - 1000011
X = 1010100
1's complement of Y = + 0111100
Sum = 10010000
End -around carry = + 1
Answer: X - Y = 0010001
b) Y - X = 1000011 - 1010100
Y = 1000011
1's complement of X = + 0101011
Sum = + 1101110
There is no end carry.
Therefore the answer is Y - X = -(1's complement of 1101110) = -0010001
23. Write the names of basic logical operators.
1. NOT / INVERT
2. AND
3. OR

24. What are basic properties of Boolean algebra?
The basic properties of Boolean algebra are commutative property, associative property
and distributive property.
25. State the associative property of boolean algebra.
The associative property of Boolean algebra states that the OR ing of several variables
results in the same regardless of the grouping of the variables. The associative property
is stated as follows:
A + (B + C) = (A + B) + C
26. State the commutative property of Boolean algebra.
The commutative property states that the order in which the variables are OR ed makes
no difference. The commutative property is:
A + B = B + A

27. State the distributive property of Boolean algebra.
The distributive property states that AND ing several variables and OR ing the result
with a single variable is equivalent to OR ing the single variable with each of the the
several variables and then AND ing the sums. The distributive property is:
A + BC = (A + B) (A + C)
28. State the absorption law of Boolean algebra.
The absorption law of Boolean algebra is given by X+XY=X, X(X+Y) =X.
29. Simplify the following using De Morgan's theorem [((AB)'C)'' D]'
[((AB)'C)'' D]' = ((AB)'C)'' + D' [(AB)' = A' + B']
= (AB)' C + D'
= (A' + B' )C + D'
30. State De Morgan's theorem.
De Morgan suggested two theorems that form important part of Boolean algebra. They
are,
1) The complement of a product is equal to the sum of the complements.
(AB)' = A' + B'
2) The complement of a sum term is equal to the product of the complements.
(A + B)' = A'B'
31. Reduce A(A + B)
A(A + B) = AA + AB
= A(1 + B) [1 + B = 1]
= A.

32. Reduce A'B'C' + A'BC' + A'BC (APR 2005)
A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C
= A'C' + A'BC [A + A' = 1]
= A'(C' + BC)
= A'(C' + B) [A + A'B = A + B]
33. Reduce AB + (AC)' + AB'C(AB + C)
AB + (AC)' + AB'C(AB + C) = AB + (AC)' + AAB'BC + AB'CC
= AB + (AC)' + AB'CC [A.A' = 0]
= AB + (AC)' + AB'C [A.A = 1]
= AB + A' + C' =AB'C [(AB)' = A' + B']
= A' + B + C' + AB'C [A + AB' = A + B]
= A' + B'C + B + C' [A + A'B = A + B]
= A' + B + C' + B'C
=A' + B + C' + B'
=A' + C' + 1
= 1 [A + 1 =1]
34. Simplify the following expression Y = (A + B)(A + C' )(B' + C' )
Y = (A + B)(A + C' )(B' + C' )
= (AA' + AC +A'B +BC )(B' + C') [A.A' = 0]
= (AC + A'B + BC)(B' + C' )
= AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC'
= AB'C + A'BC'

35. Show that (X + Y' + XY)( X + Y')(X'Y) = 0
(X + Y' + XY)( X + Y')(X'Y) = (X + Y' + X)(X + Y' )(X' + Y) [A + A'B = A + B]
= (X + Y' )(X + Y' )(X'Y) [A + A = 1]
= (X + Y' )(X'Y) [A.A = 1]
= X.X' + Y'.X'.Y
= 0 [A.A' = 0]
36. Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC
ABC + ABC' + AB'C + A'BC = AB(C + C') + AB'C + A'BC
= AB + AB'C + A'BC
= A(B + B'C) + A'BC
= A(B + C) + A'BC
= AB + AC + A'BC
= B(A + C) + AC
= AB + BC + AC
= AB + AC +BC ...Proved
37. Convert the given expression in canonical SOP form Y = AC + AB + BC
Y = AC + AB + BC
=AC(B + B' ) + AB(C + C' ) + (A + A')BC
=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC
=ABC + ABC' +AB'C + AB'C' [A + A =1]
38. Define duality property.
Duality property states that every algebraic expression deducible from the postulates of
Boolean algebra remains valid if the operators and identity elements are interchanged.

If the dual of an algebraic expression is desired, we simply interchange OR and AND
operators and replace 1's by 0's and 0's by 1's.
39. Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x(y'z' + yz)
applying De-Morgan's theorem.
F1' = (x'yz' + x'y'z)' = (x'yz')'(x'y'z)' = (x + y' + z)(x + y +z')
F2' = [x(y'z' + yz)]' = x' + (y'z' + yz)'
= x' + (y'z')'(yz)'
= x' + (y + z)(y' + z')
40. Simplify the following expression
Y = (A + B) (A = C) (B + C)
= (A A + A C + A B + B C) (B + C)
= (A C + A B + B C) (B + C)
= A B C + A C C + A B B + A B C + B B C + B C C
= A B C
41. What is a Logic gate?
Logic gates are the basic elements that make up a digital system. The electronic gate is
a circuit that is able to operate on a number of binary inputs in order to perform a
particular logical function.
42. What are the basic digital logic gates?
The three basic logic gates are
AND gate
OR gate
NOT gate

43. Which gates are called as the universal gates? What are its advantages?
The NAND and NOR gates are called as the universal gates. These gates are used to
perform any type of logic application.
44. Implement the Boolean Expression for EX – OR gate using NAND Gates.
(NOV 2003)
45. Define combinational logic.
When logic gates are connected together to produce a specified output for certain
specified combinations of input variables, with no storage involved, the resulting
circuit is called combinational logic.
46. Explain the design procedure for combinational circuits
The problem definition
Determine the number of available input variables & required O/P variables.
Assigning letter symbols to I/O variables
Obtain simplified Boolean expression for each O/P.
Obtain the logic diagram.
47. Define Half adder and full adder
The logic circuit that performs the addition of two bits is a half adder. The circuit that
performs the addition of three bits is a full adder.

48. Draw the logic Symbol and construct the truth table for the two input EX – .
49. Define Decoder? (NOV 2006)
A decoder is a multiple - input multiple output logic circuit that converts coded inputs
into coded outputs where the input and output codes are different.
50. What is binary decoder?
A decoder is a combinational circuit that converts binary information from n input lines
to a maximum of 2
51. Define Encoder?
An encoder has 2n input lines and n output lines. In encoder the output lines generate
the binary code corresponding to the input value.
52. What is priority Encoder?
A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest
priority will take precedence.

53. Define multiplexer? (NOV 2006)
Multiplexer is a digital switch. If allows digital information from several sources to be
routed onto a single output line.
54. What do you mean by comparator
A comparator is a special combinational circuit designed primarily to compare the
relative magnitude of two binary numbers.
55. Which gate is equal to AND-invert Gate?
NAND gate.
56. Which gate is equal to OR-invert Gate?
NOR gate.
57. Bubbled OR gate is equal to--------------
NAND gate
58. Bubbled AND gate is equal to-------------- (APR 2004)
NOR gate
59. State the limitations of karnaugh map.
i) Generally it is limited to six variable map (i.e) more then six variable involving
expression are not reduced.
ii) The map method is restricted in its capability since they are useful for simplifying only
Boolean expression represented in standard form.
60. What is a karnaugh map?
A karnaugh map or k map is a pictorial form of truth table, in which the map diagram is
made up of squares, with each squares representing one minterm of the function.
61. Find the minterms of the logical expression Y = A'B'C' + A'B'C + A'BC + ABC'
Y = A'B'C' + A'B'C + A'BC + ABC'
= m0 + m1 +m3 +m6
= ∑m(0, 1, 3, 6)

62. Write the maxterms corresponding to the logical expression
Y = (A + B + C' )(A + B' + C')(A' + B' + C)
= (A + B + C' )(A + B' + C')(A' + B' + C)
= M1.M3.M6
= M(1,3,6)

12 Marks Questions
1. Simplify the boolean function using tabulation method.
F = (0, 1, 2, 8, 10, 11, 14, 15)
 List all the min terms
 Arrange them as per the number of ones based on binary equivalent
 Compare one group with another for difference in one and replace the bit with dash.
 Continue this until no further grouping possible.
 The unchecked terms represent the prime implicants.
F = W'X'Y' + X'Z' + WY
2. Determine the prime implicants of the function
F (W, X, Y, Z) = (1, 4, 6, 7, 8, 9, 10, 11, 15) (NOV 2005)
 List all the min terms
 Arrange them as per the number of ones based on binary equivalent
 Compare one group with another for difference in one and replace the bit with dash.
 Continue this until no further grouping possible.
 The unchecked terms represent the prime implicants.
F = X'Y'Z + W'XZ' + W'XY + XYZ + WYZ + WX'
Minimum Set of prime implicants F = X'Y'Z + W'XZ' + XYZ + WX'
3. Simplify the Boolean function using K-map.
F(A, B, C, D, E) = (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31) (APR 2004)
Five variables hence two variable k maps one for A = 0 and the other for A = 1.
F = A'B'E' + BD'E + ACE
4. Obtain the canonical sum of products of the function Y = AB + ACD

Y = AB (C + C')(D + D') + ACD (B + B')
Y = ABCD + ABCD' + ABC'D + ABC'D' + AB'CD
5. State the postulates and theorems of Boolean algebra.
X + 0 = X X · 1 = X
X + X' = 1 X · X' = 0
X + X = X X · X = X
X + 1 = 1 X · 0 = 0
(X')' = X
X + Y = Y + X XY = YX
X + (Y + Z) = (X + Y) + Z X(YZ) = (XY)Z
X(Y + Z) = XY + XZ X + YX = (X + Y) (X + Z)
(X + Y)' = X'Y' (XY)' = X' + Y'
X + XY = X X(X + Y) = X
6. Convert the given expression in canonical SOP form Y = AC + AB + BC
7. Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x(y'z' + yz).
Byapplying De-Morgan's theorem. (Apr 2005)
8. Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC
9. Given the two binary numbers X = 1010100 and Y = 1000011, perform the
subtraction (a) X -Y and (b) Y - X using 1's complements
10. Express the function Y = A + B’C in a) canonical SOP and b) canonical POS form.
(Nov 2006)

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