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Sequential Circuits I VLSI 9th experiment

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Sequential Circuits I VLSI 9th experiment

  1. 1. SR Flip-FlopD Flip-FlopJK Flip-FlopT Flip-Flop
  2. 2. SR FLIP-FLOPmodule sr_flipflop(s,r,clk,q,qbar);input s,r,clk;output q,qbar;reg q,qbar;always@(posedge clk)begin case ({s,r}) 2b00:q=q; 2b01:q=1b0; 2b10:q=1b1; 2b11:q=1bx; endcase qbar=~q; end endmoduleD FLIP-FLOPmodule D_FF (D,clk,reset,Q); input D,clk,reset; output Q; reg Q; always @ (posedge reset or negedge clk)if (reset) Q = 1b0;else Q = D;endmodule
  3. 3. JK FLIP-FLOPmodule JK_FF (J,K,clk,reset,Q); input J,K,clk,reset; output Q; wire w; assign w = (J&~Q)|(~K&Q); D_FF dff1(w,clk,reset,Q);endmodulemodule D_FF (D,clk,reset,Q); input D,clk,reset; output Q; reg Q; always @ (posedge reset or negedge clk)if (reset) Q = 1b0;else Q = D;endmoduleT FLIP-FLOPmodule T_FF (T,clk,reset,Q); input T,clk,reset; output Q; wire w; assign w = T^Q; D_FF dff1(w,clk,reset,Q);endmodulemodule D_FF (D,clk,reset,Q); input D,clk,reset; output Q; reg Q; always @ (posedge reset or negedge clk)if (reset) Q = 1b0;else Q = D;endmodule

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