1. IP Creations and Solutions:
Let’s Work Together
A place for sharing ideas for circuit designers and chip architects
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2. IP Creations and Solutions Group
Purpose:
— This group allows creators of Semiconductor IP to share
techniques and resources.
— Our goal is to help IP creators to connect with IP users.
— Another goal is to create and maintain a quality
standard for IP.
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3. Detailed Description
— If you are a creator of Integrated Circuit functional
blocks, this group is for you.
— If you are a user of IC Design Blocks, this group is for
you.
— Our goal is to bring Circuit Designers and Chip Architects
together to discuss the issues that affect all of us.
— What’s working with the present IP distribution system?
— What isn’t working and why?
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4. 3 Different Business Models:
Model Name Description Developer User Point of Issues:
Point of View View
Front End loaded – User pays developer Great – full payment Not so good; all How do you get
an NRE up front and is received up front. money paid out developer to come
that is the total cost before IP is proven back & fix problems?
paid. to work..
Back End loaded – User pays no NRE, Problem -Developer Good for user. He Keeping track of
but instead pays a spends money up pays out as he gets royalties is painful.
royalty for the use of front, but realizes no income. Still, Total royalty can be
the IP revenue until royalties can be hard quite high for a
customer has sales. to track. successful product.
Tracking royalties
can be difficult
Middle Road – User pays a reduced Covers some of Delays some Both parties have
NRE up front, then a developer’s upfront payment until skin in the game,
royalty based on cost product is shipping. right through EOL
units shipped Developer has
incentive to fix any
problems.
Capped Total Total of NRE & Might limit total Helps limit total cost Limits total cost for
Royalty is capped at revenue from high of IP. Makes costs customer. Makes IP
an agreeable number volume products more predictable. more attractive.
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5. How do we know the IP will
work in the Chip?
— For most people, this is the largest single issue.
— For this reason, due diligence is key.
— Silicon results in the chip technology of interest is
paramount
— Also, this is why most buyers prefer to spread payouts over
time, tied to major milestones.
— Key Milestones
— Initial payment (to get the project moving)
— Delivery of GDS data
— Silicon validation and characterization (yield and datasheet)
— Product Qualification
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6. What if I don’t have silicon
results, is that a deal killer?
— This is a key issue that keeps many small shops out of the IP
business
— However, using this type of IP can reduce the user’s cost
considerably
— How can we “Qualify” an untested IP block?
— We really need some innovation here as the cost of Qualifying an IP
block is above $500K and climbing…
— Some ideas;
— Simulation reviews – What simulations were run across what PVT
corners? What were the vectors? Were all the datasheet parameters
measured?
— Design Rule violations – Are there any design rule violations? Has the
foundry approved these violations?
— Reduced up front payments, Royalties instead
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7. How do I verify the Quality of
an IP block?
— Silicon Characterization Report:
— Does the IP meet it’s Datasheet?
— Across Process variations?
— What is the expected yield of this IP in a chip?
— Testimonials:
— How many chips use this IP?
— In what technologies
— Inputs from other customers
— Reliability Report:
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8. What if the silicon doesn’t
work?
— Prepare for in situ debug, i.e. BIST
— This is the preferred method
— Access through available ports (JTAG, etc.)
— Acceptable, but much slower than BIST and probably not as
complete.
— Write code to access through chip logic
— Slow, tedious, and painful!
— People have spent 6 months debugged problems this way!
— By the time they figure out the problem, the market
window has closed!
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9. What about views (Models)?
— Which views do you need for your tool flow?
— LEF, Verilog, VHDL, Netlist, Symbol
— What else do you need?
— How to protect IP, while delivering necessary views?
— How do you verify these views are accurate?
— Timing issues inside of Verilog or VHDL model
— Completeness of Model? (Are all the input vectors
covered?)
— Timing accuracy for Core Library models…
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10. EDA Tools
— Mainstream EDA vendors
— Traditional path for tools
— High cost – often >$150K per seat + 15% per year
maintenance
— Reasonable support model
— Open Source Tools
— Much cheaper to use
— How functional are they?
— What about maintenance?
— What about support? Turn-around time on bug fixes?
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11. Where do we go from here?
— How do we develop IP more cheaply, while still
maintaining the Quality?
— Is there a better way?
— What might that look like?
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12. About the Author:
— Mr. Chritz has been in the IC Design and Development
business for 30+ years.
— In that time he has designed Memory, Logic, and Analog
Circuitry.
— He has managed teams from 3 to 30 people.
— In his position at ON Semiconductor, he was responsible for
the purchase of many different types of IP (Memory, Logic,
IO, and BIST)
— As well he was responsible for the creation of several
different types of IP (Logic, Memory, BIST)
— He also set the Quality standards for the IP, whether
purchased or created.
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