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Solving the System-Level 
Design Riddle
Before We Start 
q This webinar will be available afterwards at 
www.designworldonline.com & email 
q Q&A at the end of the presentation 
q Hashtag for this webinar: #DWwebinar
Moderator Presenter 
Aimee Kalnoskas 
Design World/EE 
Randy Smith 
Sonics Inc.
Solving the 
System-Level 
Design Riddle 
December 2014
What is the System Design Riddle? 
How do I 
complete my 
design on-time? 
On-budget? 
With no 
errors? 
Then marketing says they need it… 
Sooner 
With higher performance 
In less area 
Sooner? Sorry, I meant early… 
…maybe you can drop a feature?
What’s wrong? Waterfall Methodologies 
• Sequential operations 
o Little parallelism 
• Changes in one phase may result in a reset 
of all downstream steps 
• While design reuse (and use of purchased 
IP) is allowed, it cannot be fully exploited 
• If one feature is causing a delay, it may be 
impossible to move forward with the rest 
of the design until it is resolved 
• In general, the focus is on the process, 
rather than the desired outcome 
It’s easy to see the problems with the waterfall method. 
It assumes that every requirement can be identified 
before any design or coding occurs. 
Specification 
Prototype 
Design 
Simulation 
Verification 
Emulation 
Physical Design 
Software
Reasons for Changing IC Methodology 
Desired new attributes 
• Ability to make reasonable progress with 
an incomplete specification 
• To better solve modern design challenges: 
o Time-to-market 
o Power 
o Security 
• Ability to easily ship “on-time”/early with a 
reduced feature set 
• Improved relationship between 
architectural, logical, physical, and 
software design 
Some drivers for change 
• Consumer products 
o Short release cycle 
o Low power, but still always on 
o Security 
o Design costs 
• IoT 
o Starting design without a complete spec 
• Makimoto’s wave shifts emphasis from 
standardization to customization 
• System companies are in best position to 
assume product risk
Why is Sonics leading this? 
Percent of Reuse Percent of Reuse Avg. Number of IP Blocks 
0% 
0 
20% 
50 
40% 
100 
60% 
150 
80% 
200 
100% 
250 
10% 
30% 
50% 
70% 
90% 
1998 
1999 
2000 
2001 
2002 
2003 
2004 
2005 
2006 
2007 
2008 
2009 
2010 
2011 
2012 
2013 
2014* 
2015* 
2016* 
2017* 
2018* 
Avg, Number of IP Blocks 
Source: Semico Research Corp.
Why is Sonics leading this? 
$120 
$100 
$80 
$60 
$40 
$20 
$0 
$70 
$60 
$50 
$40 
$30 
$20 
$10 
$0 
90nm 65nm 45nm / 40nm 32nm / 28nm 20nm 14nm* 10nm* 
Total M Dollars 
M Dollars Silicon IP Integration Cost Software IP Integration Cost Total IP Integration Cost 
Source: Semico Research Corp.
SoC Architects Drive Both SW & HW 
• Large (and growing) teams 
dependent upon architecture 
• SoC architect responsible for 
many views of architecture 
o Normally disparate 
• Increasing complexity of SW 
and HW results in increased 
costs and delays 
SW Development of HW-independent 
HW 
SW 
Dev. of HW-dependent SW and 
system architecture exploration 
Performance analysis architecture 
validation and 
RTL verification and 
implementation
Worth considering: Agile SW Development 
• The Agile Manifesto was written in 
February of 2001, at a summit of 
seventeen independent-minded 
practitioners of several programming 
methodologies. The participants didn't 
agree about much, but they found 
consensus around four main values: 
o Individuals and interactions over processes and tools 
o Working software over 
comprehensive documentation 
o Customer collaboration over 
contract negotiation 
o Responding to change over 
following a plan 
Requirements 
Architecture & 
Design 
Development 
Test & 
Feedback 
“The Agile movement proposes alternatives to traditional project management. Agile approaches 
are typically used in software development to help businesses respond to unpredictability.”
HW and IC Design Teams Must Evolve 
Yesterday Tomorrow 
Component-Level Aggregation System-Level Architecture 
One-time Usage Platform Reuse 
Hierarchical Requirements and Stepwise 
Design Management 
Concurrent Engineering and 
Agile IC Methodology 
Dedicated Resources Shared Resources
What an Agile IC Methodology Might Look Like 
Specification 
Prototype 
Design 
Simulation 
Verification 
Emulation 
Physical Design 
Waterfall 
Time
What an Agile IC Methodology Might Look Like 
Specification 
Prototype 
Design 
Simulation 
Verification 
Emulation 
Physical Design 
Agile IC 
Methodology 
Time 
Change the slope! The 
more vertical the 
better!
How Sonics helps 
• Sonics’ on-chip networks help leading SoC designers solve some of the most difficult 
challenges in SoC design 
IP Integration 
High Frequency 
Memory Throughput 
Physical Design 
Power Management 
Security 
Time-to-market 
• Sonics System IP: On-chip Networks, Memory Subsystem, Power Partitioning & 
Management, Performance Monitor & Debug, Security Firewalls 
Development costs 
13 3 MHz 106 MHz 53 MHz 
Cortex- 
A15 
Cluster 
Cortex- 
A7 
Cluster 
Mali- 
T658 
Cluster 
CCI-40 
267 MHz 13 MHz 267 MHz 267 MHz 
Video 
Engine 
Video 
Encode 
Cam 
1 
Cam 
2 
DMA 
Display 
Ctrl. 
USB 
1 
USB 
2 
On-die 
SRAM 
DRAM 
Ch. 1 
DRAM 
Ch. 2 
USB 
3 
USB 
OTG 
E-net 
Audio 
HDMI 
32 64 32 64 
SATA UFS 
SD/ 
CF/ 
MMC 
J 
3x1 
PCIe HSI 
On-die 
Peripherals ROM 
A 
2x2 
G 
4x1 
F 
4x1 
E 
4x1 
H 
5x2 
C 
2x3 
Security 
Engine 
M M M M 
S M M M M M M M M 
S 
64 
M M M M M M M 
S S 
B 
2x3 
S S 
M S 
128 128 
128 
32 
T 
128 
T 
128 
T 
64 
T 
I T I I I I 
I 
I 
I 
I 
I 
I 
I 
I 
T I I I I I I I 
64 
64 
64 
64 
53 MHz 
32 32 32 32 64 64 64 64 
267 MHz 
64 
64 
64 
20 MHz 20 MHz 40 MHz 13 MHz 13 MHz 13 MHz 13 MHz 
267 MHz 13 MHz 267 MHz 13 MHz 13 MHz 13 MHz 13 MHz 
13 MHz 13 MHz 53 MHz 53 MHz 53 MHz 
D R3 
213 
D R3 
213 
IP 
Control 
S 
32 
T 
13 MHz 
M 
128 
I 
D 
1x3 
I 
4x1 
T 
Power Domain 
Boundary 
SonicsGN 
Request 
Network
Sonics – The NoC Leader for 18 Years 
• Sonics enables designers to integrate any 
IP from anywhere, anytime 
o Easy IP re-use 
o Connecting third party IP/subsystems 
• Total System IP approach: 
o Intelligent memory scheduling 
o Optimal power-aware designs 
o Data flow services: QoS, Security firewalls 
o Software drivers 
• Commanding presence in digital 
entertainment, mobile and wireless 
o 200+ SoC tape-outs 
• Results: 2.5B+ units shipped 
o 138+ patent properties 
o Improved TTM and quality
Does Sonics Solve the 
Riddle? 
• No, not entirely 
o Using Sonics and other high-quality IP will aid greatly 
o But there are limitations that good IP alone doesn’t 
solve 
• Your design methodology is probably wrong, 
though it may be the best you can do today
Short term actions 
How you can help 
• Join the LinkedIn group 
• Participate in the 
conversation 
• Invite others to get involved 
too 
Sonics’ Plan 
• Get the discussion started 
• Create the communications 
links 
• Gather the interested parties 
Step 1: Join the “Agile IC Methodology” group on LinkedIn 
Step 2: Join the conversation – participate!
Agile IC Methodology 
Progress 
• Group went live on October 1, 2014… 
o +280 members joined 
o +50 different companies represented in the group 
o 20 discussions threads 
• Don’t miss out! Join Agile IC Methodology group today!
Questions? 
Aimee Kalnoskas 
Design World/EE 
akalnoskas@wtwhmedia.com 
Randy Smith 
Sonics Inc 
randy@sonicsinc.com
Thank You 
q This webinar will be available at 
designworldonline.com & email 
q Tweet with hashtag #DWwebinar 
q Connect with Design World 
q Discuss this on EngineeringExchange.com

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We Got a Warning Letter – Now What? How to Keep Calm in a Compliance Storm
We Got a Warning Letter – Now What? How to Keep Calm in a Compliance StormWe Got a Warning Letter – Now What? How to Keep Calm in a Compliance Storm
We Got a Warning Letter – Now What? How to Keep Calm in a Compliance Storm
 

2014 12-10 aimee

  • 1. Solving the System-Level Design Riddle
  • 2. Before We Start q This webinar will be available afterwards at www.designworldonline.com & email q Q&A at the end of the presentation q Hashtag for this webinar: #DWwebinar
  • 3. Moderator Presenter Aimee Kalnoskas Design World/EE Randy Smith Sonics Inc.
  • 4. Solving the System-Level Design Riddle December 2014
  • 5. What is the System Design Riddle? How do I complete my design on-time? On-budget? With no errors? Then marketing says they need it… Sooner With higher performance In less area Sooner? Sorry, I meant early… …maybe you can drop a feature?
  • 6. What’s wrong? Waterfall Methodologies • Sequential operations o Little parallelism • Changes in one phase may result in a reset of all downstream steps • While design reuse (and use of purchased IP) is allowed, it cannot be fully exploited • If one feature is causing a delay, it may be impossible to move forward with the rest of the design until it is resolved • In general, the focus is on the process, rather than the desired outcome It’s easy to see the problems with the waterfall method. It assumes that every requirement can be identified before any design or coding occurs. Specification Prototype Design Simulation Verification Emulation Physical Design Software
  • 7. Reasons for Changing IC Methodology Desired new attributes • Ability to make reasonable progress with an incomplete specification • To better solve modern design challenges: o Time-to-market o Power o Security • Ability to easily ship “on-time”/early with a reduced feature set • Improved relationship between architectural, logical, physical, and software design Some drivers for change • Consumer products o Short release cycle o Low power, but still always on o Security o Design costs • IoT o Starting design without a complete spec • Makimoto’s wave shifts emphasis from standardization to customization • System companies are in best position to assume product risk
  • 8. Why is Sonics leading this? Percent of Reuse Percent of Reuse Avg. Number of IP Blocks 0% 0 20% 50 40% 100 60% 150 80% 200 100% 250 10% 30% 50% 70% 90% 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014* 2015* 2016* 2017* 2018* Avg, Number of IP Blocks Source: Semico Research Corp.
  • 9. Why is Sonics leading this? $120 $100 $80 $60 $40 $20 $0 $70 $60 $50 $40 $30 $20 $10 $0 90nm 65nm 45nm / 40nm 32nm / 28nm 20nm 14nm* 10nm* Total M Dollars M Dollars Silicon IP Integration Cost Software IP Integration Cost Total IP Integration Cost Source: Semico Research Corp.
  • 10. SoC Architects Drive Both SW & HW • Large (and growing) teams dependent upon architecture • SoC architect responsible for many views of architecture o Normally disparate • Increasing complexity of SW and HW results in increased costs and delays SW Development of HW-independent HW SW Dev. of HW-dependent SW and system architecture exploration Performance analysis architecture validation and RTL verification and implementation
  • 11. Worth considering: Agile SW Development • The Agile Manifesto was written in February of 2001, at a summit of seventeen independent-minded practitioners of several programming methodologies. The participants didn't agree about much, but they found consensus around four main values: o Individuals and interactions over processes and tools o Working software over comprehensive documentation o Customer collaboration over contract negotiation o Responding to change over following a plan Requirements Architecture & Design Development Test & Feedback “The Agile movement proposes alternatives to traditional project management. Agile approaches are typically used in software development to help businesses respond to unpredictability.”
  • 12. HW and IC Design Teams Must Evolve Yesterday Tomorrow Component-Level Aggregation System-Level Architecture One-time Usage Platform Reuse Hierarchical Requirements and Stepwise Design Management Concurrent Engineering and Agile IC Methodology Dedicated Resources Shared Resources
  • 13. What an Agile IC Methodology Might Look Like Specification Prototype Design Simulation Verification Emulation Physical Design Waterfall Time
  • 14. What an Agile IC Methodology Might Look Like Specification Prototype Design Simulation Verification Emulation Physical Design Agile IC Methodology Time Change the slope! The more vertical the better!
  • 15. How Sonics helps • Sonics’ on-chip networks help leading SoC designers solve some of the most difficult challenges in SoC design IP Integration High Frequency Memory Throughput Physical Design Power Management Security Time-to-market • Sonics System IP: On-chip Networks, Memory Subsystem, Power Partitioning & Management, Performance Monitor & Debug, Security Firewalls Development costs 13 3 MHz 106 MHz 53 MHz Cortex- A15 Cluster Cortex- A7 Cluster Mali- T658 Cluster CCI-40 267 MHz 13 MHz 267 MHz 267 MHz Video Engine Video Encode Cam 1 Cam 2 DMA Display Ctrl. USB 1 USB 2 On-die SRAM DRAM Ch. 1 DRAM Ch. 2 USB 3 USB OTG E-net Audio HDMI 32 64 32 64 SATA UFS SD/ CF/ MMC J 3x1 PCIe HSI On-die Peripherals ROM A 2x2 G 4x1 F 4x1 E 4x1 H 5x2 C 2x3 Security Engine M M M M S M M M M M M M M S 64 M M M M M M M S S B 2x3 S S M S 128 128 128 32 T 128 T 128 T 64 T I T I I I I I I I I I I I I T I I I I I I I 64 64 64 64 53 MHz 32 32 32 32 64 64 64 64 267 MHz 64 64 64 20 MHz 20 MHz 40 MHz 13 MHz 13 MHz 13 MHz 13 MHz 267 MHz 13 MHz 267 MHz 13 MHz 13 MHz 13 MHz 13 MHz 13 MHz 13 MHz 53 MHz 53 MHz 53 MHz D R3 213 D R3 213 IP Control S 32 T 13 MHz M 128 I D 1x3 I 4x1 T Power Domain Boundary SonicsGN Request Network
  • 16. Sonics – The NoC Leader for 18 Years • Sonics enables designers to integrate any IP from anywhere, anytime o Easy IP re-use o Connecting third party IP/subsystems • Total System IP approach: o Intelligent memory scheduling o Optimal power-aware designs o Data flow services: QoS, Security firewalls o Software drivers • Commanding presence in digital entertainment, mobile and wireless o 200+ SoC tape-outs • Results: 2.5B+ units shipped o 138+ patent properties o Improved TTM and quality
  • 17. Does Sonics Solve the Riddle? • No, not entirely o Using Sonics and other high-quality IP will aid greatly o But there are limitations that good IP alone doesn’t solve • Your design methodology is probably wrong, though it may be the best you can do today
  • 18. Short term actions How you can help • Join the LinkedIn group • Participate in the conversation • Invite others to get involved too Sonics’ Plan • Get the discussion started • Create the communications links • Gather the interested parties Step 1: Join the “Agile IC Methodology” group on LinkedIn Step 2: Join the conversation – participate!
  • 19. Agile IC Methodology Progress • Group went live on October 1, 2014… o +280 members joined o +50 different companies represented in the group o 20 discussions threads • Don’t miss out! Join Agile IC Methodology group today!
  • 20. Questions? Aimee Kalnoskas Design World/EE akalnoskas@wtwhmedia.com Randy Smith Sonics Inc randy@sonicsinc.com
  • 21. Thank You q This webinar will be available at designworldonline.com & email q Tweet with hashtag #DWwebinar q Connect with Design World q Discuss this on EngineeringExchange.com