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TOP SIDE ASSEMBLY
LAYER BOARDS) AS APPLICABLE.
062-0031 (DOUBLE-SIDED BOARDS) OR 062-0073 (MULTI-
TO STANDARDS AS DEFINED IN APPLE SPECIFICATION
ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM
NOTES:
ORIG DIV
APPLE
THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED
HURLEY
DESIGNER
01/08/13
DATE SCALE
1:1
(II) NOT TO REPRODUCE OR COPY IT
(III) NOT TO REVEAL OR PUBLISH IT
THE POSSESSOR AGREES TO THE FOLLOWING
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
PROPRIETARY PROPERTY OF APPLE
THE INFORMATION CONTAINED HEREIN IS THE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
TITLE
820-4124-A
X200 MLB (C1)
PCBF,
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
IV ALL RIGHTS RESERVED
II NOT TO REPRODUCE OR COPY IT
3
B
7
BRANCH
DRAWING NUMBER SIZE
D
SHEET
R
DATE
D
A
C
PAGE
A
C
3456
D
B
8 7 6 5 4 2 1
12
APPD
CK
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
DRAWING TITLE
DESCRIPTION OF REVISIONREV ECN
REVISION
PROPRIETARY PROPERTY OF APPLE INC.
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
QTY DESCRIPTIONPART#
DRAWING
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
SCH AND BOARD PART NUMBERS
MLB-C1
X200 0002535199A
051-0886
A.0.0
2014-01-13PRODUCTION RELEASED
1 OF 121
1 OF 54
SCH,MLB-C1,X200
LAST_MODIFIED=Tue Oct 29 15:52:27 2013
J85 MLB_C12/05/20122218 VIDEO: EDP SUPPORT & CONN
BUTTON: CONN N/A N/A2117
AUDIO: CS35L19A AMPS KAVITHA 01/18/20122016
KAVITHA 01/18/20121915 AUDIO: L81 CODEC
AUDIO: HP FLEX CONN N/A1814
TOUCH: SUPPORT CKT & CONN N/A 06/21/20101713
IO: TRISTAR N/A N/A1311
SOC: MISC & ALIASES N/A 04/11/20111210
SOC: VDD, SRAM, CPU, GPU PWRS N/A 04/18/2011119
SOC: SRAM, IO PWRS N/A 04/18/2011108
SOC: DP,MIPI MLB 05/04/201297
SOC: NAND N/A 04/18/201186
N/A 05/05/201175
SOC: MAIN N/A 04/18/201164
BOM TABLES J72_MLB_C11/26/201243
BLOCK DIAGRAM: SYSTEM J85_MLB_B04/02/201322
11/26/201212154 POWER: ALIASES J72_MLB_C
J85 MLB_C12/03/129352
J72_MLB_C11/26/20129051 SEP: EEPROM & SOC DEBUG
J85 MLB_C11/26/201285 POWER: PP1V8_SW
J72_MLB_C11/26/20128449 PMU: ANYA PAGE 4
J72_MLB_C11/26/20128348 PMU: ANYA PAGE 3
J85 MLB_C12/03/20128247 PMU: ANYA PAGE 2
J72_MLB_C11/26/20128146 PMU: ANYA PAGE 1
N/A N/A7545 POWER: BATTERY CONNECTOR
WIFI_DEV05/20/20135844 WIFI/BT: MODULE
N/A 04/18/20115743 IO: FILTERS & HOTBAR CONN
RADIO_MLB_8710/29/20134942 CELL: ANTENNA FEEDS
RADIO_MLB_8710/29/20134841 CELL: GPS
RADIO_MLB_8710/29/20134740 CELL: RX DIVERSITY
RADIO_MLB_8710/29/20134639 CELL: ASM AND HB LTE FRONT-END
RADIO_MLB_8710/29/20134538 CELL: PA DCDC CONVERTER
RADIO_MLB_8710/29/20134437 CELL: 2G PA
RADIO_MLB_8710/29/20134336 CELL: BAND 5/8 PAD
RADIO_MLB_8710/29/20134235 CELL: BAND 7/20 PAD
RADIO_MLB_8710/29/20134134 CELL: BAND 2/3 PAD
RADIO_MLB_8710/29/20134033 CELL: PENTABAND PA
RADIO_MLB_8710/29/20133932 CELL: RF TRANSCEIVER (3 OF 4)
RADIO_MLB_8710/29/20133831 CELL: RX MATCHING
RADIO_MLB_8710/29/20133730 CELL: RF TRANSCEIVER (2 OF 2)
RADIO_MLB_8710/29/20133629 CELL: RF TRANSCEIVER (1 0F 2)
RADIO_MLB_8710/29/20133528 CELL: BASEBAND (2 OF 2)
RADIO_MLB_8710/29/20133427 CELL: BASEBAND (1 OF 2)
RADIO_MLB_8710/29/20133326 CELL: BASEBAND PMU (2 OF 2)
RADIO_MLB_8710/29/20133225 CELL: BASEBAND PMU (1 0F 2)
RADIO_MLB_8710/29/20133024 CELL:AP INTERFACE & DEBUG CONNECTORS
N/A N/A2923 CAMERA: REAR CONN & FILTERS
J85 MLB_C12/05/122822 SENSOR: PROX
CONTENTS DATESYNC MASTERPDF CSA
N/A N/A2721 SENSOR: ACCEL, COMPASS, GYRO
SYNC MASTERCONTENTS DATECSAPDF
TABLE OF CONTENTS N/A N/A11
PCB11820-4124 PCBF,MLB-C1,X200
1 SCH1051-0886 SCH,MLB-C1,X200
J72_MLB_C11/26/20129453 TEST: EE TP/PPCAMERA: FF-ALS CONN & FILTERS J85 MLB_C12/03/20122620
SENSOR: OSCAR J72_MLB_C11/26/20122419
NAND STORAGE 05/04/20121412
TEST: TP/HOLES/FIDUCIALS
50
03/31/2011
MLB
SOC: I/OS
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
HSIC2
HSIC1
I2C2
I2S1
ALS
I2C3
CSA 27CSA 27CSA 27
BATTERY
I2S3
I2S4
CSA 13
SPI2
I2S2
CSA 14
CSA 28
1-3
CSA 17
HALL EFF
OSCAR
I2C0
CSA 24
FMI0
COMPASS
SPI1
I2C0
CUMULUS
CSA 81-84
FRONT CAMERA
UART3
DISPLAY/
BUTTON FLEX
AMP
LEFT
SPEAKER
USB2.0
WIFI/BT ANT
WIFI/BT ANT
CSA 58
TRISTAR
REAR CAMERA
BT_I2S
MIPI1C
MIPI0C
ISP1_I2C
ISP0_I2C
UART2
UART6
SPI
XSP
HP
FMI1
NAND FLASH
UART4
DWI
UART5
EDP
CSA 75
I2C1
PMU
BACKLIGHT
TOUCH PANEL
SPI BUS
GYROACCELEROMETER
HOME BUTTON
PROX SENSOR
ANYA
PRIMARY CELLULAR ANT
NOT ON
CELLULAR/
JTAG
GRAPE
GPS
DIVERSITY CELLULAR ANT
HSIC1
WIFI-ONLY CONFIG
WIFI/BTUART1
GPS ANT
SIM CARD
USART
ALCATRAZ
MBUS
CSA 31-46
MIMO
MIC1 MIC2
CSA 19
L81
CODEC
AUDIO
RIGHT
USB
ASPI2S0
CSA 20
CSA 20
UART0
AMP
SPEAKER
CUMULUS
SYNC_DATE=04/02/2013SYNC_MASTER=J85_MLB_B
BLOCK DIAGRAM: SYSTEM
051-0886
A.0.0
2 OF 121
2 OF 54
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_5_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
PART NUMBER
ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
PART NUMBER
ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_5_ITEM
WIFI 4.3UF CAP
U2200
338S1233 ST MICRO - DISQUAL’ED
PMU
338S1191 OLD ACCEL - ST MICRO
338S1114 OLD ACCEL - ST MICRO
338S1158 OLD GYRO - ST MICRO
OLD INVENSENSE P/N 338S1200 (3/22/13)
OLDER INVENSENSE P/N 338S1135
GYRO
MECHANICAL PARTS
Page Notes
ACCEL
Power aliases required by this page:
128GB_PROD
ANDGATE_TI
FERRITE_TY
JTAG_DAP
DEVELOPMENT_JTAG_TAP
COMMON
BOM OPTIONS
64GB_PROD
ALTERNATE
MLB (WDOG TO PMU)
BOM options provided by this page:
32GB_PROD
16GB_PROD
FERRITE_TDK
Signal aliases required by this page:
(NONE)
WIFI BOM OPTIONS
SOC
(NONE)
FLASH CONFIGURATIONS
BARCODE LABEL/EEEE CODES
NOTE: FOLLOWING J72, U2200 USES 353S3672 FOOTPRINT (353S4272 HAS SMALLER PADS DUE TO NEW DFM RULES)
U5800339S0213339S0223 RDAR #13988471C1009,C1015,...138S0657138S0702
132S0288
1 CRITICAL338S1163 IC,ACCEL,3-AXIS,DIG,BMA282,LGA14 U2700
CRITICALU81001343S0656 IC,PMU,ANYA,D2089A1,OTPXX,FCCSP342
1 U1400TOS,19NM,PPN1.5,C,12DP,64GB 96GB335S0929
SYNC_DATE=11/26/2012SYNC_MASTER=J72_MLB_C
BOM TABLES
FENCE,RADIO,MLB,C BRD,X221806-7613 1 PD_CAN_RADIO CRITICAL
1 CRITICALPD_FENCE_MLB806-6207 FENCE,TALL,MLB,X221
BASIC COMMON,ALTERNATE
C2726CAP 0.1UF 16V 0201 CRITICAL GYRO_INVENSENSE1
C2726CAP 0.01UF 25V 0201132S0391 CRITICAL GYRO_STMICRO1
U27201 GYRO_INVENSENSECRITICAL338S1218
TOS,19NM,PPN1.5,C,QDP,32GB335S0922 32GB1 U1400
1 U1400 64GB335S0923 TOS,19NM,PPN1.5,C,ODP,64GB
CRITICAL EEEE_X200C_BETTER_IVSFNJFEEEE FOR 639-5389 (X200C1 BETTER IVS)1825-7639
CRITICAL GYRO_STMICRO338S1192 1 GYRO, ST MICRO U2720
U0652H6P + 1GB ELPIDA339S0207 1 CRITICAL
HYNIX DDRU0652339S0207339S0208
335S0923 HYNIX 20NM PPN1.5 64GB64GB U1400335S0932
335S0931 335S0922 HYNIX 20NM PPN1.5 32GB32GB U1400
U140016GB HYNIX 20NM PPN1.5 16GB335S0921335S0930
U14001 TOS,19NM,PPN1.5,C,16DP,128GB 128GB335S0924
EEEE FOR 639-5391 (X200C1 BEST+ IVS) EEEE_X200C_BEST+_IVSFNJ7 CRITICAL1825-7639
EEEE_X200C_ULTIMATEFNJ6EEEE FOR 639-5387 (X200C1 ULTIMATE)825-7639 1 CRITICAL
EEEE_X200C_BESTFNJ9EEEE FOR 639-5385 (X200C1 BEST)825-7639 1 CRITICAL
EEEE_X200C_BETTERFNJ5EEEE FOR 639-5394 (X200C1 BETTER) CRITICAL825-7639 1
EEEE_X200C_GOODFNJDEEEE FOR 639-5393 (X200C1 GOOD)1 CRITICAL825-7639
EEEE_X200C_GOOD_IVSFNJ8EEEE FOR 639-5388 (X200C1 GOOD IVS)825-7639 CRITICAL1
EEEE_X200C_ULTIMATE_IVSFNJGEEEE FOR 639-5392 (X200C1 ULTIMATE IVS) CRITICAL1825-7639
EEEE_X200C_BEST_IVSFNJCEEEE FOR 639-5390 (X200C1 BEST IVS) CRITICAL1825-7639
EEEE_X200C_BEST+FNJHEEEE FOR 639-5386 (X200C1 BEST+)825-7639 1 CRITICAL
U14001 16GB335S0921 TOS,19NM,PPN1.5,C,DDP,16GB
U2200IC,SLG5AP1423V,PWR SW,GREENFET3,4A,TDFN8353S4272 1
GYRO, INVENSENSE
051-0886
A.0.0
4 OF 121
3 OF 54
SYM 1 OF 13
HSIC2_STB
USB_VSSA0
USB_ANALOGTEST
TESTMODE
USB_DP
USB_DM
WDOG
TST_CLKOUT
FAST_SCAN_CLK
USB_REXT
USB_VBUS
USB_ID
JTAG_SEL
JTAG_TRST*
JTAG_TDO
JTAG_TDI
HSIC_VSS120
JTAG_TCK
JTAG_TMS
JTAG_TRTCK
XI0
XO0
HSIC0_DATA
HSIC0_STB
HSIC2_DATA
HSIC_VSS121
HSIC_VSS122
RESET*
CFSB
HOLD_RESET
FUSE1_FSRC
HSIC1_DATA
HSIC1_STB
USB_VDD330
USB_DVDD
VDD_ANA_PLL_CCC
ANALOGMUXOUT
HSIC_VDD120
HSIC_VDD122
HSIC_VDD121
VDD_ANA_PLL
IN
BI
BI
OUT
IN
IN
IN
BI
BI
BI
BI
IN
IN
IN
IN
TP
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
H6P: JTAG, USB, PLL, HSIC, XTAL
USBHS ON/OFF TOLERANCE 5V/1.98V
NOTE: NEW USB_REXT
VALUE FOR H6 = 200 OHM
TBD: XTAL PASSIVES WILL CHANGE ON H6P WITH FIRST HW BUILD
OLD (H5) VALUE: 44.2 OHM
(REPLACE WITH XW LATER?)
NOTE: CANDIDATE FOR COST-SAVINGS
(25MA)
(25MA)
(5.4MA)
(6X1MA)
(1MA)
VDDIO18_GRP4
VDDIO18_GRP1
(3X13MA)
HSIC_VDD120
HSIC_VDD122
HSIC_VDD121
VDDIO18_GRP3
1.8V TOLERANT
C0630
20%
0.1UF
01005
X5R-CERM
6.3V
R0642
MF
1%
01005
200
1/32W
R0622
010050.00
C0608
X5R
10%
0.01UF
6.3V
01005
C0648
10%
X5R
6.3V
0.01UF
0100501005
0.1UF
20%
C0651
6.3V
X5R-CERM
C0690
0.22UF
6.3V
20%
X5R
0201
U0652
H6P
FCMSP
POP-1GB-DDR
OMIT
C0607
12PF
16V
CERM
01005
5%
100K
1%
R0617
01005
MF
1/32W
C0618
10%
6.3V
X5R-CERM
01005
1000PF
R0651
68.1K
1/32W
MF
1%
01005
46
11 52
11 52
10
81011244852
1052
C0613
5%
16V
CERM
12PF
01005
1052
100K
R0647
1%
01005
MF
1/32W
R0646
1/32W
MF
01005
1%
100K
1/32W
MF
01005
1%
100K
R0645
4453
4453
242753
242753
41152
41152
Y06021.60X1.20MM-SM
24.000MHZ-30PPM-9.5PF-60OHM
10
452
TP-P55
TP0600
10
10 52
C0691
0.22UF
6.3V
20%
X5R
0201
R0655
01005
1%
1/32W
MF
1.00M
MF
1/32W
1%
01005
R0640
1.33K
C0627
6.3V
10%
01005
0.01UF
X5R
SOC: MAIN
SYNC_DATE=04/18/2011SYNC_MASTER=N/A
=PP1V8_SOC
=PP1V0_USB_SOC
XTAL_SOC_24M_I
XTAL_SOC_24M_O
=PP3V3_USB_SOC
PP1V8_PLL_SOC_F
=PP1V2_HSIC_SOC
RESET_SOC_L
SOC_24M_O
USB_VBUS_DETECT
USB_REXT
=PP1V8_PLL_SOC
NC_USB_ANALOGTEST
SOC_TESTMODE
USB_SOC_P
USB_SOC_N
WDOG_SOC
SOC_TEST_CLKOUT
SOC_FAST_SCAN_CLK
USB_VBUS_DETECT_R
NC_USB_ID
TP_JTAG_SOC_TDO
NC_JTAG_SOC_TRTCK
NC_HSIC0_DATA
NC_HSIC0_STB
NC_ANALOGMUXOUT
JTAG_SOC_SEL
JTAG_SOC_TMS
JTAG_SOC_TDI
JTAG_SOC_TCK
SOC_HOLD_RESET
JTAG_SOC_TCK
JTAG_SOC_TMS
JTAG_SOC_TDI
=PP1V8_SOC
MAKE_BASE=TRUE
HSIC2_WLAN_STB
HSIC2_BB_STB
HSIC2_BB_DATA
HSIC1_WLAN_STB
MAKE_BASE=TRUE
HSIC1_BB_DATA
JTAG_SOC_TRST_L
HSIC1_BB_STB
MAKE_BASE=TRUE
HSIC2_WLAN_DATA
MAKE_BASE=TRUE
HSIC1_WLAN_DATA
6 OF 121
A.0.0
4 OF 54
051-0886
2
1
1
2
1 2
2
1
2
1
2
1
2
1
AM34
H23
D26
AB3
B29
A29
AD4
AC3
AD3
E23
D23
E24
D28
E28
E27
F27
H20
C28
F28
D27
F25
E25
A26
B26
AM33
H21
AM32
F29
E29
D29
H16
A27
B27
F23
F24
AE20
E26
G22
AM31
G23
U16
1 2
1
2
2
1
1 2
1
2
1
2
1
2
42
13
2
1
1
2
1 2
2
1
457101854
54
54
52
54
54
52
41152
41152
452
457101854
OUT
OUT
IN
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
IN
IN
IN
IN
IN
IN
IN
BI
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
IN
OUT
OUT
IN
IN
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
OUT
SYM 2 OF 13
GPIO4
UART6_TXD
UART6_RXD
UART5_RTXD
UART4_RTSN
UART4_CTSN
UART3_RXD
UART3_RTSN
UART3_CTSN
UART2_TXD
UART2_RXD
UART2_RTSN
UART2_CTSN
UART1_TXD
UART1_RXD
UART1_RTSN
UART1_CTSN
UART0_TXD
UART0_RXD
TMR32_PWM2
TMR32_PWM1
TMR32_PWM0
GPIO8
GPIO7
GPIO6
GPIO5
GPIO38
GPIO37
GPIO36
GPIO35
GPIO34
GPIO33
GPIO32
GPIO31
GPIO3
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO2
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO1
GPIO0
UART4_RXDGPIO29
GPIO30
UART3_TXD
UART4_TXD
GPIO10
GPIO9
SPI3_SSIN
SPI3_MOSI
SPI3_MISO
SPI2_SSIN
SPI2_SCLK
SPI2_MOSI
SPI2_MISO
SPI1_SSIN
SPI1_SCLK
SPI1_MOSI
SPI1_MISO
SPI0_SSIN
SPI0_SCLK
SPI0_MOSI
SPI0_MISO
SOCHOT1
SOCHOT0
SIO_7816UART1_SCL
SIO_7816UART1_RST
SIO_7816UART0_SCL
SEP_7816UART1_SCL
SEP_7816UART0_RST
I2S4_MCK
I2S4_LRCK
I2S4_DOUT
I2S4_DIN
I2S4_BCLK
I2S3_MCK
I2S3_LRCK
I2S3_DOUT
I2S3_DIN
I2S3_BCLK
I2S2_MCK
I2S2_LRCK
I2S2_DOUT
I2S2_DIN
I2S2_BCLK
I2S1_MCK
I2S1_LRCK
I2S1_DOUT
I2S1_DIN
I2S1_BCLK
I2S0_MCK
I2S0_LRCK
I2S0_DOUT
I2S0_DIN
I2S0_BCLK
I2C3_SDA
I2C3_SCL
I2C2_SDA
I2C2_SCL
I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL
DWI_DO
DWI_DI
DWI_CLK
SIO_7816UART0_SDA
SIO_7816UART0_RST
SEP_7816UART1_SDA
SEP_7816UART1_RST
SEP_7816UART0_SCL
SEP_7816UART0_SDA
SIO_7816UART1_SDA
SPI3_SCLK
DISP_VSYNC
SYM 3 OF 13
OUT
OUT
BI
BI
BI
BI
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
OUT
IN
BI
OUT
IN
OUTOUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
VDDIO18_GRP2VDDIO18_GRP2
(SCREEN ROTATION LOCK)
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP2
VDDIO18_GRP1
SOC I/OS
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP1
VDDIO18_GRP1
PMU
TRISTAR
SPK AMPS
PROX
ALS
R0700
1/32W
5%
2.2K
MF
01005
MF
01005
2.2K
5%
1/32W
R0701
MF
01005
1.8K
1/32W
5%
R0702
MF
01005
1.8K
1/32W
5%
R0703
01005
MF
2.2K
5%
1/32W
R0705R0704
5%
1/32W
2.2K
MF
01005
13
1352
1352
1352
220K
1/32W
MF
5%
01005
R0771
220K
5%
1/32W
MF
01005
R0770
R0765
5%
MF
1/32W
220K
01005
1/32W
1%
MF
01005
R0738
100K
1/32W
100K
1%
MF
01005
R0737
100K
1/32W
1%
01005
MF
R0736R0735
01005
1%
100K
MF
1/32W
51348
51748
22
242652
10
10
11 24 28 52
11 24 28 52
15
15
15
15
1553
1553
15
15
10
10
10
10
48 53
48 52
1%
MF
01005
33.2
1/32W
R0720
1553
10
10
10
17
17
51748
10
45 48
1653
1653
1653
1653
1553
1553
1553
15
1%
1/32W
33.2
01005
MF
R0721
1653
548
48
10
1352
1352
44
44
44 53
44 53
11 52
11 52
19 48
19
19 53
19 53
4453
24 28
24 28
10
19
13 52
242752
242752
242752
242752
242752
11 52
11 52
FCMSP
H6P
POP-1GB-DDR
U0652
OMIT
CRITICAL
OMIT
H6P
FCMSP
POP-1GB-DDR
CRITICAL
U0652
13
5 51
5 51
5 16 52
5 11 48 52
5 19
5 16 52
5 19
5 11 48 52
5 48
R0751
1/32W
5%
2.2K
MF
01005
R0750
01005
MF
2.2K
1/32W
5%
R0753
NOSTUFF
1/32W
5%
2.2K
MF
01005
R0752
NOSTUFF
01005
MF
2.2K
1/32W
5%
100K
5%
MF
1/32W
01005
R0754
1/32W
100K
01005
MF
5%
R0755
44 53
44 53
10
10
10
1552
2852
20
2428
552
19
242652
18
1148
16
28
28
516
R0739
1/32W
MF
100K
1%
01005
28
5 20 22
5 20 22
16
5 16 5214
14
SYNC_DATE=05/05/2011SYNC_MASTER=N/A
SOC: I/OS
GPIO_SOC2BEACON_EN
GPIO_SOC2AJ_HS3_SHUNT_EN
DISPLAY_SYNC
GPIO_SOC2AJ_HS4_SHUNT_EN
=PP1V8_SOC
NC_SPI1_NAVAJO_MISO
NC_SPI1_NAVAJO_MOSI
NC_SPI1_NAVAJO_SCLK
NC_GPIO_NAVAJO2SOC_INT
GPIO_SPKAMP_RST_L
GPIO_SOC2PMU_KEEPACT
HSIC1_SOC2WLAN_HOST_RDY
HSIC2_BB2SOC_REMOTE_WAKE
HSIC2_BB2SOC_DEVICE_RDY
HSIC2_SOC2BB_HOST_RDY
SOCHOT1_L
SOCHOT0_L
I2C2_SCL_1V8
GPIO_BTN_VOL_UP_L
HSIC1_SOC2WLAN_HOST_RDY
GPIO_FORCE_DFU
GPIO_SPKAMP_KEEPALIVE
HSIC1_WLAN2SOC_REMOTE_WAKE
NC_SEP_7816UART1_SDA
DWI_AP_DO
PMU_GPIO_OSCAR2PMU_HOST_WAKE
UART3_SOC2BB_TX
UART2_WLAN2SOC_TX
UART2_SOC2WLAN_TX
UART1_SOC2BT_TX
UART1_BT2SOC_TX
UART1_BT2SOC_RTS_L
UART1_SOC2BT_RTS_L
UART0_SOC_RXD
GPIO_OSCAR_RESET_L
GPIO_BTN_VOL_DOWN_L
GPIO_BTN_ONOFF_L
UART0_SOC_TXD
UART3_BB2SOC_TX
UART3_SOC2BB_RTS_L
UART3_BB2SOC_RTS_L
SOCHOT1_L
=PP1V8_S2R_MISC
GPIO_BTN_SRL_L
I2C1_SOC2OSCAR_SWDIO_1V8
I2C1_SOC2OSCAR_SWDCLK_1V8
=PP1V8_SOCGPIO_BTN_HOME_L
GPIO_BTN_ONOFF_L
=PP1V8_S2R_MISC
=PP1V8_ALWAYS
NC_SEP_7816UART0_RST
SEP_I2C0_SDA
HSIC1_WLAN2SOC_DEVICE_RDY
NC_SEP_7816UART1_SCL
I2C0_SCL_1V8
I2C1_SOC2OSCAR_SWDIO_1V8
I2C0_SDA_1V8
I2S2_CODEC_XSP_LRCK
I2S2_CODEC_XSP_DIN
I2S1_SPKAMP_DOUT
I2S1_SPKAMP_MCK
I2S0_CODEC_ASP_LRCK
SPI2_CODEC_CS_L
SPI2_CODEC_SCLK
SPI2_CODEC_MOSI
SPI2_CODEC_MISO
SPI1_GRAPE_CS_L
SPI1_GRAPE_SCLK
SPI1_GRAPE_MOSI
NC_SPI0_SSIN
GPIO_BOARD_ID1
BB_JTAG_TCK
BB_JTAG_TDI
BB_JTAG_TMS
I2S3_SOC2BT_DATA
I2S3_BT2SOC_DATA
I2S2_CODEC_XSP_BCLK
I2S0_CODEC_ASP_MCK_R
I2S0_CODEC_ASP_DOUT
I2S0_CODEC_ASP_DIN
I2S0_CODEC_ASP_BCLK
OSCAR_TIME_SYNC_HOST_INT
GPIO_BTN_SRL_L
GPIO_BTN_HOME_L
I2S0_CODEC_ASP_MCK
I2S2_CODEC_XSP_DOUT
I2S3_SOC2BT_BCLK
SPI1_GRAPE_MISO
GPIO_BOARD_ID0
I2S1_SPKAMP_LRCK
I2S1_SPKAMP_DIN
UART6_TS_ACC_RXD
UART6_TS_ACC_TXD
UART4_SOC2OSCAR_TXD
CLK_32K_SOC2CUMULUS
UART5_BATT_RTXD
UART4_OSCAR2SOC_RXD
NC_UART2_CTS
NC_UART2_RTS
I2C3_SDA_1V8
I2C3_SCL_1V8
SEP_I2C0_SDA
SEP_I2C0_SCL
BB_JTAG_TDO
BB_JTAG_TRST_L
I2C2_SCL_1V8
I2C0_SDA_1V8
I2C0_SCL_1V8
I2C2_SDA_1V8
TP_SOC_TST_CPUSWITCH_OUT
SEP_I2C0_SCL
NC_SEP_7816UART1_RST
I2S3_SOC2BT_LRCK
GPIO_BOARD_REV0
GPIO_BOARD_REV1
GPIO_BOARD_REV2
GPIO_CODEC_IRQ_L
GPIO_SOC2BB_WAKE_MODEM
GPIO_GRAPE_IRQ_L
BB_IPC_GPIO
GPIO_ALS_IRQ_L
GPIO_BOARD_ID3
GPIO_BB2SOC_RESET_DET_L
GPIO_BOOT_CONFIG0
GPIO_PMU2SOC_IRQ_L
GPIO_SOC2PMU_KEEPACT
GPIO_GRAPE_RST_L
GPIO_BB2SOC_GPS_SYNC
GPIO_SOC2BB_RADIO_ON_L
GPIO_BOOT_CONFIG1
GPIO_FORCE_DFU
TP_GPIO_DFU_STATUS
GPIO_SOC2OSCAR_DBGEN
GPIO_BOOT_CONFIG2
GPIO_BOOT_CONFIG3
GPIO_SOC2BB_RST_L
GPIO_PROX_IRQ_L
GPIO_SPKAMP_RST_L
GPIO_TS2SOC2PMU_INT
GPIO_SPKAMP_LEFT_IRQ_L
GPIO_SOC2LCD_PWREN
GPIO_BT_WAKE
GPIO_BB2SOC_GSM_TXBURST
I2C1_SOC2OSCAR_SWDCLK_1V8
GPIO_BOARD_ID2
I2C2_SDA_1V8
I2C3_SCL_1V8
I2C3_SDA_1V8
DWI_AP_CLK
GPIO_SPKAMP_RIGHT_IRQ_L
GPIO_SPKAMP_KEEPALIVE
NC_GPIO_BB_HSIC_DEV_RDY
NC_GPIO_GYRO_IRQ1
I2S1_SPKAMP_BCLK
I2S1_SPKAMP_MCK_R
=PP1V8_S2R_MISC
SOCHOT0_L
051-0886
A.0.0
7 OF 121
5 OF 54
1
2
1
2
1
2
1
2
1
2
1
2
1 2
1 2
1 2
1
2
1
2
1
2
1
2
1 2
1 2
AD5
Y31
W31
AM5
AU3
AV3
AP1
AN4
AN3
AM1
AM2
AM3
AL5
AK3
AK4
AL4
AL2
AR18
AR19
AC32
AD34
AC31
AE5
AE2
AF1
AE4
AT17
AT16
AR16
AP16
AT15
AT14
AR14
AP15
AD1
AV13
AT13
AT12
AN14
AR13
AP12
AP13
AK2
AJ4
AB2
AJ5
AG5
AH4
AH2
AH3
AG4
AG3
AG1
AF2
AB1
AC5
AT3AP14
AU13
AN1
AT2
AF4
AF3
AP11
AN12
AV10
AN8
AP7
AR6
AU6
AR5
AU4
AV4
AU5
AV5
AT5
AP5
AN6
AP17
AP18
AA32
AA33
AA31
AR2
AR1
AE31
AE32
AE33
AD31
AF33
AG31
AH33
AG34
AF31
AG32
E30
AJ34
AH34
AH31
AJ33
AL33
AK33
AK34
AJ32
AL34
C30
AL31
AK31
AJ31
AL32
W32
W30
AR11
AT11
AU7
AP8
AR7
AV6
AT19
AT18
AP19
AB31
AB33
AP4
AR4
AP3
AP2
AA34
AT10
AN17
1
2
1
2
1
2
1
2
1 2
1 2
1
2
457101854
5 16
5 48
5 44 53
28
24 28
24 28
5 49 52
5 44 53
5 52
5 16 52
44 53
5 48
55154
5 17 48
519
519
4571018545 13 48
5 17 48
55154
54
44 53
52022
52022
551
551
51652
5114852
5114852
51652
55154
5 49 52
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
OUT
OUT
OUT
OUT
PPN0_ALE
PPN0_CEN0
PPN0_CEN1
PPN0_CLE
PPN0_DQS
PPN0_IO0
PPN0_IO1
PPN0_IO2
PPN0_IO3
PPN0_IO4
PPN0_IO5
PPN0_IO6
PPN0_IO7
PPN0_REN
PPN0_VREF
PPN0_WEN
PPN0_ZQ
PPN1_ALE
PPN1_CEN0
PPN1_CEN1
PPN1_CLE
PPN1_IO0
PPN1_IO1
PPN1_IO2
PPN1_IO3
PPN1_IO4
PPN1_IO5
PPN1_IO6
PPN1_REN
PPN1_VREF
PPN1_WEN
PPN1_ZQ
PPN1_DQS
PPN1_IO7
SYM 4 OF 13
VSS
VSS
SYM 11 OF 13
VSSVSS
SYM 12 OF 13
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
VDDIO18_GRP3
1252
12
12
12
12
12
12
12
1253
12
12
12
12
100K
1/32W
1%
MF
01005
R0831
MF
R0832
100K
1%
1/32W
01005
12 52
12
12
12
12
12
12
12
12
1253 12
12
12
12
12
10%
0.01UF
X5R
01005
6.3V
C0860
C0861
10%
0.01UF
X5R
01005
6.3V
R0860
50K
MF
1/32W
01005
1%
R0861
50K
MF
1/32W
1%
01005
U0652
POP-1GB-DDR
H6P
FCMSP
OMIT
CRITICAL
01005
R0870
1%
240
1/32W
MF
01005
R0871
1%
240
MF
1/32W
FCMSP
POP-1GB-DDR
H6P
U0652
OMIT
CRITICAL
FCMSP
POP-1GB-DDR
H6P
U0652
OMIT
CRITICAL
SYNC_DATE=04/18/2011SYNC_MASTER=N/A
SOC: NAND
NC_PPN1_CEN1NC_PPN0_CEN1
FMI1_CE0_L
PPVREF_FMI_SOC
FMI0_AD<4>
FMI0_AD<0>
FMI0_CE0_L
FMI0_WE_L
FMI0_AD<7>
FMI0_AD<6>
FMI0_AD<5>
FMI0_AD<2>
FMI0_AD<1>
FMI0_DQS
FMI0_ALE
FMI1_AD<1>
FMI1_AD<0>
FMI1_AD<2>
FMI1_AD<4>
FMI1_AD<3>
FMI1_AD<7>
FMI1_AD<6>
FMI1_AD<5>
FMI1_CLE
FMI1_ALE
FMI1_DQS
=PP1V8_NAND_SOC
FMI0_ZQ FMI1_ZQ
FMI1_WE_L
FMI1_RE_LFMI0_RE_L
FMI0_CLE
FMI0_AD<3>
=PP1V8_NAND_SOC
051-0886
A.0.0
8 OF 121
6 OF 54
1
2
1
2
2
1
2
1
1
2
1
2
A31
G32
H31
B31
D34
B32
C32
C33
C34
F32
F33
F34
G34
D33
D31
A32
E33
N34
R32
P32
P31
M34
M33
L32
M32
K32
J32
H33
L31
N31
N32
K33
L34
H34
1 2 1 2
A11
A1
AA3
AF29
AJ30
A3
A4
A5
A7
A9
A13
A14
A16
A18
A25
A28
A30
A33
A34
AA1
AA2
AA4
AA8
AA10
AA12
AA14
AA16
AA18
AA22
AA24
AA26
AA28
AA30
AB5
AB7
AB9
AB11
AB15
AB17
AB19
AB21
AB23
AB25
AB27
AB29
AB32
AC4
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AC26
AC28
AC30
AC34
AD2
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD21
AD23
AD25
AD29
AD32
AE3
AE8
AE10
AE12
AE16
AE18
AE22
AE24
AE26
AE28
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF23
AF32
AG2
AG8
AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26
AG28
AG30
AH5
AH7
AH9
AH11
AH13
AH15
AH17
AH19
AH21
AH23
AH25
AH27
AH29
AH32
AJ1
AJ3
AJ8
AJ10
AJ12
AJ14
AJ16
AJ18
AJ22
AJ24
AJ26
AK5
AK7
AK9
AK11
AK13
AK15
AK17
AK19
AK21
AK23
AK27
AK29
AK32
AL3
AL6
AL8
AL10
AL12
AL14
AL16
AL18
AL20
AL22
AL24
AL26
AL28
AL30
AM4
AM7
AM18
AM30
AN2
AN5
AN7
AB6
AM9
AM11
AM13
AN16
AM15
AN19
AN20
AN21
AN22
AN23
AN24
AJ28
A2
AB13
AE14
AN31
AP25
AP26
E10
E11
E12
G28
G26
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
G5
G4
G3
G1
F31
F30
F26
F15
F14
F13
F12
F10
F9
F8
F7
F6
F5
F4
F3
F2
E34
E32
E31
E22
E21
E20
E19
E18
E15
E14
E13
E8
E7
E5
E4
E3
E1
D22
D21
D20
D19
D18
D17
D15
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
C31
C29
C27
C26
C23
C22
C19
C18
C17
C16
C15
C13
C11
C10
C9
C7
C6
C5
C3
C2
C1
B34
B33
B30
B28
B25
B19
B18
B17
B16
B15
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B2
B1
AV34
AV33
AV20
AV18
AV16
AV14
AV11
AV9
AV2
AV1
AU34
AU33
AU21
AU18
AU16
AU11
AU2
AU1
AT32
AT31
AT30
AT29
AT28
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
AT6
AT4
AT1
AR32
AR20
AR17
AR15
AR12
AR8
AR3
AP28
AP27
AP24
AN33
AN32
AR29
AR28
AR25
AR24
AR22
AR21
E9
C12
AP21
AP20
AP6
AN34
AP32
AR23
E6
C24
AP30
AP31
D32
D16
AP29
6 54
654
OUT
OUT
OUT
BI
IN
IN
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
IN
IN
IN
IN
DP_PAD_AUXN
DP_PAD_AUXP
DP_PAD_AVDD_AUX
DP_PAD_AVDD0
DP_PAD_AVDD1
DP_PAD_AVDD2
DP_PAD_AVDD3
DP_PAD_AVDDP0
DP_PAD_AVDDX
DP_PAD_AVSS_AUX
DP_PAD_AVSS0
DP_PAD_AVSS1
DP_PAD_AVSS2
DP_PAD_AVSS3
DP_PAD_AVSSP0
DP_PAD_AVSSX
DP_PAD_DC_TP
DP_PAD_DVDD
DP_PAD_DVSS
DP_PAD_R_BIAS
DP_PAD_TX0N
DP_PAD_TX0P
DP_PAD_TX1N
DP_PAD_TX1P
DP_PAD_TX2N
DP_PAD_TX2P
DP_PAD_TX3N
DP_PAD_TX3P
EDP_HPD
SYM 6 OF 13
MIPI0C_DPDATA0
SENSOR1_RST
SENSOR1_CLK
MIPI1C_DPDATA0
SENSOR0_RST
SENSOR0_ISTRB
SENSOR0_CLK
MIPI1D_VREG_0P4V
MIPI1D_VDD18
MIPI1C_DPDATA1
MIPI1C_DPCLK
MIPI1C_DNDATA1
MIPI1C_DNDATA0
MIPI1C_DNCLK
MIPI0D_VREG_0P4V
MIPI0D_VDD18
MIPI0D_DPCLK
MIPI0D_DNCLK
MIPI0C_DPDATA2
MIPI0C_DPDATA1
MIPI0C_DNDATA2
MIPI0C_DNDATA1
MIPI_VSS
ISP0_SDA
ISP0_SCL
ISP1_SCL
MIPI0C_DPDATA3
MIPI0C_DNDATA3
MIPI0C_DPCLK
MIPI0D_DNDATA3
MIPI0D_DPDATA3
MIPI0D_DNDATA2
MIPI0D_DPDATA2
MIPI0D_DNDATA1
MIPI0D_DPDATA1
MIPI0C_DNCLK
MIPI0D_DPDATA0
MIPI0D_DNDATA0
MIPI_VDD10
SENSOR1_ISTRB
MIPI0C_DNDATA0
ISP1_SDA
SENSOR0_XSHUTDOWN
SENSOR1_XSHUTDOWN
SYM 5 OF 13
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
BI
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(2MA)
(2MA)
(55MA)
VDDIO18_GRP1
VDDIO18_GRP1
MIPI_VDD10
(50MA)
(50MA)
(1MA)
(50MA)
(14MA)
(50MA)
VDDIO18_GRP3
(14MA)
(10MA)
DISPLAYPORT
20 52
20 52
20 52
20 52
20 53
20 53
R0940
49.9
01005
01005
5%
2.2K
1/32W
MF
R0932
1/32W
R0933
01005
5%
2.2K
MF
20 53
20 53
R0941
01005
100
23 52
23 52
01005
5%
2.2K
1/32W
MF
R0931
01005
2.2K
5%
1/32W
MF
R0930
23 52
23 52
2353
2353
2353
2353
2353
2353
CRITICAL
OMIT
U0652
FCMSP
POP-1GB-DDR
H6P
C0962
20%
0.1UF
X5R-CERM
6.3V
01005
20%
0204
1UF
4V
X6S
C0930
CRITICAL
OMIT
U0652
POP-1GB-DDR
H6P
FCMSP
C0957
1.0UF
0201-1
6.3V
X5R
20%
18 53
18 53
18 53
18 53
18 53
18 53
18
18
18
18 53
18 53
R0900
01005
MF
1/32W
4.99K
1%
NOSTUFF
01005
6.3V
X5R
0.01UF
10%
C0950
C0958
01005
16V
NP0-C0G-CERM
8.2PF
+/-0.5PF
1/32W
0%
0.00
MF
R0901
01005
C0951
16V
01005
5%
56PF
NP0-C0G
C0952
01005
16V
NP0-C0G-CERM
8.2PF
+/-0.5PF
01005
NP0-C0G
C0953
56PF
5%
16V
0201
20%
X5R
6.3V
C0954
0.22UF
C0955
0201-1
6.3V
X5R
1.0UF
20%
C0956
0201-1
6.3V
X5R
1.0UF
20%
SOC: DP,MIPI
SYNC_MASTER=MLB SYNC_DATE=05/04/2012
=PP1V8_MIPI_SOC
NC_MIPI1D_VREG
NC_MIPI0D_VREG
NC_SENSOR1_XSHUTDOWN
NC_SENSOR1_ISTRB
NC_SENSOR0_ISTRB
NC_SENSOR0_XSHUTDOWN
NC_MIPI0C_CAM_REAR_DATA_P2
NC_MIPI0C_CAM_REAR_DATA_N2
MIPI0C_CAM_REAR_DATA_P<0>
EDP_DATA_P<1>
PP1V8_EDP_AVDD_AUX
=PP1V8_SOC
ISP0_CAM_REAR_SCL
ISP0_CAM_REAR_SDA
ISP0_CAM_REAR_CLK
ISP1_CAM_FRONT_CLK_R
MIPI1C_CAM_FRONT_DATA_P<0>
ISP0_CAM_REAR_CLK_R
NC_MIPI1C_CAM_FRONT_DATA_P1
MIPI1C_CAM_FRONT_CLK_P
NC_MIPI1C_CAM_FRONT_DATA_N1
MIPI1C_CAM_FRONT_DATA_N<0>
MIPI1C_CAM_FRONT_CLK_N
NC_MIPI0D_DPCLK
NC_MIPI0D_DNCLK
MIPI0C_CAM_REAR_DATA_P<1>
MIPI0C_CAM_REAR_DATA_N<1>
NC_MIPI0C_CAM_REAR_DATA_P3
NC_MIPI0C_CAM_REAR_DATA_N3
MIPI0C_CAM_REAR_CLK_P
NC_MIPI0D_DNDATA3
NC_MIPI0D_DPDATA3
NC_MIPI0D_DNDATA2
NC_MIPI0D_DPDATA2
NC_MIPI0D_DNDATA1
NC_MIPI0D_DPDATA1
MIPI0C_CAM_REAR_CLK_N
NC_MIPI0D_DPDATA0
NC_MIPI0D_DNDATA0
MIPI0C_CAM_REAR_DATA_N<0>
=PP1V0_MIPI_SOC
=PP1V8_EDP_SOC
SOC_EDP_R_BIAS
EDP_AUX_N
EDP_AUX_P
TP_EDP_PAD_DC_TP
EDP_DATA_N<0>
EDP_DATA_P<0>
EDP_DATA_N<1>
EDP_DATA_N<2>
EDP_DATA_P<2>
EDP_DATA_N<3>
EDP_DATA_P<3>
EDP_HPD
ISP1_CAM_FRONT_SDA
ISP1_CAM_FRONT_SCL
ISP0_CAM_REAR_SHUTDOWN_L
ISP1_CAM_FRONT_CLK
ISP1_CAM_FRONT_SHUTDOWN_L
=PP1V0_EDP_PAD_DVDD_SOC
051-0886
A.0.0
9 OF 121
7 OF 54
1 2
1
2
1
2
1 2
1
2
1
2
B20
A20
F18
F19
F20
F21
F22
G18
F17
G17
H19
G19
G20
G21
H18
H17
E16
F16
G16
E17
B21
A21
B22
A22
B23
A23
B24
A24
D30
2
1
2
1
AU27
AT9
AU9
AT33
AN28
AT8
AN10
AV8
AR30
AR31
AP33
AR33
AP34
AT34
AR34
AR27
AR26
AU30
AV30
AU24
AU26
AV24
AV26
AM28
AM27
AM26
AM25AN29
AV7
AT7
AU8
AU23
AV23
AU25
AV28
AU28
AV29
AU29
AV31
AU31
AV25
AU32
AV32
AN25
AN26
AN27
AM29
AL25
AR10
AV27
AP9
AR9
AP10
2
1
1
2
2
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
2
1
54
4 5 10 18 54
54
54
54
DDR1_VREF_CA
DDR0_VREF_CA
DDR1_RREF_DQ
VSS
DDR0_CKEIN
DDR0_VDD_CKE
DDR1_RREF_CA
DDR0_RREF_CA
DDR0_RREF_DQ
DDR0_VREF_DQ
DDR1_VREF_DQ
VDDCA
VDD2
VDD1
VDDQ
DDR1_VDD_CKE
DDR1_CKEIN
SYM 7 OF 13
VDDIOD_DDR1CA
VDDIOD_DDR0CA
VDDIO18_GRP4
VSS
VDDIO18_GRP2
VDDIO18_GRP1
VDDIOD_DDRDQ
VDDIO18_GRP3
SYM 9 OF 13
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(DDR IMPEDANCE CONTROL)
ON 5/6/12, BY MANU G
NOTE: CKEIN CONFIRMED 1.8V TOLERANT
CAPS FOR VDDIOD ARE SHARED WITH VDDQ
(45MA)
(500MA)
SHARED WITH VDDIOD)
(CURRENT CONSUMPTION
(CURRENT CONSUMPTION
SHARED WITH VDDIOD)
(<1MA)
(<1MA)
(1000MA)
(20MA)
(31MA)
(2MA)
(65MA)
(GPIO,UART,SPI,I2C)
(SENSOR,SOCHOT,PMU)
CAPS FOR VDDIO18_X ARE SHARED WITH VDDIODX
NOSTUFF
0.01UF
10%
6.3V
C1056
X5R
01005
R1056
01005
1.00K
MF
1%
1/32W
R1055
01005
1/32W
MF
1%
1.00K
X5R
6.3V
01005
NOSTUFF
C1054
0.01UF
10%
R1053
01005
MF
1%
1.00K
1/32W
R1054
01005
1%
1/32W
1.00K
MF
0204
1UF
20%
4V
X6S
C1007
1UF
0204
20%
4V
X6S
C1006
R1031
MF
01005
240
1%
1/32W
01005
MF
R1001
240
1/32W
1%
01005
0.1UF
C1000
20%
6.3V
X5R-CERM
C1009
0610
4V
4.3UF
X5R-CERM
20%
20%
4V
X7S
0204
0.47UF
C1004
20%
4V
X5R-CERM
0610
4.3UF
C1015
0610
4V
20%
X5R-CERM
4.3UF
C1027
OMIT
CRITICAL
U0652
H6P
POP-1GB-DDR
FCMSP
4V
0204
20%
X6S
1UF
C1029
4V
0204
X7S
20%
0.47UF
C1026
X6S
1UF
4V
0204
20%
C1028
20%
0.47UF
X7S
0204
4V
C1031
X6S
0204
1UF
20%
4V
C1071
20%
4V
X7S
0.47UF
0204
C1073
402
4.7UF
X5R
6.3V
20%
C1070
X6S
4V
20%
1UF
0204
C1072
H6P
POP-1GB-DDR
FCMSP
OMIT
CRITICAL
U0652
0201
FL1000
1KOHM-25%-0.2A
X5R-CERM
10V
20%
1.0UF
0201-1
C1042
01005
MF
R1000
240
1/32W
1%
R1030
MF
01005
240
1%
1/32W
NOSTUFF
X5R
10%
01005
0.01UF
6.3V
C1002
R1005
01005
1/32W
MF
2.21K
1%
R1006
01005
MF
2.21K
1%
1/32W
NOSTUFF
6.3V
C1052
0.01UF
X5R
10%
01005
01005
MF
2.21K
1%
1/32W
R1051
R1052
01005
MF
1/32W
1%
2.21K
SOC: SRAM, IO PWRS
SYNC_MASTER=N/A SYNC_DATE=04/18/2011
DDR0_CA_ZQ
DDR0_DQ_ZQ
DDR1_CA_ZQ
=PP1V2_S2R_DDR_SOC
PPVREF_DDR1_DQ
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0.6V
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
PPVREF_DDR1_CA
VOLTAGE=0.6V
MIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2MM
PPVREF_DDR0_DQ
MIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
PPVREF_DDR0_CA
=PP1V2_VDDQ_DDR
=PP1V2_S2R_DDR
=PP1V2_VDDQ_DDR
=PP1V2_S2R_DDR
PPVREF_DDR1_DQ
PPVREF_DDR0_DQ
=PP1V2_VDDQ_DDR
=PP1V8_S2R_DDR
RESET_SOC_L
=PP1V8_VDDIO18_SOC
=PP1V2_VDDIOD_SOC
PP1V8_XTAL
PPVREF_DDR1_CA
=PP1V2_S2R_DDR
DDR1_DQ_ZQ
PPVREF_DDR0_CA
051-0886
A.0.0
10 OF 121
8 OF 54
NET_SPACING_TYPE=PWR
NET_SPACING_TYPE=PWR
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=PWR
2
11
2
1
2
2
1
1
2
1
2
2
1
2
1
1
2
1
2
2
1
2
1
2
1
2
1
2
1
Y33
AU17
T4
H27
K9
H25
J31
J20
G30
G31
G33
H1
H2
H3
H4
H5
H29
H32
J2
J3
J4
J5
J10
J12
J18
J22
J24
J26
J28
J30
K1
K3
K4
K7
K11
K13
K15
K17
K19
K21
K23
K25
K27
K29
K31
K34
L2
J6
J8
J14
K5
AP22
AP23
AC33
AU15
F11
D14
U4
AB34
AF34
AV12
AV15
R34
W34
AC2
AD33
C20
G2
J33
L3
P33
U2
U33
Y34
AJ2
AG33
AU10
AU14
AU22
AV17
AU20
C8
C4
C14
D24
AK1
AE34
B3
D25
B14
E2
J34
P34
V33
U1
AU12
AV22
AU19
A6
A8
C25
C21
J1
F1
L1
R1
N1
V1
A10
A12
A15
A17
A19
AE1
AC1
AH1
AL1
Y1
K2
J16
U31
U32
AV21
AV19
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
AG6
AE6
AC6
Y30
AM17
Y19
Y21
Y23
Y27
Y29
Y32
AM8
AM12
Y17
Y15
Y13
Y9
Y5
Y4
Y2
W33
W28
W26
W24
W22
W20
W18
W16
W12
W8
W5
W3
V34
V32
V30
V27
V25
V15
V13
V9
V7
V5
V4
V3
V2
U34
U30
V29
U29
T29
R29
AM24
AM23
AM22
AM21
AM20
Y6
W10
W14
U6
T6
G29
G24
P30
H30
K30
M30
W2
T11
T9
T7
V23
V21
V19
V17
U22
U20
U18
U14
U12
U10
U8
U5
U3
T34
T33
T32
T31
T30
T27
T25
T23
T21
T19
T17
T15
T13
T5
T3
T2
T1
R33
AH30
AD30
AM19
AM10
AH6
AD6
V11
Y3
Y7
Y11
AA6
H10
H11
H12
H13
H14
H15
M6
N6
P6
R6
V6
W6
AM14
AM16
H9
W4
W1
U28
U26
H6
H7
H8
U24
G27
G25
AJ6
AE30
21
2
1
1
2
1
2
2
1
1
2
1
2
2
1
1
2
1
2
54
8
8
8
8
854
854
854
854
8
8
854
54
41011244852
954
54
52
8
854
8
VDD_SENSE
VDDVDD
SYM 10 OF 13
SYM 8 OF 13
VDD_ANA_TMPSADC0
VDD_ANA_TMPSADC1
VDD_ANA_TMPSADC2
VDD_ANA_TMPSADC3
VDD_SRAM_SOC
VSS
VDD_SRAM_CPU
VDD_GPUVDD_CPU
VDD_GPU_SENSE
VDD_SENSE_CPU
SYM 13 OF 13
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(VDD BALLS = VDD_SOC PWR DOMAIN)
7,500MA FOR G3 GPU
@125C
@1.1V/1.2GHZ
10,800MA FOR CPU0+1
@1.1V
@125C
(2.5MA)
(2.5MA)
(2.5MA)
(2.5MA)
@125C
@1.0V
(1500MA)
1,500MA FOR CYCLONE + M$ SRAM
(THERMAL VIRUS)
@1.0V
@125C
2,500MA FOR VDD_SOC
POP-1GB-DDR
H6P
FCMSP
U0652
OMIT
CRITICAL
20%
4V
0610
4.3UF
X5R-CERM
C1148
20%
C1151
1UF
4V
X6S
0204
4V
0.47UF
20%
C1153
X7S
0204
0204
X6S
C1150
1UF
20%
4V
X7S
4V
20%
0204
C1152
0.47UF
FCMSP
POP-1GB-DDR
H6P
U0652
OMIT
CRITICAL
C1160
20%
0.1UF
01005
6.3V
X5R-CERM
OMIT
POP-1GB-DDR
H6P
U0652
CRITICAL
FCMSP
CRITICAL
C1103
4V
X5R-CERM
4.3UF
0610
20%
C1102
X5R-CERM
4.3UF
0610
20%
4V
CRITICAL
C1101
4V
20%
X5R-CERM
4.3UF
0610
CRITICALCRITICAL
C1100
0610
20%
4V
X5R-CERM
4.3UF
C1109
CRITICAL
0204
X6S
4V
20%
1UF
C1114
+/-0.5PF
8.2PF
01005
NP0-C0G-CERM
16V
C1108
CRITICAL
1UF
20%
4V
X6S
0204
C1107
CRITICAL
1UF
20%
4V
X6S
0204
0201
0.22UF
20%
X5R
6.3V
C1113
C1106
20%
1UF
4V
0204
X6S
CRITICAL
4V
20%
1UF
C1105
0204
X6S
CRITICAL
0201
0.22UF
20%
X5R
6.3V
C1112C1111
0.47UF
20%
0204
X7S
4V
CRITICAL
0204
X6S
20%
C1104
1UF
4V
CRITICAL
0204
20%
0.47UF
C1110
CRITICAL
X7S
4V
C1118
CRITICAL
4V
X5R-CERM
0610
4.3UF
20%
C1117
CRITICAL
4.3UF
4V
20%
0610
X5R-CERM
C1122
4V
20%
X5R-CERM
4.3UF
0610
CRITICAL
C1126
20%
1UF
4V
0204
X6S
CRITICAL
C1121
CRITICAL
4V
20%
X5R-CERM
4.3UF
0610
C1125
1UF
20%
4V
X6S
0204
CRITICAL
C1116
20%
X5R
4V
0402
15UF
C1115
20%
X5R
4V
0402
15UF 4.3UF
0610
X5R-CERM
20%
4V
CRITICAL
C1120
C1124
20%
1UF
4V
X6S
0204
CRITICAL
4.3UF
X5R-CERM
0610
20%
4V
CRITICAL
C1119
C1123
20%
1UF
4V
0204
X6S
CRITICAL
C1130
20%
1UF
4V
X6S
0204
CRITICAL
C1129
20%
1UF
4V
X6S
0204
CRITICAL
C1134
01005
8.2PF
NP0-C0G-CERM
16V
+/-0.5PF
0201
0.22UF
20%
C1133
6.3V
X5R
C1128
20%
1UF
4V
0204
X6S
CRITICAL
C1127
1UF
20%
4V
0204
X6S
CRITICAL
C1132
CRITICAL
0204
X6S
4V
20%
1UF
C1131
CRITICAL
0204
X6S
4V
20%
1UF
C1138
4V
0204
0.47UF
20%
CRITICAL
X7S
0.47UF
4V
20%
0204
CRITICAL
C1142
X7S
C1137
4V
20%
0204
0.47UF
CRITICAL
X7S
CRITICAL
4V
20%
0204
C1141
0.47UF
X7S
0201
6.3V
X5R
C1145
0.22UF
20%
C1136
20%
0204
4V
0.47UF
CRITICAL
X7S
C1140
CRITICAL
4V
0204
0.47UF
20%
X7S
20%
CRITICAL
C1135
0.47UF
4V
X7S
0204
C1139
CRITICAL
20%
0.47UF
0204
4V
X7S
01005
20%
6.3V
X5R
0.22UF
C1144
01005
20%
6.3V
0.22UF
X5R
C1143
CRITICAL
C1187
X7S
4V
20%
0.47UF
0204
CRITICAL
C1186
20%
4V
0204
0.47UF
X7S
CRITICAL
C1185
0.47UF
20%
0204
X7S
4V
CRITICAL
C1184
20%
0204
X7S
4V
0.47UF
CRITICAL
C1183
0204
4V
1UF
20%
X6S
CRITICAL
C1182
4V
1UF
20%
X6S
0204
C1194
8.2PF
+/-0.5PF
01005
NP0-C0G-CERM
16V
0.22UF
X5R
6.3V
20%
01005
C1193C1192
01005
20%
6.3V
X5R
0.22UF
C1191
01005
20%
6.3V
X5R
0.22UF
C1190
01005
20%
6.3V
X5R
0.22UF
CRITICAL
20%
1UF
4V
0204
X6S
C1181
CRITICAL
20%
0204
1UF
4V
X6S
C1180
CRITICAL
20%
1UF
4V
X6S
C1179
0204
CRITICAL
X6S
4V
20%
1UF
0204
C1178
CRITICAL
0610
4V
20%
X5R-CERM
4.3UF
C1177
CRITICAL
4V
X5R-CERM
4.3UF
0610
20%
C1176
CRITICAL
20%
X5R-CERM
4.3UF
0610
4V
C1175
CRITICAL
4.3UF
0610
4V
20%
X5R-CERM
C1174
CRITICAL
4V
20%
4.3UF
0610
X5R-CERM
C1173
CRITICAL
X5R-CERM
4V
20%
4.3UF
0610
C1172
15UF
0402
4V
X5R
20%
C1171
15UF
0402
4V
20%
X5R
C1170
0.47UF
0204
4V
X7S
20%
C1189
CRITICAL
0204
4V
X7S
20%
0.47UF
CRITICAL
C1188
SOC: VDD, SRAM, CPU, GPU PWRS
SYNC_MASTER=N/A SYNC_DATE=04/18/2011
=PPVDD_CPU
=PPVDD_GPU
PPVDD_CPU_SOC_SENSE
PPVDD_GPU_SOC_SENSE
=PP1V8_VDDIO18_SOC
=PPVDD_SRAM_SOC
PPVDD_SOC_SOC_SENSE
=PPVDD_SOC
051-0886
A.0.0
11 OF 121
9 OF 54
P20
P22
K10
K8
K18
K16
K14
K12
K6
J29
J27
J23
J21
J19
J17
J15
J13
J11
AK6
AK20
R7
V31
R17
U23
R25
V22
J25
N27
N17
N15
N13
AN11
Y20
Y18
Y16
W19
W17
W7
V28
V26
V24
V20
V18
V16
V14
U27
U25
U21
U19
U17
U7
T28
T26
T24
T22
T20
T18
T16
T14
R27
R23
R21
R19
R15
R13
P28
P24
P18
P16
P14
P12
P10
P8
N29
N25
N23
N21
N19
N11
N9
N7
M26
M24
M22
M20
M18
M16
M14
M12
M10
L27
L25
L23
L21
L19
L17
L15
L13
L11
L9
L7
K28
J9
J7
H28
H24
AN9
AL23
AK30
AN18
AF30
AF20
AF6
AE21
AN15
AD20
AN13
AB20
AB14
AA17
K20
AA7
U15
P26
M28
L29
AA19
R11
R9
K26
K24
K22
H26
AH20
AB30
M8
2
1
2
1
2
1
2
1
2
1
R28
R30
R31
AJ20
AA20
AB4
H22
AA9
AA11
AA13
AA15
AB8
T10
T12
U11
L4
L5
L6
L8
L10
L12
L14
L16
L18
L20
L22
L24
L26
L28
L30
L33
M1
M2
M3
M4
M5
M7
M9
M11
M13
M15
M17
M19
M21
N3
N5
N8
N10
N12
N14
N16
N18
N20
N22
N24
N26
N28
N30
P1
P2
P3
P4
P7
P9
P11
P13
P17
P19
P21
P23
P25
P27
P29
R2
R3
R4
R5
R8
R10
R16
R18
R24
R26
T8
U9
W13
V10
V8
U13
W15
W11
W9
V12
Y8
AD24
AD26
AD28
AE23
AE25
AE27
AF24
AF26
AF28
AK25
Y25
M23
M25
M27
M29
M31
N2
N4
N33
P5
P15
R12
R22
R14
R20
Y14
Y12
Y10
2
1
AL29
AL9
AL7
AL19
AC29
AD22
AL13
AL11
AK8
AK14
AK10
AJ9
AJ19
AJ17
AJ15
AH8
AH16
AH12
AG13
AB18
AF8
AF18
AF10
AE9
AE7
AE19
AE17
AB16
AE13
AE11
AD8
AD18
AD16
AD14
AD12
AD10
AB10
AB26
AB24
Y28
Y26
Y24
Y22
W27
W25
W21
AA29
AL27
AL21
AK28
AJ29
AJ25
AJ23
AA27
AJ21
AH26
AH24
AH22
AG21
AB12
AC9
AC19
AF27
AF25
AC27
AC25
AB28
AC23
AC21
AE15
AG9
AG7
AC11
AA25
AA23
AC17
AC15
AC13
AF12
AF14
AF16
AG23
AG27
AF22
AE29
AD27
AK12
AJ7
AJ13
AH18
AH14
AH10
AG15
AC7
AA21
AB22
AG11
AG17
AJ11
AK16
AK18
AL15
AL17
AA5
AM6
AN30
AG19
AG25
AG29
AH28
AJ27
AK22
AK24
AK26
W29
W23
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
54
54
53
854
54
53
54
OUT
CLK
RESET
DETGND
GND
GND
GND
GND
GND
I/O
DETECT
VCC VPP
OUT
BIIN
IN
SCHEMATIC DEFINED CONSTRAINTS (YES/NO)
CKPLUS RULE EXCEPTIONS
TABLE_DASHBOARD_INFO
REQUIRED
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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B
A
NOTICE OF PROPRIETARY PROPERTY:
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D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
EVT101
BOARD_ID[1]
MLB_C
SIM CARD
SPI0 TEST MODE
MLB
BOARD REVISION
S/W READ FLOW
2. DISABLE PU AND ENABLE PD
1. SET GPIO AS INPUT
BOARD_ID[0]
ID[3-0] SYSTEM
1. SET GPIO AS INPUT
BOOT_CONFIG[3-0]
2. DISABLE PU AND ENABLE PD
BOOT_CONFIG[3] (GPIO29)
S/W READ FLOW
BOOT_CONFIG[0] (GPIO18)
BOOT_CONFIG[2] (GPIO28)
BOARD ID
3. READ
BOARD_ID[3]
BOARD_ID[2]
BRD_REV[2-0]
3. READ
1. SET GPIO AS INPUT
S/W READ FLOW
3. READ
BOOT_CONFIG[1] (GPIO25)
BOOT CONFIG ID
1010 J85 AP
1011 J85 DEV
1100 J86 AP
1101 J86 DEV
1110 J87 AP
1111 J87 DEV
MLB_B
0000
0010
JTAG
SPI0
0011
0001
2. ENABLE PU AND DISABLE PD
NAND <-- SELECTED
NAND TEST MODE
ID_J85_J87
2.2K
5%
01005
1/32W
MF
R1205
01005
5%
MF
1/32W
2.2K
R1201
NOSTUFFNOSTUFF
2.2K
1/32W
5%
R1200
MF
01005 01005
5%
2.2K
1/32W
MF
R1203
NOSTUFF
MF
1/32W
2.2K
5%
R1206
ID_DEV
01005
ID_J86_J87
5%
2.2K
01005
1/32W
MF
R1204
R1260
5%
100
MF
1/32W
01005
01005
1/32W
2.2K
5%
MF
R1213
4 52
100
5%
1/32W
MF
01005
R1210
01005
R1250
0%
0.00
1/32W
MF
NOSTUFF
SIM-CARD-X113-X223
F-ST-SM
CELL
J3000
24 28 52
24 28 52242852
242852
C3002
CELL
CERM
6.3V
5%
100PF
01005
01005
MF
1/32W
1%
CELL
15.00K
R3000
C3001
0402
X5R
10%
16V
1.0UF
CELL
01005
MF
1/32W
5%
2.2K
R1202
1/32W
5%
100
R1211
01005
MF
NOSTUFF
2.2K
01005
5%
MF
R1207
1/32W
2.2K
MF
5%
R1208
01005
1/32W
NOSTUFF
5%
2.2K
01005
1/32W
MF
R1209
NO
SYNC_DATE=04/11/2011SYNC_MASTER=N/A
SOC: MISC & ALIASES
GPIO_BOOT_CONFIG2
SIMCRD_CLK_CONN
SIMCRD_RST_CONN
PP_LDO6_RUIM_1V8
NC_J3000_5
SIMCRD_IO_CONN
SIM_TRAY_DETECT
MAKE_BASE=TRUE
WDOG_SOC WDOG_SOC2PMU_RESET_IN
MAKE_BASE=TRUE
I2S3_BT2SOC_DATA I2S4_BT2SOC_DATA
I2S3_SOC2BT_DATA
MAKE_BASE=TRUE
I2S4_SOC2BT_DATA
I2S3_SOC2BT_BCLK
MAKE_BASE=TRUE
I2S4_SOC2BT_BCLK
I2S3_SOC2BT_LRCK
MAKE_BASE=TRUE
I2S4_SOC2BT_LRCK
RESET_SOC_LJTAG_SOC_TRST_L
JTAG_SOC_SEL
GPIO_BOARD_ID1
GPIO_BOARD_REV1
SOC_FAST_SCAN_CLK
GPIO_BOARD_ID2
GPIO_BOARD_REV2
GPIO_BOOT_CONFIG3
GPIO_BOARD_REV0
GPIO_BOARD_ID3
SOC_HOLD_RESET
SOC_TESTMODE
=PP1V8_SOC
=PP1V8_SOC
GPIO_BOARD_ID0
GPIO_BOOT_CONFIG0
GPIO_BOOT_CONFIG1
051-0886
A.0.0
12 OF 121
10 OF 54
1
2
1
2
1
2
1
2
1
2
1
2
1 2
1
2
1
2
1 2
3
2
8
11
10
12
4
9
6
7
1
5
2
1
1
2
2
1
1
2 1
2
1
2
1
2
1
2
5
24252752
4 48
5 44
5 44
5 44
5 44
4 8 11 24 48 52452
5
5
4
5
5
5
5
5
4
4 52
457101854
457101854
5
5
5
OUT
IN
OUT
OUT
OUT
DIG_DP
DVSS
DVSS
DVSS
DIG_DN
USB1_DP
USB1_DN
USB0_DP
UART0_TX
USB0_DN
UART1_TX
UART0_RX
UART2_TX
UART1_RX
JTAG_CLK
UART2_RX
JTAG_DIO
ACC_PWR
VDD_3V0
VDD_1V8
P_IN
ACC1
ACC2
DP1
DN1
DP2
DN2
CON_DET_L
HOST_RESET
SWITCH_EN
SDA
INT
SCL
BYPASS
POW_GATE_EN*
BRICK_ID
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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A
NOTICE OF PROPRIETARY PROPERTY:
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
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SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
343S0658 = TRISTAR 2, A1
TRISTAR
343S0614 = TRISTAR 1
TO USB BB MUX
(T’S OFF TO H4A UART4)
AP USB
ACCESSORY UART
AP DEBUG UART
TRISTAR BYPASS FOR 3V LDO
BB DEBUG UART
343S0639 = TRISTAR 2, A0
998-5855 = TRISTAR 2, TC
46
4 8 10 24 48 52
48
CRITICAL
C1303
1.0UF
X5R-CERM
10V
20%
0201-1
0.1UF
6.3V
C1302
10%
CERM-X5R
0201
0.1UF
X5R-CERM
C1300
01005
6.3V
20%
0.1UF
20%
6.3V
X5R-CERM
01005
C1301
5 48
+/-0.5PF
16V
01005
8.2PF
C1321
NP0-C0G-CERM
C1320
16V
01005
NP0-C0G-CERM
8.2PF
+/-0.5PF
C1322
16V
NP0-C0G-CERM
01005
+/-0.5PF
8.2PF
R1370
MF
0.00
0%
1/32W
01005
15
C1360
10V
20%
X5R-CERM
1.0UF
0201-1
CRITICAL
C1361
10%
1UF
402
X5R
25V
CBTL1610A1UK
U1300
CRITICAL
WLCSP
SYNC_DATE=N/ASYNC_MASTER=N/A
IO: TRISTAR
MIKEY_TS_P
MIKEY_TS_N
USB_BB_P
USB_BB_N
USB_SOC_P
UART6_TS_ACC_TXD
USB_SOC_N
UART0_SOC_TXD
UART6_TS_ACC_RXD
UART3_BB2SOC_TX
UART0_SOC_RXD
JTAG_SOC_TCK
UART3_SOC2BB_TX
JTAG_SOC_TMS
=PP3V0_S2R_TRISTAR
PPVBUS_PROT
PPOUT_E75_ACC_ID1
PPOUT_E75_ACC_ID2
E75_DPAIR1_P
E75_DPAIR1_N
E75_DPAIR2_P
E75_DPAIR2_N
TS_CON_DET_L
TS2PMU_RESET_IN
RESET_SOC_L
I2C0_SDA_1V8
GPIO_TS2SOC2PMU_INT
I2C0_SCL_1V8
TRISTAR_BYPASS
NET_SPACING_TYPE=PWR
VOLTAGE=3V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=0.5MM
OVP_SW_EN_L
PMU_USB_BRICKID
L81_MBUS_REF
=PP1V8_S2R_TRISTAR =PP3V3_ACC
051-0886
A.0.0
13 OF 121
11 OF 54
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1 2
2
1
2
1
C3
F5
C1
A6
C4
A1
B1
A3
E2
B3
F2
E1
D2
F1
A5
D1
B5
D5
F4
F3
F6
C5
E5
A2
B2
A4
B4
E3
B6
E4
D3
C6
D4
E6
D6
C2
1552
1552
245253
245253
452
552
452
552
552
5242852
552
452
5242852
452
54
46 52
43
43
43
43
43
43
43
5 48 52
5 48 52
48
54 54
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IO0-1
IO7-1
IO6-1
IO3-1
IO4-1
IO5-1
IO1-1
IO2-1
IO7-0
IO5-0
IO6-0
IO4-0
IO2-0
IO3-0
IO1-0
IO0-0
VCC
CLE1
CE1*
CLE0
CE0*
WE0*
ALE0
RE0
RE0*
DQS0*
R/B0*
DQS0
ALE1
WE1*
RE1
RE1*
DQS1
DQS1*
R/B1*
ZQ
VREF
VSSQVSS
VCCQ
VDDI
TMSC
TCKC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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NOTICE OF PROPRIETARY PROPERTY:
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12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
ENSURE TRACE INDUCTANCE < 2NH
LAYOUT NOTE FOR U1400 VDDI:
C1413
2.2UF
X5R-CERM
0201
20%
4V
20%
C1412
15UF
4V
0402
X5R
20%
C1411
15UF
4V
0402
X5R
20%
C1410
4V
X5R
15UF
0402
C1404
20%
4V
X7S
0.47UF
0204
C1407
1UF
20%
X5R
6.3V
02010204
20%
C1405
X6S
4V
1UF
6 52
6
6
6
6
6 53
6 52
6
6
6
6
6
R1454
MF
1%
243
1/32W
01005
0201
20%
4V
C1450
2.2UF
X5R-CERM
6
6
6
653
6
6
6
6
6
6
6
6
6
6
6
6
OMIT
LGA-12X17
U1400
CRITICAL
XXNM-XGBX8-MLC-PPN1.5-ODP
R1460
01005
1%
1/32W
MF
50K
R1461
01005
1%
1/32W
MF
50K
6.3V
01005
C1460
X5R
0.01UF
10%
6.3V
01005
C1461
X5R
0.01UF
10%
16V
5%
01005
NP0-C0G
C1491
27PF
16V
5%
01005
NP0-C0G
27PF
C1490
27PF
16V
5%
01005
NP0-C0G
C1492
NP0-C0G
01005
5%
16V
27PF
C1494
27PF
NP0-C0G
01005
5%
16V
C1493
10UF
6.3V
CERM-X5R
0402-2
20%
C1402
20%
CERM-X5R
6.3V
0402-2
10UF
C1401
6.3V
20%
10UF
CERM-X5R
0402-2
C1400
20%
0402-2
CERM-X5R
6.3V
10UF
C1480
1UF
20%
C1406
6.3V
X5R
0201
SYNC_DATE=05/04/2012
NAND STORAGE
SYNC_MASTER=MLB
=PP3V3_NAND
FMI1_AD<3>
FMI1_AD<4>
FMI0_AD<4>
FMI0_CE0_L
NC_U1400_RE0
FMI1_CE0_L
FMI_ZQ_U1400
FMI0_AD<5>
FMI0_RE_L
PPVREF_FMI_NAND
=PP1V8_NAND
FMI1_AD<0>
FMI1_AD<7>
FMI1_AD<6>
FMI1_AD<5>
FMI1_AD<1>
FMI0_AD<7>
FMI0_AD<6>
FMI0_AD<2>
FMI0_AD<3>
FMI0_AD<1>
FMI0_AD<0>
FMI1_CLE
FMI0_CLE
FMI0_WE_L
FMI0_ALE
FMI0_DQS
FMI1_ALE
FMI1_WE_L
NC_U1400_RE1
FMI1_RE_L
FMI1_DQS
NC_U1400_DQS1
TP_TMSC_U1400
TP_TCKC_U1400
TP_U1400_RB0
NC_U1400_DQS0
TP_U1400_RB1
=PP1V8_NAND
PPVDDI_NAND
FMI1_AD<2>
051-0886
A.0.0
14 OF 121
12 OF 54
2
1
2
1
2
1
2
12
1
2
1
2
1
1
2
2
1
G1
G7
J7
N3
N5
L7
J1
L1
H6
K6
J5
L5
J3
K2
H2
G3
F2
M6
B6
C3
C5
A3
A5
E3
C1
B4
C7
F4
E5
H4
D2
E1
D4
D6
M4
K4
E7
A1
G5
OA8
OF8
G0
OE0
OD8
OC8
N7
OE8
OD0
OC0
A7
M2
L3
F6
B2
OF0
G8
N1
OB8
OB0
OA0
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
12
1
2
1
2
1
2
1
2
1
54
12 48 54
53
53
53
53
12 48 54
CAP
ON S
D
VDD
GND
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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D
8 7 6 5 4 3
C
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NOTICE OF PROPRIETARY PROPERTY:
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C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
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SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
TOUCH SUBSYSTEM
(PLUG - FLEX 998-4527)
RCPT - MLB 998-4526 -> 516S1054
LAYOUT NOTE:
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION
0.38 DCR
1/32W
MF
R1752
0.000%
01005
J1700
503304-2010
CRITICAL
F-ST-SM-1
MF
R1790
1/32W
1.00K
1%
01005
R1753
0.00
01005
MF
0%
1/32W NOSTUFF
C1761
27PF
5%
NP0-C0G
16V
01005
0201
C1702
X7R-CERM
16V
1000PF
10%
X5R
10V
10%
1UF
402
C1701
27PF
01005
16V
NP0-C0G
5%
C1700
L1700
0201
240OHM-350MA
1000PF
16V
X7R-CERM
0201
C1705
10%
C1704
0201
X5R
6.3V
20%
1UF
0201
10%
1000PF
X7R-CERM
C1708
16V
X5R
6.3V
20%
1UF
0201
C1707
5%
27PF
NP0-C0G
C1703
16V
01005
240OHM-350MA
0201
L1701
0201-2
240-OHM-0.2A-0.8-OHM
L1702
01005
5%
27PF
NP0-C0G
16V
C1706
6.3V
X5R
1UF
20%
0201
C1752
CRITICAL
SLG5AP302
U1700
TDFN
CRITICAL
C1750
0201
10%
0.1UF
X5R-CERM
16V
CRITICAL
C1751
10%
X7R
10V
4700PF
201
CRITICAL
1%
100K
R1751
MF
1/32W
01005
X5R-CERM
10UF
C1753
20%
0402-2
10V
CRITICAL
01005
150OHM-25%-200MA-0.7DCR
L1760
C1760
27PF
5%
NP0-C0G
16V
01005
TOUCH: SUPPORT CKT & CONN
SYNC_MASTER=N/A SYNC_DATE=06/21/2010
PP1V8_GRAPE_SW
GPIO_BTN_HOME_L GPIO_BTN_HOME_FILT_LGPIO_BTN_HOME_R_L
PP3V0_S2R_HALL_FILT
DISPLAY_SYNC_R
SPI1_GRAPE_MOSI
SPI1_GRAPE_MISO
GPIO_GRAPE_IRQ_L
CLK_32K_SOC2CUMULUS
SPI1_GRAPE_CS_L
PP1V8_GRAPE_FILT
GPIO_GRAPE_RST_L
GPIO_BTN_HOME_FILT_L
NC_PMU_GPIO_HALL_IRQ_4
PMU_GPIO_MB_HALL3_IRQ
PMU_GPIO_MB_HALL2_IRQ
PMU_GPIO_MB_HALL1_IRQ
PP5V25_GRAPE_FILT
SPI1_GRAPE_SCLK_RSPI1_GRAPE_SCLK
DISPLAY_SYNC
=PP3V0_S2R_HALL PP3V0_S2R_HALL_FILT
VCC_MAIN_GRAPE_RAMP
=PP1V8_GRAPE
=PPVCC_MAIN_GRAPE
=PP1V8_S2R_GRAPE
=PP5V25_GRAPE PP5V25_GRAPE_FILT
PP1V8_GRAPE_FILT
051-0886
A.0.0
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13
17
24
23
19
11
15
9
7
5
1
3
18
20
12
14
16
8
10
6
4
2
22
21
1 2
1 2
2
1
2
1
2
1
2
1
21
2
1
2
1
2
1
2
1
2
1
21
21
2
1
2
1
7
2 5
3
18
2
1
2
11
2
2
1
21
2
1
52
548 13 52
1352
52
552
552
552
552
552
1352
552
13 52
48
48
48
13 52
525
5
54 13 52
54
54
54
54 13 52
13 52
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(P/N 510S0761 - FLEX)
P/N 510S0760 - MLB
AUDIO_JACK_FLEX RET1
AUDIO_JACK_FLEX MIC2
AUDIO_JACK_FLEX MIC1
AUDIO_JACK_FLEX RET2
PER DAVE BREECE
J1800
CRITICAL
AA07A-S016VA1
F-ST-SM-COMBO
0201-2
L1800
240-OHM-0.2A-0.8-OHM
C1800
NP0-C0G
16V
27PF
5%
01005
0.1UF
10%
6.3V
C1801
CERM-X5R
0201
NP0-C0G
16V
27PF
5%
01005
C1802
R1850
0%
0.00
MF
1/32W
01005
NOSTUFF
NP0-C0G
16V
5%
C1850
01005
27PF
01005
5%
16V
NP0-C0G
56PF
C1821
5%
16V
NP0-C0G
56PF
C1820
01005 01005
C1822
56PF
NP0-C0G
16V
5%5%
16V
NP0-C0G
56PF
01005
C1830
AUDIO: HP FLEX CONN
SYNC_DATE=03/31/2011SYNC_MASTER=N/A
MIN_NECK_WIDTH=0.06 MMVOLTAGE=2.65VPP_LDO14_2V65
LAT_SW2_CTL
GPIO_SOC2AJ_HS3_SHUNT_EN
PP1V8_DMIC_FILT
LAT_SW1_CTL
CONN_HP_LEFT_FILT
CONN_HP_RIGHT_FILT
CONN_HP_HS3_FILT
CONN_HP_HEADSET_DET_FILT
CONN_HP_HS3_REF_FILT
GPIO_SOC2AJ_HS4_SHUNT_EN
DMIC1_FF_SCLK_FILT
DMIC1_FF_SD
CONN_HP_HS4_REF_FILT
CONN_HP_HS4_FILT
DMIC1_FF_SCLK
=PP1V8_DMIC
051-0886
A.0.0
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20
19
18
17
15
13
11
9
7
1
16
14
12
10
8
6
4
2
5
3
21
2
1
2
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
2532333940
2852
5
242852
15
15
15
15
15
5
15
15
15
15
54
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
IN
IN
BI
BI
OUT
OUT
SYM 2 OF 2
DMIC1_SCLK
DMIC2_SD
MCLK
GND13
GND0
TSTI2
TSTI1
TSTI0
GND18
GND17
GND16
GND15
GND14
GND12
GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
RESET*
WAKE*
INT*
CDOUT
CDIN
CCLK
XSP_SDOUT
XSP_SDIN_DAC2_MUTE
XSP_LRCK_FSYNC
XSP_SCLK
ASP_SDOUT
ASP_SDIN
ASP_LRCK
ASP_SCLK
DMIC2_SCLK
DMIC1_SD
CS*
MBUS_REF
SYM 1 OF 2
FLYP
MIC4_BIAS_FILT
AIN3+
AIN1-
FLYN
GNDA
MIC1_BIAS
MIC2_BIAS_FILT_IN
MIC2_BIAS_FILT
MIC2_BIAS
AIN2+
AIN2M
MIC2_BIAS_IN
AIN3-
MIC3_BIAS
MIC3_BIAS_FILT
AIN4+
AIN4-
MIC4_BIAS
GNDP
GNDD
GNDHS
+VCP_FILT
FILT-
FILT+
LINEOUT_REF
LINEOUTB
LINEOUTA
HPDETECT
HS4_REF
HS3_REF
HS4
HS3
HPOUTB
HPOUTA
DN
DP
AOUT2-
AOUT2+
AOUT1_M
AOUT1+
GNDCP
-VCP_FILT
VA
VCP1
VD
VP0
VL
VP1
VPROG_CP
VPROG_MB
SPEAKER_VQ
AIN1+
MIC1_BIAS_FILT
GNDHS
FLYC
VCP0
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEADDIGITAL MIC
TO HEADPHONE JACK
TO THE HP CONNECTOR
U1900 DECAPS CHANGED ON 5/24/12 PER RADAR #11485846
NOTE:
PLACE R1930 & R1931 CLOSE TO U3600
MIKEY BUS FILTER
PLACE L1900 TO 1905 CLOSE
14
0402
10UF
CERM-X5R
CRITICAL
20%
6.3V
C1910
XW1900
SHORT-8L-0.25MM-SM
NOSTUFF
CRITICAL
20%
X5R
4.7UF
C1907
402
6.3V
CRITICAL
4.7UF
X5R
20%
402
6.3V
C1908
22
010055%1/32W MF
R1912
22
MF1/32W 5% 01005
R1913
14
14
5
5
22
01005MF5%1/32W
R1910
MF 010055%
22R19111/32W
5
5
5
553
553
5
5
553
553
553
553
552
4852
48
C1912
X5R
6.3V
402
20%
4.7UF
MF
1/20W
2.21K
1%
R1901
201
0201-1
20%
1.0UF
C1911
X5R
6.3V
1.00K
5%
1/32W
MF
01005
NOSTUFF
R1940
14
14
11
XW1902
NOSTUFF
SHORT-8L-0.25MM-SM
0201 CERM-X5R
0.1UF
10%6.3V
C1916
0201 CERM-X5R
0.1UF
10%6.3V
C1917
SHORT-8L-0.25MM-SM
XW1903
NOSTUFF
R1931
5%
MF
12
201
1/20W
R1930
5%
MF
201
1/20W
12
C1932
5%
25V
0201
NP0-CERM
100PF
SIGNAL_MODEL=EMPTY
C1931
5%
100PF
0201
NP0-CERM
25V
NOSTUFF
C1930
5%
NP0-CERM
25V
100PF
0201
SIGNAL_MODEL=EMPTY
11 52
11 52
L1900
FERR-33-OHM-0.8A-0.09-OHM
0201
L1901
FERR-33-OHM-0.8A-0.09-OHM
0201
L1902
FERR-33-OHM-0.8A-0.09-OHM
0201
L1903
FERR-33-OHM-0.8A-0.09-OHM
0201
L1904
01005
120-OHM-210MA
L1905
120-OHM-210MA
01005
14
14
C1990
01005
16V
NP0-C0G
100PF
5%
C1991
5%
100PF
NP0-C0G
16V
01005
0201
R1950
1.00
1%
1/20W
MF-LF
0201-1
1.0UF
20%
6.3V
CRITICAL
X5R
C1951
X5R
C1950
4.7UF
CRITICAL
20%
402
6.3V
0201
R1951
1/20W
1%
1.00
MF-LF
MF
1/20W
1%
R1952
255K
201
C1913
0.1UF
10%
0201
X5R-CERM
10V
5%
1/20W
MF
0
R1953
201
U1900
WLCSP
CS42L81-CWZR-A1
CRITICAL
WLCSP
U1900
CS42L81-CWZR-A1
0.1UF
0201
X5R-CERM
10V
C1914
10%
CRITICAL
X5R-CERM
4.7UF
20%
10V
0402
C1909C1904
10V
X5R-CERM
0201
10%
0.1UF
20%
6.3V
X5R-CERM
01005
C1915
0.1UF
20%
01005
X5R-CERM
6.3V
0.1UF
C1902
0201
10%
0.1UF
X5R-CERM
10V
CRITICAL
C1903
4.7UF
CRITICAL
6.3V
C1901
X5R
402
20%
4.7UF
C1905
X5R
6.3V 20%
402
C1906
20%
4.7UF
6.3V
402 X5R
14
L1920
240-OHM-0.2A-0.8-OHM
0201-2
C1920
4700PF
10%
10V
X7R
201
NOSTUFF
R1920
01005
3.3K
1/32W
5%
MF
14
SYNC_DATE=01/18/2012
AUDIO: L81 CODEC
SYNC_MASTER=KAVITHA
338S1213 338S1116 RADAR:13373870 SSMC FABU1900
155S0773 155S0453 L1904,L1905 RADAR:11100717
=PP1V7_VA_VCP
NO_TEST=TRUENC_MIC4_BIAS
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
CODEC_HP_HS4_REF
=PP1V8_AUDIO
L81_FLYP
0.15MM
0.3MM
L81_FLYC
0.15MM
0.3MM
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
PP1V7_VCP
VOLTAGE=1.7V
NO_TEST=TRUEAIN1P
NO_TEST=TRUEAIN1N
L81_MIC2_BIAS
L81_MIC2_BIAS_FILT_IN
HP_MIC_POS
MIC1_BIAS_FILT NO_TEST=TRUE
SPI2_CODEC_MISO
SPI2_CODEC_MOSI
SPI2_CODEC_SCLK
SPI2_CODEC_CS_L
L81_MBUS_REF
I2S2_CODEC_XSP_DOUT
L81_FILT
0.30MML81_PVCP 0.15MM
GND_AUDIO_CODEC
L81_NVCP
0.30MM0.15MM
NO_TEST=TRUE
NC_RIGHT_CH_OUT_N
NO_TEST=TRUE
NC_RIGHT_CH_OUT_P
L81_AIN2_POS
VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
PPVCC_VPROG_CP
=PPVCC_MAIN_AUDIO
GND_AUDIO_CODEC
MIC4_BIAS_FILT NO_TEST=TRUE
MIN_NECK_WIDTH=0.15MM
PPVCC_VPROG_MB
VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
L81_FLYN
0.15MM
0.3MM
PPVCC_VPROG_MB_F
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.3MM
VOLTAGE=4.2V
0.15MM
0.20MM
GND_AUDIO_CODEC
VOLTAGE=0V
I2S2_CODEC_XSP_SDOUTI2S2_CODEC_XSP_DIN
DMIC1_FF_SCLK
DMIC1_FF_SD
I2S0_CODEC_ASP_SDOUTI2S0_CODEC_ASP_DIN
L81_DMIC1_FF_SD
NC_DMIC2_SCLK NO_TEST=TRUE
I2S0_CODEC_ASP_BCLK
I2S0_CODEC_ASP_LRCK
I2S0_CODEC_ASP_DOUT
I2S2_CODEC_XSP_BCLK
I2S2_CODEC_XSP_LRCK
GPIO_CODEC_IRQ_L
PMU_GPIO_CODEC_HS_INT_L
I2S0_CODEC_ASP_MCK
L81_DMIC1_FF_SCLK
PMU_GPIO_CODEC_RST_L
=PP1V8_AUDIO
CODEC_MIC_BIAS_FILT
MAKE_BASE=TRUE
NC_MIC3_BIAS NO_TEST=TRUE
NO_TEST=TRUENC_MIC1_BIAS
AIN4P
AIN4N
MAKE_BASE=TRUE
CODEC_AIN
AIN3P
AIN3N
AIN1N
AIN1P
MIC1_BIAS_FILT
MIC4_BIAS_FILT
MIC3_BIAS_FILT
L81_MIC2_BIAS_IN
L81_AIN2_NEG
CODEC_HP_HS3
CODEC_HP_RIGHT MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MMCODEC_HP_HS3
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MMCODEC_HP_HS4
MIN_NECK_WIDTH=0.15MMCODEC_HP_LEFT MIN_LINE_WIDTH=0.20MM
L81_MBUS_P
CONN_HP_HS3_FILT
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.20MM
CONN_HP_RIGHT_FILT
MIN_LINE_WIDTH=0.20MM
CONN_HP_LEFT_FILT
MIN_NECK_WIDTH=0.15MM
CODEC_HP_DET_R
MIN_LINE_WIDTH=0.50MM
CONN_HP_HS4_FILT
MIN_NECK_WIDTH=0.20MM
L81_MBUS_N
AIN4N NO_TEST=TRUE
MIC3_BIAS_FILT NO_TEST=TRUE
NO_TEST=TRUEAIN3N
NO_TEST=TRUEAIN3P
CONN_HP_HEADSET_DET_FILTCODEC_HP_DET
NO_TEST=TRUE
NC_LEFT_CH_OUT_N
CODEC_HP_DET
CODEC_HP_HS4
HP_MIC_NEG
NO_TEST=TRUEAIN4P
NO_TEST=TRUE
NC_LEFT_CH_OUT_P
NO_TEST=TRUE NC_CODEC_LINE_OUT_R
NC_CODEC_LINE_OUT_LNO_TEST=TRUE
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
CONN_HP_HS3_REF_FILT
MIN_NECK_WIDTH=0.1MM
CONN_HP_HS4_REF_FILT
MIN_LINE_WIDTH=0.15MM
L81_MIC2_BIAS_FILT
CODEC_HP_HS3_REF
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
L81_MBUS_N
L81_MBUS_P MIKEY_TS_P
MIKEY_TS_N
NC_SPEAKER_VQ
051-0886
A.0.0
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2
1
21
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
1
1
2
2 1 1 2
1 22 1
1 2
1 2
2
1
2
1
2
1
21
21
21
21
21
21
2
1
2
1
1 2
2
1
2
1
1 2
1 2
2
1
1
2
B2
B7
C8
G5
C6
D4
C7
C4
J5
H7
H5
G7
G6
F8
F7
F6
F5
E7
E6
E5
D8
D7
D6
D5
D3
C9
B10
B9
A7
B8
A6
A4
A5
B5
B4
A1
A2
B3
A3
B6
B1
C5
K5
H10
F2
C3
E4
K10
G2
H2
K3
F3
G4
C1
D1
J3
C2
H4
G3
D2
E2
F4
E10
A10
J2
H9
F1
E1
H6
J6
K6
H8
J7
K7
K1
J1
K8
J8
K4
J4
D9
D10
F9
F10
J9
K9
G1
G9
A9
E8
A8
E9
G10
H1
C10
E3
H3
K2
J10
G8
2
1
2
1
2
1
2
1
2
1
2
1
2
1
12
12
21
2
1
1 2
1654
52
1554
1552
15
15
15
15 52
1654
1552
15
15 52
1554
15
15
15
15
15
15
15
15
15
1552
52
1552
1552
52
15
52
15
15
15
15
15
15
15
1552
15
52
15
15
FILT+
SCL
VP
SDA
VA
ADO
VBST
SW
GNDA
IREF+
OUT+
OUT-
ISENSE+
ISENSE-
VSENSE+
VSENSE-
LDO_FILT
GNDP
INT*
RESET*
ALIVE
MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT
VER1
FILT+
SCL
VP
SDA
VA
ADO
VBST
SW
GNDA
IREF+
OUT+
OUT-
ISENSE+
ISENSE-
VSENSE+
VSENSE-
LDO_FILT
GNDP
INT*
RESET*
ALIVE
MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT
VER1
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
SPEAKER CONNECTOR
UPDATED: DEC 13
BY MARCH 2013. C0 FIXES PROCESS ISSUES.
2. THE CURRENT VERSION OF L19 IS B0 AND WILL CHANGE TO C0
REMOVED BASED ON PERFORMANCE ON J65
1. ALL THE EMI/DESSENSE FILTER COMPONENTS HAVE BEEN
I2C ADDRESS: 1000000X PLACE XWS CLOSE TO CONNECTOR
LEFT SPEAKER AMP
I2C ADDRESS: 1000001X
RIGHT SPEAKER AMP
TFA302610A-SM
2.2UH-20%-3.3A-0.115OHM
L2050
U2040
WLCSP
CS35L19B-CWZR/C0
WLCSP
U2050
CS35L19B-CWZR/C0
CRITICAL
0402-1
X5R-CERM
20%
10V
10UF
C2094C2092
0.1UF
10%
10V
X5R-CERM
0201
C2093
10V
10%
0.1UF
X5R-CERM
0201 X5R-CERM
10UF
CRITICAL
C2095
10V
20%
0402-1
CRITICAL
X5R-CERM
0402-1
20%
10V
10UF
C2091
CRITICAL
C2090
10V
20%
0402-1
X5R-CERM
10UF
10V
C2042
CRITICAL
X5R-CERM
4.7UF
0402
20%
SIGNAL_MODEL=EMPTY
SM
XW2051
SIGNAL_MODEL=EMPTY
SM
XW2050
SIGNAL_MODEL=EMPTY
SM
XW2040
SIGNAL_MODEL=EMPTY
SM
XW2041
C2054
10V
0201
10%
0.1UF
X5R-CERM
C2055
603
X5R
10V
20%
10UF
CRITICAL
R2051
201
MF
1%
44.2K
1/20W
6.3V
CERM-X5R
0.1UF
10%
C2056
0201
4.7UF
X5R-CERM1
CRITICAL
C2058
6.3V
20%
402
402
C2057
20%
CRITICAL
4.7UF
X5R-CERM1
6.3V
R2041
201
MF
1%
1/20W
44.2K
X5R-CERM1
4.7UF
C2048
402
20%
6.3V
CRITICAL
20%
0402
10V
X5R-CERM
C2041
CRITICAL
4.7UF
CRITICAL
C2051
0402
10V
20%
4.7UF
X5R-CERM
C2043
0402
X5R-CERM
10V
CRITICAL
4.7UF
20%
CRITICAL
TFA302610A-SM
L2040
2.2UH-20%-3.3A-0.115OHM
10%
C2044
X5R-CERM
0.1UF
10V
0201
CRITICAL
10UF
C2045
20%
10V
X5R
603 CERM-X5R
10%
6.3V
0.1UF
C2046
0201
X5R-CERM1
CRITICAL
C2047
20%
6.3V
4.7UF
402
MF
1%
1/4W
0.100
R2050
CRITICAL
0402
1%
MF
1/4W
CRITICAL
0.100
R2040
0402
CRITICAL
C2052
X5R-CERM
4.7UF
0402
10V
20%
CRITICAL
C2053
20%
10V
0402
4.7UF
X5R-CERM
SIGNAL_MODEL=EMPTY
XW2077
SM
XW2076
SM
SIGNAL_MODEL=EMPTY
XW2075
SIGNAL_MODEL=EMPTY
SM
SIGNAL_MODEL=EMPTY
SM
XW2074
SYNC_MASTER=KAVITHA
AUDIO: CS35L19A AMPS
SYNC_DATE=01/18/2012
GPIO_SPKAMP_KEEPALIVE
I2C2_SDA_1V8
I2S1_SPKAMP_MCK
SPKR_L_CONN_P
SPKR_L_CONN_P
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
I2S1_SPKAMP_DIN
SPKR_R_VSENSE_N
SPKR_R_VSENSE_N
SPKR_R_CONN_P
SPKR_R_CONN_PMIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
=PP1V7_VA_VCP
SPKR_R_SES_P
SPKR_L_SES_P
SPKR_L_VSENSE_N
SPKR_L_VSENSE_N
=PPVCC_MAIN_AUDIO
SPKR_L_VSENSE_P
SPKR_L_VSENSE_P
SPKR_R_VSENSE_P
SPKR_R_VSENSE_P
L19_R_SWITCH
PP1V7_VA_VCP
I2S1_SPKAMP_BCLK
I2S1_SPKAMP_LRCK
GPIO_SPKAMP_RIGHT_IRQ_L
L19_L_LDO_FILT
L19_R_LDO_FILT
GPIO_SPKAMP_RST_L
NET_SPACING_TYPE=PWRL19_L_VBOOST
L19_R_IREF
L19_L_FILTL19_L_SWITCH
L19_L_IREF
GPIO_SPKAMP_LEFT_IRQ_L
I2S1_SPKAMP_BCLK
I2S1_SPKAMP_LRCK
I2S1_SPKAMP_DOUT
I2C2_SDA_1V8
GPIO_SPKAMP_KEEPALIVE
I2C2_SCL_1V8
GPIO_SPKAMP_RST_L
I2S1_SPKAMP_MCK
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
SPKR_L_CONN_N
SPKR_L_CONN_N
SPKR_L_P
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
SPKR_L_SES_N
MIN_LINE_WIDTH=0.5 MM
SPKR_R_CONN_N
MIN_NECK_WIDTH=0.2 MM
SPKR_R_CONN_N
SPKR_R_P
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
L19_R_FILT
I2C2_SCL_1V8
I2S1_SPKAMP_DIN
I2S1_SPKAMP_DOUT
NET_SPACING_TYPE=PWR
L19_R_VBOOST
=PPVCC_MAIN_AUDIO
SPKR_R_SES_N
=PP1V7_VA_VCP
20 OF 121
A.0.0
051-0886
4 OF 416 OF 54
21
F2
D1
D6
A4
B1
C1
D5
F5
C7
A5
A1
A2
D4
F4
F3
B5
B6
C6
E4
C4
C3
B4
B3
B7
D2
C2
E1
F1
E2
E3
C5
D3
A3
A7
A6
D7
E7
E6
F6
F7
E5
B2
F2
D1
D6
A4
B1
C1
D5
F5
C7
A5
A1
A2
D4
F4
F3
B5
B6
C6
E4
C4
C3
B4
B3
B7
D2
C2
E1
F1
E2
E3
C5
D3
A3
A7
A6
D7
E7
E6
F6
F7
E5
B2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
1 2
1 2
1
2
1 2
2
1
2
1
2
1
21
2
1
2
1
2
1
1 2
1 2
1 2
2
1
2
1
1 2
1 2
1 2
1 2
51652
51652
51653
16 43 5216 43
52
51653
16
16
16 43 5216 43
52
15 16 54
16
16
151654
16
16
16
16
475254
51653
51653
5
516
5
51653
51653
51653
51652
51652
51652
516
51653
16 43 5216 43
52
16 43
52
16 43 52
51652
51653
51653
151654 15 16 54
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
BUTTON CONNECTOR
(MOVED HERE TO SUPPORT COST FORMAT)
(REF DES PRESERVED FOR LAYOUT)
516S0828
01005
MF
1%
1/32W
1.00K
R2900
01005
MF
1/32W
1%
1.00K
R2901
01005
MF
1%
1/32W
1.00K
R2902
01005
1/32W
MF
1%
1.00K
R2903
12.8V-100PF
201-1
DZ2960
12.8V-100PF
201-1
DZ2961
201-1
12.8V-100PF
DZ2962
12.8V-100PF
201-1
DZ2963
CRITICAL
J2960
F-ST-SM
503548-1010
25V
0201
CERM
82PF
5%
C2963
0201-2
240-OHM-0.2A-0.8-OHM
L2963
82PF
5%
25V
0201
CERM
C2962
0201-2
240-OHM-0.2A-0.8-OHM
L2962
82PF
25V
0201
CERM
5%
C2961
0201-2
240-OHM-0.2A-0.8-OHM
L2961
CERM
0201
25V
82PF
5%
C2960
0201-2
240-OHM-0.2A-0.8-OHM
L2960
BUTTON: CONN
SYNC_DATE=N/ASYNC_MASTER=N/A
GPIO_BTN_ONOFF_R_L
GPIO_BTN_VOL_UP_R_L
GPIO_BTN_VOL_DOWN_R_L
GPIO_BTN_SRL_R_L
GPIO_BTN_VOL_DOWN_L
GPIO_BTN_VOL_UP_L
GPIO_BTN_ONOFF_L
GPIO_BTN_SRL_L
GPIO_BTN_ONOFF_L_FILT
GPIO_BTN_VOL_UP_L_FILT
GPIO_BTN_SRL_L_FILT
GPIO_BTN_VOL_DOWN_L_FILT
051-0886
A.0.0
21 OF 121
17 OF 54
1 2
1 2
1 2
1 2
1
2
1
2
1
2
1
2
1
5
3
10
8
6
4
9
7
2
13
11 12
14
2
1
21
2
1
21
2
1
21
2
1
215
5
548
548
52
52
52
52
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
NCIN
OUT
SYM_VER-2
SYM_VER-2
SYM_VER-2
SYM_VER-2
SYM_VER-2
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VDD
D
SON
CAP
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PART NUMBER
ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
REVIEW: 4700PF 0201 132S0187
EDP CONNECTOR SUPPORT
LAYOUT NOTE:
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION
REVIEW: CAN/SHOULD WE USE 132S0316, 0.1UF 20%, 01005
RDAR://PROBLEM/12579948
RDAR://PROBLEM/12579963
TO REDUCE THE 2.5V FROM THE TCON TO 1.8V TO THE AP?
REVIEW: WILL THE DISPLAY INCLUDE A VOLTAGE DIVIDER
RDAR://PROBLEM/12579981
P/N 516S1056
NOTE:
HOWEVER TO BE CONSERVATIVE, DIVIDER CKT IS NOT REMOVED
PER GREG DE MERCEY, EDP_HPD PIN IS 2.5V TOLERANT
BACK-UP DELAYED PWREN CKT
7
C2221
NP0-C0G-CERM
50V
56PF
2%
0201
18
18
18 53
18 53
18 53
18 53
18 53
18 53
18 53
18 53
L2240
01005
240-OHM-25%-0.20A-1.0DCR
C2260
27PF
NP0-C0G
16V
5%
01005
5%
R2243
MF
1/32W
01005
100K
18 53
18 53
18 53
18 53
18 53
18 53
18 53
18 53
18
18
C2232
16V
01005
NP0-C0G-CERM
15PF
5%
F-ST-SM-1
CRITICAL
AA07A-S032-VA1
J2201
L2201
0402A
CRITICAL
FERR-120-OHM-1.5A
47
47
47
47
47
1852
47
CERM
C2230
82PF
0201
5%
25V
1852
1/32W
MF
01005
R2250
7.5K
5%
U2201
CRITICAL
SOT891
74LVC1G32
LCM_PWR_EN_OR_GATE
LCM_PWR_EN_OR_GATE
0.1UF
6.3V
20%
01005
X5R-CERM
C2270
518
01005
0.000%
R2290
MF
1/32W
LCM_PWR_EN_OR_GATE
CRITICAL
C2202
20%
10UF
0402
6.3V
CERM-X5R
518
1/32W
MF
0%
0.00
R2291
01005
LCM_PWR_EN_RES
0.1UF
X5R-CERM
C2203
0201
16V
10%
R2242
1/32W
01005
MF
5%
20.0K
+/-0.5PF
C2233
50V
C0G-CERM
8.2PF
201
0402
220-OHM-1A
L2200
CRITICAL
3.25-OHM-0.1A-2.4GHZ
L2242
CRITICAL
TAM0605-4SM
5%
R2241
100K
MF
01005
1/32W
3.25-OHM-0.1A-2.4GHZ
L2212
CRITICAL
TAM0605-4SM
3.25-OHM-0.1A-2.4GHZ
L2222
CRITICAL
TAM0605-4SM
3.25-OHM-0.1A-2.4GHZ
CRITICAL
L2232
TAM0605-4SM
C2250
01005
0.1UF
6.3V X5R-CERM20%
C2251
6.3V
0.1UF
X5R-CERM20%01005
C2242 0.1UF
6.3V X5R-CERM20%01005
20%
0.1UFC2243
6.3V X5R-CERM01005
0.1UFC2244
X5R-CERM20%01005 6.3V
0.1UFC2245
6.3V X5R-CERM20%01005
0.1UFC2246
6.3V X5R-CERM20%01005
0.1UFC2247
6.3V X5R-CERM20%01005
0.1UFC2248
6.3V X5R-CERM20%01005
3.25-OHM-0.1A-2.4GHZ
L2202
CRITICAL
TAM0605-4SM
C2249 0.1UF
6.3V X5R-CERM20%01005
0201
16V
0.1UF
X5R-CERM
C2239
10%
518
7
7
MF
100K
5%
1/32W
01005
R2205
753
753
753
753
753
753
753
753
TDFN
CRITICAL
U2200
SLG5AP304V
OMIT
C2240
0201
0.1UF
X5R-CERM
16V
10%
0402
10%
X7R
3900PF
C2241
50V
VIDEO: EDP SUPPORT & CONN
SYNC_MASTER=J85 MLB_C SYNC_DATE=12/05/2012
155S0667 155S0583 RDAR://PROBLEM/8616060, RADAR://PROBLEM/9015335
L2242,L2810,L2811,L2812,L2813,L2814,L2710,L2711,L2712,L6030,L6031
EDP_DATA_EMI_CONN_P<0>
EDP_DATA_EMI_CONN_N<0>
EDP_DATA_EMI_CONN_P<1>
EDP_DATA_EMI_N<1>
EDP_DATA_EMI_P<1>
EDP_AUX_EMI_N
EDP_AUX_EMI_PEDP_AUX_P
LCM_OFF_L
EDP_DATA_N<1>
EDP_DATA_N<0>
EDP_DATA_P<0>
EDP_DATA_N<2>
PPVCC_MAIN_LCD_SW_CONN
=PPLED_REG_A PPLED_BACK_REG_A
GPIO_SOC2LCD_PWREN
LCD_RAMP
EDP_AUX_EMI_CONN_N
EDP_AUX_EMI_CONN_P
EDP_DATA_EMI_CONN_N<1>
EDP_DATA_EMI_CONN_P<2>
EDP_DATA_EMI_CONN_N<2>
EDP_DATA_EMI_CONN_P<3>
EDP_DATA_EMI_CONN_N<3>
EDP_AUX_N
EDP_DATA_EMI_P<0>
EDP_DATA_EMI_N<0>
EDP_DATA_EMI_N<2>
EDP_DATA_P<1>
EDP_DATA_EMI_P<2>
EDP_DATA_EMI_P<3>
EDP_DATA_P<2>
EDP_DATA_N<3>
EDP_DATA_P<3>
PPVCC_MAIN_LCD_SW
EDP_HPDEDP_HPD_2P5EDP_HPD_EMI
PPVCC_MAIN_LCD_SW_CONN
EDP_DATA_EMI_CONN_N<2>
EDP_DATA_EMI_CONN_P<2>
EDP_DATA_EMI_CONN_N<1>
EDP_DATA_EMI_CONN_P<1>
EDP_DATA_EMI_CONN_N<3>EDP_HPD_EMI
EDP_AUX_EMI_CONN_P
EDP_DATA_EMI_CONN_N<0>
EDP_DATA_EMI_CONN_P<0>
EDP_AUX_EMI_CONN_N
EDP_DATA_EMI_CONN_P<3>
LED_IO_5_A
LED_IO_6_A
LED_IO_4_A
LED_IO_2_A
LED_IO_3_A
LED_IO_1_A
PPLED_BACK_REG_A
=PPVCC_MAIN_LCD
GPIO_SOC2LCD_PWREN
NC_U2201_5
GPIO_SOC2LCD_PWREN
GATE2LCD_PWREN
=PP1V8_SOC
EDP_DATA_EMI_N<3>
051-0886
A.0.0
22 OF 121
18 OF 54
2
1
21
2
1
1
2
2
1
9
11
13
15
17
3
7
14
16
18
12
10
8
4
6
2
31
29
19
21
23
25
27
32
30
26
28
24
22
20
5
1
3334
3536
21
2
1
1 2
2
6
1
4
35
2
1
1 2
2
1
1 2
2
1
1
2
2
1
21
4
32
1
1
2
4
32
1
4
32
1
4
32
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
4
32
11 2
2
1
1
2
81
3
52
7
2
1
2
1
53
53
18 52
54 18 52
53
53
53
53
53
18
18
54
4571054
53
OUT
OUT
OUT
IN
IN
IN
VSS
VSS
RESET*
P0_10
P0_9
P0_8
P0_7
P0_4
P0_5
P0_3
P0_2
P0_1
P0_0
DBGEN
P0_20
P0_21
P0_22
P0_18
P0_19
P0_15
P0_17
P0_16
P0_14
P0_12
P0_11
VDDC
VDDIO
VDDC
P0_13
P0_6
OUT
IN
IN
BI
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
RDAR://PROBLEM/12580012
COMPARE SENSOR CONNECTIONS WITH N51, IDENTIFY AND UNDERSTAND DIFFERENCES
REVIEW: N51 HAS OSCAR I2C CONNECTED TO RF CAM I2C
OSCAR CORE = 1.2V HIBERNATE (NEED TO RUN IN S2R) APN 337S4416
NOTE: I2C1 IS ASSUMED TO USE PUSH-PULL INSTEAD OF OPEN-DRAIN
OSCAR
REVIEW:NEED PU ON CS?
RDAR://PROBLEM/12579997
OSCAR VDDIO = 1.8V HIBERNATE (NEED TO WAKE HOST)
28 44 52
28 44 52
21
21
MF
5%
15.0
01005
1/32W
R2405
R2406
MF
1/32W
5%
15.0
01005
21
5
MF
1/32W
0.00
0%
R2450
01005
CRITICAL
WLCSP
U2400
LPC18A1UK-CPA1
0201-1
6.3V
X5R
20%
1.0UF
C2400
X5R
6.3V
1.0UF
20%
0201-1
C2401
5%
100K
R2400
01005
1/32W
MF
5 53
5 53
5
5
48 52
5
548
5
21
21
21
21
21
21
21
21
SENSOR: OSCAR
SYNC_MASTER=J72_MLB_C SYNC_DATE=11/26/2012
GPIO_OSCAR_RESET_L
GPIO_SOC2OSCAR_DBGEN
TP_OSCAR_P0_22
GPIO_SOC2OSCAR_DBGEN_R
SPI_OSCAR_MISO
SPI_OSCAR2ACCEL_CS_L
SPI_OSCAR2GYRO_CS_L
=PP1V2_S2R_OSCAR
UART4_OSCAR2SOC_RXD
I2C1_SOC2OSCAR_SWDCLK_1V8
OSCAR2RADIO_CONTEXT_A
OSCAR2RADIO_CONTEXT_B
SPI_OSCAR_SCLK
SPI_OSCAR_MOSI
I2C1_SOC2OSCAR_SWDIO_1V8
PMU_GPIO_OSCAR2PMU_HOST_WAKE
OSCAR_TIME_SYNC_HOST_INT
SPI_OSCAR2COMPASS_CS_L
COMPASS2OSCAR_INT
ACCEL2OSCAR_INT2
GYRO2OSCAR_INT1
GYRO2OSCAR_INT2
ACCEL2OSCAR_INT1
=PP1V8_S2R_OSCAR
SPI_OSCAR_MOSI_R
=PP1V8_S2R_OSCAR
SPI_OSCAR_SCLK_R
UART4_SOC2OSCAR_TXD
PMU_GPIO_CLK_32K_OSCARNC_ISP0_CAM_REAR_SDA
NC_ISP0_CAM_REAR_SCL
051-0886
A.0.0
24 OF 121
19 OF 54
1 2
1 2
1 2
D6
B1
E4
A2
A3
E1
D4
D5
E2
C5
E6
E5
E3
D2
B6
D1
A6
C3
C4
B4
B5
A5
B3
B2
A1
C1
C2
C6
A4
D3
2
1
2
1
1
2
54 19 54
1954
IN1
IN2
IN4
IN3
OUT1
OUT2
OUT3
OUT4
GND
IN1
IN2
IN4
IN3
OUT1
OUT2
OUT3
OUT4
GND
OUT
IN
BI
IN
BI
OUT
IN
IN
OUT
OUT
OUT
SYM_VER-2
SYM_VER-2
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
ISP1_CAM_FRONT_SHUTDOWN_L
HIGH = TURN ON CAMERA
LOW = SHUT DOWN CAMERA
VGA FRONT CAMERA CONNECTOR
516S0876 RCPT MLB
516S0869 PLUG FLEX
F-ST-SM
503548-1820
CRITICAL
J2601
10%
01005
6.3V
X5R-CERM
1000PF
C2602
X5R
1UF
6.3V
0201
20%
C2601
0201
240OHM-350MA
L2600
C2600
5%
16V
56PF
01005
NP0-C0GSM
XW2600
R2601
1/32W
MF
01005
1%
100K
1208
U2601400MHZ-0.1A-27PF
X5R-CERM
1000PF
01005
10%
6.3V
C2605
0201
20%
6.3V
1UF
X5R
C2604
56PF
C2603
5%
NP0-C0G
16V
01005
6.3V
10%
1000PF
01005
X5R-CERM
C2608
1UF
0201
20%
6.3V
X5R
C2607
5%
16V
56PF
C2606
01005
NP0-C0G
1208
400MHZ-0.1A-27PF
U2600
7 53
0201
240OHM-350MA
L2601
240-OHM-0.2A-0.8-OHM
0201-2
L2602
752
752
752
522
5
522
752
7 53
7 53
7 53
90-OHM-50MA
TCM0605-1
L2610
90-OHM-50MA
TCM0605-1
L2611
150OHM-25%-200MA-0.7DCR
01005
L2660
SYNC_DATE=12/03/2012SYNC_MASTER=J85 MLB_C
CAMERA: FF-ALS CONN & FILTERS
ISP1_CAM_FRONT_SHUTDOWN_L_F
I2C3_SCL_1V8_F
GPIO_ALS_IRQ_L_F
PP1V8_CAM_FRONT_FILT
ISP1_CAM_FRONT_SHUTDOWN_L
I2C3_SCL_1V8
GPIO_ALS_IRQ_L
I2C3_SDA_1V8
ISP1_CAM_FRONT_CLK
ISP1_CAM_FRONT_SDA
ISP1_CAM_FRONT_SCL
=PP3V0_ALS
=PP1V8_CAM_FRONT
ISP1_CAM_FRONT_CLK_F
I2C3_SDA_1V8_F
ISP1_CAM_FRONT_SCL_F
ISP1_CAM_FRONT_SDA_F
=PP2V9_CAM_FRONT
MIPI1C_CAM_FRONT_CLK_FILT_N
MIPI1C_CAM_FRONT_CLK_FILT_P
MIPI1C_CAM_FRONT_DATA_FILT_N<0>
MIPI1C_CAM_FRONT_DATA_FILT_P<0>
GPIO_ALS_IRQ_L_F
I2C3_SCL_1V8_F I2C3_SDA_1V8_F
ISP1_CAM_FRONT_CLK_F_R
ISP1_CAM_FRONT_SHUTDOWN_L_F
ISP1_CAM_FRONT_SDA_F
ISP1_CAM_FRONT_SCL_F
PP2V9_AVDD_CAM_FRONT_FILT
GND_AVDD_CAM_FRONT
PP1V8_CAM_FRONT_FILT
PP3V0_ALS_FILT
ISP1_CAM_FRONT_CLK_F_R ISP1_CAM_FRONT_CLK_F
MIPI1C_CAM_FRONT_DATA_FILT_N<0>
MIPI1C_CAM_FRONT_DATA_FILT_P<0> MIPI1C_CAM_FRONT_DATA_P<0>
MIPI1C_CAM_FRONT_DATA_N<0>
MIPI1C_CAM_FRONT_CLK_FILT_N
MIPI1C_CAM_FRONT_CLK_FILT_P MIPI1C_CAM_FRONT_CLK_P
MIPI1C_CAM_FRONT_CLK_N
NC_U2601_5NC_U2601_1
PP3V0_ALS_FILT
GND_AVDD_CAM_FRONT
VOLTAGE=0V
NET_SPACING_TYPE=GND
MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.15 MM
PP2V9_AVDD_CAM_FRONT_FILT
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
VOLTAGE=2.9V
051-0886
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1920
22
2
1
2
1
21
2
1
1 2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
21
21
4
32
1
4
32
1
21
20
20
20
20
54
54
20
20
20
20
54
2053
2053
2053
2053
20
20 20
20
20
20
20
20
20
20
20
20 20
2053
2053
2053
2053
20
20
20
OUT
IN
IN
IN
IN
OUT
OUT IN
OUT
IN
IN
IN
OUTDRDY
SCL/SK
SDA/SI
VDD
RSV SO
VSS
TST1
TRG
VID
CAD0
CAD1
RST*
CSB*
INT2
DEN
INT1
GND
CS
SDO/SA0
SDA/SDI/SDO
SCL/SPC
VDD_IO
DRDY/
RES2
RES1
RES0
VDD
RES/VDD
CAP
GND
INT2
INT1
RES
RES
RES
CS
RES
RES
SDO/SA0
SCL/SPC
SDA/SDI/SDO
VDD VDD_IO
GND
OUT
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
11V CHARGE PUMP
COMPASS
TO VID WHEN NOT USED
APN 338S1014
TIE CSB* TO VID FOR I2C MODE
GYRO
ACCELEROMETER
MF
1/32W
01005
0.00
0%
R2727
19
0%
0.00
MF
1/32W
01005
R2757
19 21
19 21
C2701
20%
6.3V
01005
0.1UF
X5R-CERM
C2700
CERM-X5R
6.3V
20%
10UF
0402-2
19 21
120-OHM-25%-250MA-0.5DCR
01005
L2700
19
19
19
20%
6.3V
C2725
0.1UF
X5R-CERM
010050402-2
10UF
CERM-X5R
6.3V
20%
C2723
19 21
20%
6.3V
C2721
0.1UF
X5R-CERM
01005
01005
120-OHM-25%-250MA-0.5DCR
L2702
19 21
01005
MF
1/32W
15.0
5%
R2747
01005
L2741
120-OHM-25%-250MA-0.5DCR
19 21
19 21
C2726
0.1UF
0201
10%
16V
X5R-CERM
OMIT
19
19
C2711
6.3V
01005
20%
X5R-CERM
0.1UF
C2710
6.3V
20%
X5R
0201-1
1.0UF
XW2700
SHORT-10L-0.25MM-SM
CSP
U2710
AK8963C
CRITICAL
01005
120-OHM-25%-250MA-0.5DCR
L2701
CKPLUS_WAIVE=PWRTERM2GND
CRITICAL
AP3GDL20HAB18TR
U2720
LGA
OMIT
MF
1/32W
0.00
0%
R2750
01005
SHORT-10L-0.25MM-SM
XW2701
X5R-CERM
0.1UF
01005
6.3V
20%
C2750
OMIT
AP2DHAB26TR
CRITICAL
U2700
LGA
19
19
SYNC_DATE=N/ASYNC_MASTER=N/A
SENSOR: ACCEL, COMPASS, GYRO
NO_TEST=TRUENC_COMPASS_TST1
GND_COMP
GYRO_DEN SPI_OSCAR_MISO_GYRO
PP3V0_COMP
GYRO_RES_VDD
GYRO2OSCAR_INT1
SPI_OSCAR2GYRO_CS_L
SPI_OSCAR_MOSI
SPI_OSCAR_SCLK
=PP1V8_S2R_GYRO
GYRO2OSCAR_INT2
PP3V0_GYRO
GYRO_PUMP
SPI_OSCAR_MISO
=PP3V0_S2R_ACCEL
SPI_OSCAR_MISO
=PP3V0_S2R_GYRO
=PP3V0_S2R_COMP
SPI_OSCAR2COMPASS_CS_L
PP1V8_COMP
NO_TEST=TRUENC_COMPASS_TRG
SPI_OSCAR_MISO_COMP1NC_COMPASS_RSV NO_TEST=TRUE
SPI_OSCAR_MOSI
SPI_OSCAR_SCLK
COMPASS2OSCAR_INT
=PP1V8_S2R_COMP
SPI_OSCAR_MISO
PP1V8_COMP
GND_COMP GND_COMP
=PP1V8_S2R_ACCELPP3V0_ACCEL
SPI_OSCAR_MOSI
SPI_OSCAR_SCLK
SPI_OSCAR_MISO_ACCEL
SPI_OSCAR2ACCEL_CS_L
ACCEL2OSCAR_INT2
ACCEL2OSCAR_INT1
051-0886
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1 2
2
1
2
1
21
2
1
2
1
2
1
21
1 2
21
2
1
2
1
2
1
21
A1
A3
A4
B1
B3 B4
C1
C2
C3
C4
D1
D2
D4
A2
21
8
7
13
5
4
3
2
1
6
11
10
9
16
15
14
12
1
2
2
1
5
6
13
14
12
4
11
10
3
1
2
8
7
9
21
54
19 21
54
19 21
54
54
21
5421
21
21
54
ADD0
SCLK
CIN1
CIN3
CIN4
CIN12
CIN11
CIN6
CIN9
CIN8
CIN10
CIN2
CIN5
CIN0
ACSHIELD
GND
BIAS
SDA
VDRIVEVCC
ADD1
INT*
GPIO
CIN7
TPNC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BI
IN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
516S0872
PROX SENSOR
CHOSE CIN NUMBERS FOR LAYOUT EASE
PCB: ENSURE ACSHIELD PLANE UNDER
VDRIVERAIL
READ: 0X59, WRITE: 0X58
353S2964
CONNECTED TO MLB INTERCONNECT.
THEREFORE,PROX GPIO IS NOT
PROX GPIO WILL NOT BE USED.
INT IS 1.8V LEVEL.
1.8 MA MAX
0.5 PF
REF CAP TO MEASURE
NEED EXTERNAL
JUST IN CASE
U3200, NO GND PLANE NEAR PROX_CIN NETS..
INT* IS OPEN DRAIN PU RAIL MATCH VDRIVE
VDRIVE FOR: I2C AND GPIO
CIN9 SENSOR ELECTRODE
CIN7 DUMMY
AND ALSO TIE TO CONNECTOR.
A PLANE UNDER PROX_CIN NETS
PCB: ACSHIELD NEEDS TO BE
I2C ADDRESS: 0101100+R/W
PROX
C2804
6.3V
0.1UF
X5R-CERM
20%
01005
PROX
C2805
68PF
5%
6.3V
NP0-C0G
01005
PROX
R2800
MF
2.0K
1/32W
1%
01005
PROX
R2801
MF
100K
1%
1/32W
01005
PROX
0201
0.01UF
C2802
10%
10V
X5R-CERM
PROX
C2800
X5R
402
10%
6.3V
2.2UF
PROX
C2803
+/-0.05PF
201
CERM
25V
0.5PF
PROX
C2801
0.1UF
6.3V
X5R-CERM
20%
01005
PROX
C2806
5%
68PF
6.3V
NP0-C0G
01005
PROX
C2807
NP0-C0G
201
25V
27PF
1%
PROX
U2800
WLCSP
AD7149
CRITICAL
PROX
L2801
68NH-2%-320MA-1.0OHM
0402
CRITICAL
PROX
CRITICAL
L2807
68NH-2%-320MA-1.0OHM
0402
PROX
CRITICAL
0603
L2808
390NH-2%-170MA-4.0OHM
PROX
0603
L2802
CRITICAL
390NH-2%-170MA-4.0OHM
PROX
L2803
68NH-2%-320MA-1.0OHM
0402
CRITICAL
PROX
0603
L2804
CRITICAL
390NH-2%-170MA-4.0OHM
520
PROX
0201-2
240-OHM-0.2A-0.8-OHM
L2800
520
PROX
J2800
503548-0620
CRITICAL
F-ST-SM
5
SENSOR: PROX
SYNC_MASTER=J85 MLB_C SYNC_DATE=12/05/12
ACSHIELD_SB
NC_J2800_6
NC_J2800_2
NC_J2800_4
PROX_CIN9_CONN
PROX_ACSHIELD_CONN
=PP1V8_PROX
PP3V0_SENSOR_PROX_FILT
I2C3_SCL_1V8
PROX_GPIO PROX_CIN9
CIN9
ACSH_SB
PROX_CIN1
TP_PROX_CIN2
PROX_CIN7 CIN7
GPIO_PROX_IRQ_L
=PP3V0_PROX
I2C3_SDA_1V8
PROX_CIN7_CONN
PROX_BIAS
=PP1V8_PROX
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2
1
2
1
2
1
D1
C1
A3
A4
C3
E5
D5
B4
C5
C4
D4
B3
A5
D3
E4
E2
E3
E1
C2
D2
B1
A1
A2
B5
B2
2 1
2 12 1
2 1
2 12 1
2 1
8
21
109
3 4
5 6
7
2254
54
2254
BI
IN
IN
SYM_VER-2
SYM_VER-2
SYM_VER-2
OUT
OUT
OUT
OUT
OUT
OUT
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
REAR CAMERA CONNECTOR
APN: 516S0973
PLUG: 516S0974
X5R-CERM
10%
01005
6.3V
1000PF
C2902C2901
402
1UF
10%
10V
X5R
5%
16V
C2900
56PF
01005
NP0-C0G
L2900
240OHM-350MA
0201
752
6.3V
X5R-CERM
10%
1000PF
01005
C2905C2904
10%
402
1UF
10V
X5R
16V
5%
56PF
NP0-C0G
01005
C2903
240OHM-350MA
0201
L2901
C2908
10%
01005
X5R-CERM
6.3V
1000PF
C2907
X5R
10V
1UF
402
10%5%
16V
56PF
NP0-C0G
C2906
01005
240OHM-350MA
0201
L2902
10%
C2911
X5R-CERM
6.3V
1000PF
01005
1UF
10V
402
10%
X5R
C2910
16V
5%
56PF
NP0-C0G
01005
C2909
240OHM-350MA
0201
L2903
752
C2970
5%
56PF
NP0-C0G
16V
01005
5%
16V
56PF
01005
NP0-C0G
C2971
16V
5%
NP0-C0G
C2972
56PF
01005
C2973
16V
5%
NP0-C0G
56PF
01005
F-ST-SM
AA07-S022VA1
J2950
CRITICAL
7 52
90-OHM-50MA
TCM0605-1
L2910
TCM0605-1
L2911
90-OHM-50MA
90-OHM-50MA
TCM0605-1
L2912
7 53
7 53
7 53
7 53
7 53
7 53
XW2950SM
XW2951SM
150OHM-25%-200MA-0.7DCR
01005
L2950
752
1000PF
6.3V
01005
10%
X5R-CERM
C2980R2950
01005
1/32W
MF
100K
1%
CAMERA: REAR CONN & FILTERS
SYNC_MASTER=N/A SYNC_DATE=N/A
=PP2V9_CAM_REAR
CAM_REAR_VSYNC
VOLTAGE=2.9V
PP2V9_AVDD_CAM_REAR_FILT
MIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.6 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=5 MM
NET_SPACING_TYPE=GND
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
GND_CAM_AVDD
=PP1V3_CAM_REAR
=PP2V6_CAM_REAR_AF
=PP1V8_CAM_REAR
ISP0_CAM_REAR_CLK_F
MIPI0C_CAM_REAR_CLK_FILT_P
MIPI0C_CAM_REAR_DATA_FILT_P<0>
MIPI0C_CAM_REAR_DATA_FILT_N<0>
MIPI0C_CAM_REAR_DATA_FILT_P<1>
MIPI0C_CAM_REAR_CLK_FILT_N
MIPI0C_CAM_REAR_DATA_FILT_N<1>
ISP0_CAM_REAR_CLK
MIPI0C_CAM_REAR_DATA_N<0>
MIPI0C_CAM_REAR_DATA_P<0>
MIPI0C_CAM_REAR_CLK_N
MIPI0C_CAM_REAR_CLK_P
MIPI0C_CAM_REAR_DATA_N<1>
MIPI0C_CAM_REAR_DATA_P<1>
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP2V6_CAM_REAR_AF_FILT
VOLTAGE=2.6V
GND_AF_AVDD
MAX_NECK_LENGTH=5 MM
NET_SPACING_TYPE=GND
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
PP1V8_CAM_REAR_FILT
ISP0_CAM_REAR_SDA
ISP0_CAM_REAR_SCL
ISP0_CAM_REAR_SHUTDOWN_L
PP1V3_CAM_REAR_FILT
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21
2
1
2
1
2
1
21
2
1
2
1
2
1
21
2
1
2
1
2
1
2
1
25
26
24
23
22
20
18
16
10
14
12
8
6
4
2
21
19
17
15
7
9
11
13
5
3
1
4
32
1
4
32
1
4
32
1
1 2
1 2
21
2
1
1
254
54
54
54
53
53
53
53
53
53
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
BI
BI
IN
OUT
IN
IN
IN
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
IN
IN
OUT
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
GPIO53/BOOT_CONFIG_1
SIM CARD ESD PROTECTION
48
PROBE POINTS
GPIO48/BOOT_CONFIG_6
DEBUG CONNECTOR
BOOT_HSIC_OPTION
BOOT_NAND_OPTION
SW REGISTER
GPIO53/BOOT_CONFIG_1
GPIO48/BOOT_CONFIG_6
ENABLE SAHARA PROTOCOL
BOOT_USB_OPTION 0X03
BOOT_DEFAULT_OPTION
BOOT OPTIONS
0X00
0X01
0X08
47
X
0X02
VALUE
X
X
X
6
GPIO/BOOT_CONFIG CONFIGURATION
0
1
1
1
1
0 0 1 0 X X X
0
0
0
0
000
0
0
5
49
0
34
0
50
0
51
1
0
100
1
10
0
52
2
53
0
54
0
1 0
X
X
X
X
55
0
BOOT_CONFIG
X
AP INTERFACE & DEBUG CONNECTORS
GPIO51/BOOT_CONFIG_3
GPIO54/BOOT_CONFIG_0
SM
P4MM
PP3002
P4MM
SM
PP3001
SM
P4MM
PP3000
NOSTUFF
F-ST-SM
MM4829-2702
J3001
NOSTUFF
F-ST-SM
MM4829-2702
J3002
P4MM
SM
PP3009
SM
P4MM
PP3008
SM
P4MM
PP3010
P4MM
SM
PP3011
SM
P4MM
PP3012
SM
P4MM
PP3013
SM
P4MM
PP3003
NOSTUFF
10K
MF
01005
5%
1/32W
R3002
NOSTUFF
5%
10K
1/32W
MF
01005
R3003
28
2428333940
284852
283940
14242852
2752
52752
52752
52752
52752
52752
2752
27
27
2627
264852
NOSTUFF
M-ST-SM
AXE654124
J3003
5 28
5 28
5 28
27 48 52
5 28
5 28
5 11 28 52
28
5 11 28 52
4 8
10
11 48 52
52652
2652
25 33 34 35 36 37 38 54
24 25 27 28 30 52
5 26 52
115253
NOSTUFF
SHORT-10L-0.25MM-SM
XW3002
NOSTUFF
SHORT-10L-0.25MM-SM
XW3003
115253
CELL
12V-33PF01005-1
C3000
CELL
ESD0P2RF-02LS
TSSLP-2-1
U3001
CELL
TSSLP-2-1
ESD0P2RF-02LS
U3000
CELL
TSSLP-2-1
ESD0P2RF-02LS
U3003
CELL
TSSLP-2-1
ESD0P2RF-02LS
U3002
CELL:AP INTERFACE & DEBUG CONNECTORS
UART3_BB2SOC_RTS_L
PMU_GPIO_BB_VBUS_DET
PMU_GPIO_BB2PMU_HOST_WAKE
GPIO_51
ANT_SEL_1
ANT_SEL_2
LAT_SW1_CTL
BB_JTAG_RTCLK
BB_JTAG_TDI
BB_JTAG_TDO
BB_JTAG_TCK
BB_JTAG_TRST_L
BB_JTAG_TMS
DEBUG_RST_L
USB_BB_DEBUG_P
USB_BB_DEBUG_N
PMIC_RESOUT_L
PMU_GPIO_PMU2BBPMU_RST_L
HSIC2_SOC2BB_HOST_RDY
GPIO_BB2SOC_RESET_DET_L
HSIC2_BB2SOC_DEVICE_RDY
UART3_SOC2BB_RTS_L
UART3_SOC2BB_TX
UART3_BB2SOC_TX
RESET_SOC_L CKPLUS_WAIVE=SINGLE_NODENET
GPIO_SOC2BB_RADIO_ON_L
PS_HOLD_PMIC
=PPBATT_VCC_BB
PP_SMPS3_MSME_1V8
GPIO_SOC2BB_RST_L
USB_BB_N
USB_BB_P
GPIO_DEBUG_LED
SIM_TRAY_DETECT
SIMCRD_CLK_CONN
SIMCRD_IO_CONN
SIMCRD_RST_CONN
PP_LDO6_RUIM_1V8
UART_BB2WLAN_LTE_COEX
SLEEP_CLK_32K
WTR_SSBI_PRX_DRX
WTR_RF_ON
19P2M_MDM
PMIC_SSBI
BB_ERROR_FLAG
LAT_SW1_CTL
PP_SMPS3_MSME_1V8
WTR_SSBI_TX_GPS
WTR_RX_ON
HSIC2_BB_DATA
HSIC2_BB_STB
UART_WLAN2BB_LTE_COEX
ANT_SEL_1
051-0886
A.0.0
30 OF 121
24 OF 54
1
1
1
4
2
3
1
4
2
3
1
1
1
1
1
1
1
1
1
2
1
2
50
42
44
46
48
32
34
36
38
40
26
22
24
28
30
16
14
12
18
20
2
10
8
6
4
49
47
45
43
41
33
31
29
27
25
23
21
35
37
39
7
5
3
1
19
17
15
9
11
13
52
54
51
53
55
58 57
56
21
21
1
2
21
21
2 1
2 1 10 28 52
10 28 52
102852
102852
10 25 27 52
28 44
26 27
28 29
28 29
26 27
26 27
28
14242852
24 25 27 28 30 52
28 29
28 29
4 27 53
4 27 53
28 44
2428333940
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
VDD_S4
VSW_S5
VSW_S3
VSW_S2
VREG_XO
VREG_S5
VREG_S4
VREG_RFCLK
VREG_L9
VREG_L8
VREG_L7
VREG_L6
VREG_L5
VREG_L4
VREG_L3
VREG_L2
VREG_L14
VREG_L13
VREG_L12
VREG_L11
VREG_L10
VOUT_LVS1
VDD_XO
VDD_S5
VDD_S2
VDD_S1
VDD_L9
VDD_L8
VDD_L7
VDD_L5_L6_L13_L14
VDD_L4
VDD_L2_L3
VDD_L12
VDD_L10_L11
REF_GND
REF_BYP
VSW_S5_2
VREG_S3
VSW_S4
VDD_S3
VSW_S1
VREG_S1
VREG_S2
VREG
(SYM 5 OF 5)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
INTERNAL USE ONLY
INTERNAL USE ONLY
PMU (1 OF 2)
2433343536373854
4.7UF
20%
0402
10V
X5R-CERM
C3204
X5R-CERM
0402
10V
20%
4.7UF
C3205
4.7UF
20%
10V
0402
X5R-CERM
C3206
X5R-CERM
4.7UF
10V
20%
0402
C3207
0402
X5R-CERM
10V
20%
4.7UF
C3208
SHORT-10L-0.1MM-SM
XW3200 X5R-CERM
6.3V
20%
0.1UF
01005
C3209
41
27
0402-2
20%
6.3V
CERM-X5R
10UF
C3200
26 27
2.2UH-20%-2.34A-0.113OHM
2520-SM
CRITICAL
L3204
2.2UH-20%-1.2A-0.15OHM
0806
CRITICAL
L3203
22UF
6.3V
X5R-CERM-1
603
20%
C3224
22UF
20%
6.3V
X5R-CERM-1
603
C3225
2.2UH-20%-1.2A-0.15OHM
CRITICAL
0806
L3202
0806
2.2UH-20%-1.2A-0.15OHM
CRITICAL
L3201
X5R-CERM-1
22UF
603
20%
6.3V
C3226
22UF
X5R-CERM-1
603
20%
6.3V
C3228
X5R-CERM-1
603
20%
22UF
6.3V
C3229
25 52
27
25 30 52
NOSTUFF
4V
X5R
01005
20%
0.1UF
C3227
24 25 27 28 30 52
27 30
0806
2.2UH-20%-1.2A-0.15OHM
CRITICAL
L3200
1.0UF
6.3V
X5R
20%
0201-1
C3230
27 52
27
2552
253052
242527283052
BGA
PM8018-0
CRITICAL
U3300
27
27
27
27
0402-2
6.3V
CERM-X5R
20%
10UF
C3201
27
27
14 32 33 39 40
27
10 24 27 52
6.3V
X5R
1.0UF
20%
0201-1
C3210
6.3V
20%
X5R
1.0UF
0201-1
C3212
1.0UF
X5R
20%
6.3V
0201-1
C3214
20%
6.3V
X5R
1.0UF
0201-1
C3217
X5R
20%
6.3V
1.0UF
0201-1
C3211
1.0UF
X5R
6.3V
20%
0201-1
C3213
6.3V
20%
X5R
1.0UF
0201-1
C3215
20%
X5R
1.0UF
6.3V
0201-1
C3216
0402-2
CERM-X5R
20%
6.3V
10UF
C3202
1.0UF
X5R
6.3V
20%
0201-1
C3219
10UF
0402-2
CERM-X5R
20%
6.3V
C3221
0402-2
CERM-X5R
10UF
6.3V
20%
C3223
0402-2
6.3V
20%
10UF
CERM-X5R
C3218
0402-2
CERM-X5R
10UF
6.3V
20%
C3220
10UF
20%
6.3V
CERM-X5R
0402-2
C3222
1.0UF
6.3V
X5R
20%
0201-1
C3231
01005
5%
56PF
NP0-C0G
16V
C3203
CELL: BASEBAND PMU (1 0F 2)
S1_GND S2_GND S3_GND S4_GND S5_GND
PP_LDO4_VDDA_3V3
PP_LDO5_GPS_LNA_2V5
PP_LDO1
REF_BYP
PP_LDO3_AMUX_1V8
PP_LDO2_XO_HS_1V8
S5_GND
PP_SMPS5_DSP_1V05
S4_GND
S3_GND
S2_GND
S1_GND
PP_LVS1
PP_VREG
PP_SMPS4_RF2_2V05
PP_SMPS3_MSME_1V8
PP_SMPS5_DSP_1V05
PP_LDO6_RUIM_1V8
PP_LDO14_2V65
PP_LDO13_VDDPX_2V95
PP_LDO7_DAC_1V8
PP_LDO8_VDDPX_1V2
PP_LDO12_MDSP_SW_1V05
PP_LDO9_PLL_1V05
PP_LDO11_MDSP_FW_1V05
PP_LDO10_ADSP_1V05
PP_SMPS1_MSMC_1V05
PP_VSW_S1
REF_GND
PP_VSW_S2
PP_SMPS2_RF1_1V3
PP_VSW_S3
=PPBATT_VCC_BB
PP_SMPS4_RF2_2V05
PP_SMPS3_MSME_1V8
PP_VSW_S5
PP_VSW_S4
051-0886
A.0.0
32 OF 121
25 OF 54
2
1
2
1
2
1
2
1
2
1
21
2
1
2
1
1 2
21
2
1
2
1
21
21
2
1
2
1
2
1
2
1
21
2
1
98
24
88
82
87
48
42
90
20
76
105
13
77
54
63
17
11
84
32
31
29
23
43
55
65
53
8
101
89
95
104
70
58
75
5
78
44
64
59
34
28
100
12
81
18
6
92
97
79
83
1022
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
25
26
25
26
25
26
25
26
25
26
52
25 26
25 26
25 26
25 26
25 26
IN
OUT
MPP_06
MPP_05
MPP_04
MPP_03
MPP_02
MPP_01
GPIO_06
GPIO_05
GPIO_04
GPIO_03
GPIO_02
GPIO_01
(SYM 4 OF 5)
MPP MISC
NC
NC
NC
NC
NC
NC
NC
NC
BI
IN
IN
IN
IN
GND_S3
GND_S2
GND_S1
GND_S4
GND_S5
GND
VCOIN
(SYM 3 OF 5)
INPUT PWR
NC
OPT_1
PM_RESIN_N
KPD_PWR*
BAT_ID
LED_DRV_N
OPT_2
PM_MDM_INT_N
PM_USR_INT_N
PON_RESET*
PON_TRIG
SSBI
PS_HOLD
(SYM 1 OF 5)
CONTROL
NC
NC
OUT
OUT
NC
OUT
IN
NC
NC
OUT
IN
OUT
OUT
GND0
XTAL_32K_OUT
XTAL_32K_IN
XTAL_19M_OUT
XTAL_19M_IN
XOADC_GND
XO_THERM
XO_OUT_D0_EN
XO_OUT_D0
XO_OUT_A1
XO_OUT_A0
SLEEP_CLK
RSVD
GND1
(SYM 2 OF 5)
CLOCKS
IN
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PMU (2 OF 2)
1 (1.8V)
0 (NC, PD)
BB GPIO_29
JXX
NXX
BOARD_ID
1.3V
1.1V
PRODUCT_ID
PROTO1
PA_ID
0.3V
0.5V
1.1V
7.5
7.6
7.7
8.7
8.6
8.5
TO MINIMIZE THERMAL DRIFT
GND NEEDS TO BE CLEARED UNDER THIS CRYSTAL
1.3V
0.1V
AP SECTION NEEDS ITS OWN THERMISTOR PLACED NEAR THE PA’S.
PVT
DVT
PROTO2 PROTO2
MAV VER
1.7V
1.5V
EVT2
EVT1
0.7V
0.9V
REVISION
1.5V1.5V
28
27
BGA
CRITICAL
PM8018-0
U3300
1%
MF
01005
1/32W
100K
R3304
1/32W
100K
MF
1%
01005
R3305
2427
52452
28
244852
52452
20.0K
5%
01005
MF
1/32W
R3301
1.00K
1/32W
01005
5%
MF
R3300
PM8018-0
BGA
U3300
SM
XW3304
SHORT-10L-0.25MM-SM
XW3303
SM
XW3302
SHORT-10L-0.25MM-SM
XW3301
SM
XW3300
PM8018-0
BGA
U3300
28
28
24 27
252627
19.200MHZ
2.0X1.6-SM
CRITICAL
Y3300
24 27
27
24 27
29
SHORT-10L-0.1MM-SM
XW3305
100K
MF
1/32W
1%
01005
R3303
X5R-CERM
01005
10%
6.3V
1000PF
C3300
PM8018-0
BGA
U3300
MF
1/32W
1%
499K
01005
R3307
1%
MF
1/32W
01005
100K
R3306
252627
CELL: BASEBAND PMU (2 OF 2)
VREF_DAC_BIAS
VDDPX_BIAS
GPIO_SOC2BB_RST_L
S3_GND
S4_GND
S5_GND
S1_GND
S2_GND
PMIC_SSBI
PS_HOLD_PMIC
PMU_GPIO_PMU2BBPMU_RST_L
GPIO_SOC2BB_RADIO_ON_L
PM_USR_IRQ_L
PM_MDM_IRQ_L
PMIC_RESOUT_L
PP_LDO3_AMUX_1V8
19P2M_XTAL_OUT
19P2M_MDM
19P2M_CLK_EN
SLEEP_CLK_32K
19P2M_XTAL_IN
19P2M_WTR
XO_THERM_Y1
XO_GND
PS_HOLD
BOARD_ID PA_ID
PP_LDO3_AMUX_1V8
051-0886
A.0.0
33 OF 121
26 OF 54
80
73
72
66
67
85
49
71
60
50
38
33
1
2
1
2
1 2
1 2
56
30
96
103
91
36
93
99
94
39
51
61
46
52
40
57
1 2
21
1 2
21
1 2
62
16
69
35
86
74
14
21
4
41
68
47
3
24
1
2
1
1
2
2
1
27
15
3
2
1
22
10
9
25
37
19
26
7
45
1
2
1
2
25
25
25
25
25
2452
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram
I pad mini 2 full  schematic Diagram

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  • 1. R2040 R2050 U2720 L2050 L2040 C8190 C8140 C8141 L5700 L8229 DZ5700 R8100 C8149 DZ5703 DZ5704DZ5702 U1400 DZ8120 D8230 D8228 D8100 L2201 DZ5710 Q8104 Q8123 XW1902 XW1903 XW1900 C1026 C1004 C1405 C1007 C1404 C8210 U8550 L8103 L8100 L8104 L8106 L8105 L8102 L8101 L8111 L8108 L8107 L8109 U8100 L8110 C8145 Y8200 U1700 U2200 U0652 Y0602 C2800 C5701 C8233 C8237 C8307 C8139 C8201 C8136 C8200 C8203 C8230 DZ2963 DZ2961 DZ2962 DZ2960 J2201 J1700 D5700D5702D5701D5703 U3000 U3001 U3002 U3003 J7500 C3432 C4235 C4100 C4101 C4232 C4322 C4323 R8323 R8324 R8321 R8322 R8327 L2962 L2961 L2960 L2963 L2901 L2900 L1800 L2602 L2800 L2903 L2902 L1920 L2601 L2600 L1700 L1701 L1702 FL7500 L4440 C1912 C1908 C1906 C1905 C1950 C1907 C1901 C1070 C2907C2910C2901C2904 C1701 C1361 C8235 C2047 C2048 C1909 C2058 C2053 C2052 C2041 C2042 C2057 C2043 C8150 C8172 C8171 C8160 C81A2 C81A1 C81A7 C8161C8158C8184C8182C8180C8178C8175C8157C81A3C81A0C81A5C81A6 C2051 C1910 C8193 C8194 C5800 C5801 C3205 C3208 C3206 C3207 C3204 C2202 C2241 C8239 C8290 C8238 C8231 C8226 C8169 C8241 C8155 C8211 C8240 C8232 C8163 C8164 C8153 C8187 C8186 C8185C8183C8181C8179C8177C8176C81A4 C8170 C8162 C8151 C8154 C8168 C8156 C8167 C8166 C8152 C8234 C8188 C8159 C8165 C4507 C4485 R1901 R1951 R1950 R1952 R2051R2041 R5700 R5 82 0 R5 81 0 R5 83 0 R8130 R8116 R8173 R8399 R8303 R4739 R4607 R4139 R4608 R4437 R1953 R1931 R1930 L4801 R4801 R8172 R8146 R8170 R3702 C4058 C4049 L3817 C4048 L3821 R4 60 5 R4701 L4747 L4746 R0770 R0765 R1207 R1454 R1260 R0870 R2450 R0753 R0752 R0871 R2727 R0832 R2750 R0617 R1250 R0705 R0704 R1211 R0703 R0702 R1052 R1051 R1000 R0738 R1940 R0646 R1920 R2757 R2405 R0831 R0655 R0720 R2400 R2406 R2747 R0640 R1461 R1912 R1913 R1910 R1911 R1460 R2902 R2901 R2900 R2903 R0721 R1209 R1208 R0739 R1213 R8352 R1006 R1005 R1001 R0751 R1205 R1206 R0933 R0930 R0941 R0940 R1201 R0701 R0931 R0750 R2801 R2601 R1850 R2800 R2241 R5790 R5791 R1790 R2243 R1753 R1752 R2242 R2250 R8240 R8231 R8232 R8235 R8239 R8227 R5706R5705 R0736 R5802 R5800 R5801 R5804 R5803 R3401 R8330 R3307R3305 R3306 R3304 R3301 R3300 R3530R3531 R4500 R3002 R3003 R3502 R3402 R3403 R3400 R3303 R1751 R2205 R2290 R3000 R2291 R0651 R0771 R1370 R8411 R8435 R8410 R8445 R8450 R8451 R8430 R8420 R8425 R0735 R5805 R4534 R3604 C3905 C3904 C3914 C3913 C3903 R3600 C4146 C3910 R3602 L4029 R3603 R3601 L4012 R4064 L4044 L4030 R4065 L4070 R4300 L4435 L4802 L4803 L1900 L1901 L1902 L1903 L5702 L5701 C5824 C5 82 1 C5814 L5811 C5811 L4765 L3814 L3815 L3813 L3806 L3805 L3804 C3808 L4257 C3810 L4317 L4138 L4097 C4320 L4439 L4136 L4438L4437 L4 61 3 R3700 C4807 L4743 C4799 C3809 L4200 L4701 C4708 C4064 C4056 L3820 L2741 L2702 L2700 L2701 L2660 L2950 L1904 L1905 L1760 L2240 L3520 FL4802 C1411 C1402 C1401 C1400 C2094 C1410 C1412 C1480 C8109 C1116 C2095 C8110 C8105 C2090 C2091 C8131 C8101 C8356 C1115 C8111 C8108 C8117 C8120 C8114C8116 C8112 C1170 C1171 C8115 C8118 C8113 C8119 C8100C8106 C8107 C8102C8103 C8104 C8132 C8130 C2723 C2700 C5880 C5882 C5881 C3222 C3200 C3201 C3202 C3220 C3221 C3223 C3218 C3001 C1753 C8127 C8123 C8122 C8121 C8124 C8126 C8125 C8550 C8128 C8129 C3715 C3701 C4504 C1103 C1148 C1027 C1015 C1009 C1100 C1102 C1101 C1122 C1117 C1119 C1118 C1120 C1121 C1174 C1176 C1172 C1173 C1177 C1175 SL9303 SL9304 SL9300 SL9305 C2962 C2726 C2046 C1914 C1904 C1920 C1932 C1930 C1913 C2963 C1931 C2961 C2960 C2056 C2054 C2093 C2044C2092 C8350 C8352 C9000 C1903 C2803 C2802 C2807 C1801 C4801 C4802 C5704 C1702 C1705 C1708 C7524 C5700 C8285 C8281 C8282 C8283 C8284 C8280 C2233 C2221 C5823 C5825 C5 82 2 C5 82 6 C5820 C5827 C5815 C5813 C5816 C5 81 0 C5817 C5703C5702 C1751 C1750 C2240C8143 C8216 C8142 C8146 C2203 C1302 C2239 C2230 C8259 C8196 C8305 C8306 C8215 C8242 C1917 C1916 C4047 C4060 C4063 L4228 L4229 C4155 L4642 C4151 C4150 C4154 C3434 L4807 C4803 C4208 C4794 R4711 L4072 L4316 L4071 C1406 C2400 C2710 C1911 C1951 C2401 C1407 C2607 C2604 C2601 C1704 C1707 C3417C3405 C3407 C3422 C3433 C1413C1450 C3230 C3210 C3211 C3212 C3213 C3416C3408 C3418 C3419 C3420 C3406 C3410 C3411 C3415 C3404 C3424 C3425 C3401 C3403 C3421 C3400 C3402 C3412 C3409 C3414 C3413 C3426 C3219 C3214 C3217 C3215 C3216 C3431 C8308 C8144 C1360 C1752 C1303 C81A9 C8138 C8137 C8135 C81A8 C8355 C3700 C4002 C4230 C4149 C4487 C4319 C3231 C2045 C2055 C3228 C3224 C3226C3225 C3229 C8250 C8252 C8253 C8254 C8148 C8147 C8251 C8212 C1490C1493 C0618 C1052 C1915 C1902 C1494C0607 C0613 C1461 C1991 C1990 C1491 C1460 C1002 C2725 C2721 C2711 C2701 C2750 C2900 C2905 C2903 C2971 C2805 C2804 C2908 C2970 C2603 C2806 C1822 C1802 C1830 C1820C1821 C1800 C1850 C2608 C2606 C2801 C2911 C2909C2973 C2906C2972 C2980 C2902 C2605 C2602 C2600 C1700 C2249 C2248 C2247 C2246 C1703 C2245 C2244 C1760 C1706 C2251 C2243 C2242 C2250 C1761 C7526 C7523 C7525 C7522 C2260 C2232 C5705 C5707 C3002 C3423 C3520 C1492 C3300 C3227 C3500 C4500 C3203 C3209 C2270 C1321 C8301 C1301 C1320 C1300 C1322 C8400 C8310 C8555 C8460 C3600 C3720 C3718 C3717 C3601 C3704 C3703 C3702 C3714 C3713 C3712 C3705 C3711 C3710 C4797 C4545C3719 C3708 C3707 C3709 C4798 C4739 C4738 C4737 C4736 C4710 C3902 C3706 C3906 C3716 C3908 C3909 C3721 C3801 C3911 C3804 C3803 C3800 C3807 C3806 C4502 C4503C4148 C3912C3805C3802 C4508 C3602 C4008 C4227 C4228 C4229 C4219C4218 C4038 C4042 C4054 C4023 C4076 C4075 C4072 C4012 C4039 C3811 C4052 C4147 C4053 C4074 C4073 C4001 C4043 C4041 C4669C4668 C4034C4033 C4055 C4664 C4663 C4639 C4666 C4665 C4622 C4317 C4316 C4641 C4489 C4318 C4486 C4483 C4471 C4484 C4488 C4472 C4467 C4805 C4804 C4809 C4234 C4233 C4207 C4104 C4102 C4103 C4324C4325 C4326 C4327 C4239 L4045 C4231 L4020 J5820 J5810 U2201 U2710 U8350 J2960 J4800 J4910 XW5897 XW5891 XW5890 XW5892 XW5896 XW5895 XW5894 XW5893 XW3301 XW3303 XW3200 XW3305 XW8410 PP9406 PP9416 PP9417 PP9419 PP9420 PP9421 PP9422 PP9423 PP9424 PP9425 PP9403 PP9468PP9469 PP9471 PP9472 PP9482PP9483 FL4801 J1800 U2601 U2600 J2601 J4802 J2800 J2950 U2800 L2801 L2803 L2807 XW2700 L2808 L2802 L2804 MH9300 XW2701 XW3002 XW3003 SP* SSSPPP*** U8400 Q8440 XW2051 XW2050 XW2951 XW2950 XW2600 XW7520 U2400 XW8114 X W 8 1 0 2 X W 8 1 0 1 XW8106 XW2041 XW2040 XW8103 X W 8 1 0 7 XW8104 XW8105 L5 81 0 L4083 L4806 L4805 L4804 C4071 L3809 L3808 C4046 C4061 L3204 Y3300 XW3304 XW3302 XW3300 U3520 L3201 L3202L3203 L3200 STD9302 J3000 L2212L2242L2232L2202L2222 U5820 L2200 L5703 L2911L2910L2912 L2610L2611 L5704 U1900 U3400 U3300 U5810 MH9302 STD9301 STD9300 L4740 C4756 C4755 L4742 L3903 L3902 L3909 C3901 L3901 L3906 L3824 L3822 L3908 L3907 L3905 L3904 L3823 L4122 L4182 L4254 L4253 C4216 L4123 L4314L4315 L4436 L3807 L3811 L3812 L3810 C4037 C4040 R3901 C3907 L3819 U4722 U4500 U3803 FL4211 U4215 U4358 U4027 U4617 U4410 U4714 U4000 U3801 SW4601 U3802 FL4012 L4500 U4801 U3600 U2700 C3000 L3800L3802 L3803L3801 L8225 U5800 U3901 C4 23 6 C4640 FL3901 U4123 U4025 U2040 U2050 U9000 U1300 L8112 U5811 FL3902 L3840 L3825 C4321 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * *** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * TOP SIDE ASSEMBLY LAYER BOARDS) AS APPLICABLE. 062-0031 (DOUBLE-SIDED BOARDS) OR 062-0073 (MULTI- TO STANDARDS AS DEFINED IN APPLE SPECIFICATION ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM NOTES: ORIG DIV APPLE THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED HURLEY DESIGNER 01/08/13 DATE SCALE 1:1 (II) NOT TO REPRODUCE OR COPY IT (III) NOT TO REVEAL OR PUBLISH IT THE POSSESSOR AGREES TO THE FOLLOWING (I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE PROPRIETARY PROPERTY OF APPLE THE INFORMATION CONTAINED HEREIN IS THE NOTICE OF PROPRIETARY PROPERTY DRAWING NUMBER TITLE 820-4124-A X200 MLB (C1) PCBF,
  • 2. Apple Inc. NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 8 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. IV ALL RIGHTS RESERVED II NOT TO REPRODUCE OR COPY IT 3 B 7 BRANCH DRAWING NUMBER SIZE D SHEET R DATE D A C PAGE A C 3456 D B 8 7 6 5 4 2 1 12 APPD CK 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DRAWING TITLE DESCRIPTION OF REVISIONREV ECN REVISION PROPRIETARY PROPERTY OF APPLE INC. TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_HEAD REFERENCE DESIGNATOR(S) BOM OPTION TABLE_5_HEAD QTY DESCRIPTIONPART# DRAWING TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM SCH AND BOARD PART NUMBERS MLB-C1 X200 0002535199A 051-0886 A.0.0 2014-01-13PRODUCTION RELEASED 1 OF 121 1 OF 54 SCH,MLB-C1,X200 LAST_MODIFIED=Tue Oct 29 15:52:27 2013 J85 MLB_C12/05/20122218 VIDEO: EDP SUPPORT & CONN BUTTON: CONN N/A N/A2117 AUDIO: CS35L19A AMPS KAVITHA 01/18/20122016 KAVITHA 01/18/20121915 AUDIO: L81 CODEC AUDIO: HP FLEX CONN N/A1814 TOUCH: SUPPORT CKT & CONN N/A 06/21/20101713 IO: TRISTAR N/A N/A1311 SOC: MISC & ALIASES N/A 04/11/20111210 SOC: VDD, SRAM, CPU, GPU PWRS N/A 04/18/2011119 SOC: SRAM, IO PWRS N/A 04/18/2011108 SOC: DP,MIPI MLB 05/04/201297 SOC: NAND N/A 04/18/201186 N/A 05/05/201175 SOC: MAIN N/A 04/18/201164 BOM TABLES J72_MLB_C11/26/201243 BLOCK DIAGRAM: SYSTEM J85_MLB_B04/02/201322 11/26/201212154 POWER: ALIASES J72_MLB_C J85 MLB_C12/03/129352 J72_MLB_C11/26/20129051 SEP: EEPROM & SOC DEBUG J85 MLB_C11/26/201285 POWER: PP1V8_SW J72_MLB_C11/26/20128449 PMU: ANYA PAGE 4 J72_MLB_C11/26/20128348 PMU: ANYA PAGE 3 J85 MLB_C12/03/20128247 PMU: ANYA PAGE 2 J72_MLB_C11/26/20128146 PMU: ANYA PAGE 1 N/A N/A7545 POWER: BATTERY CONNECTOR WIFI_DEV05/20/20135844 WIFI/BT: MODULE N/A 04/18/20115743 IO: FILTERS & HOTBAR CONN RADIO_MLB_8710/29/20134942 CELL: ANTENNA FEEDS RADIO_MLB_8710/29/20134841 CELL: GPS RADIO_MLB_8710/29/20134740 CELL: RX DIVERSITY RADIO_MLB_8710/29/20134639 CELL: ASM AND HB LTE FRONT-END RADIO_MLB_8710/29/20134538 CELL: PA DCDC CONVERTER RADIO_MLB_8710/29/20134437 CELL: 2G PA RADIO_MLB_8710/29/20134336 CELL: BAND 5/8 PAD RADIO_MLB_8710/29/20134235 CELL: BAND 7/20 PAD RADIO_MLB_8710/29/20134134 CELL: BAND 2/3 PAD RADIO_MLB_8710/29/20134033 CELL: PENTABAND PA RADIO_MLB_8710/29/20133932 CELL: RF TRANSCEIVER (3 OF 4) RADIO_MLB_8710/29/20133831 CELL: RX MATCHING RADIO_MLB_8710/29/20133730 CELL: RF TRANSCEIVER (2 OF 2) RADIO_MLB_8710/29/20133629 CELL: RF TRANSCEIVER (1 0F 2) RADIO_MLB_8710/29/20133528 CELL: BASEBAND (2 OF 2) RADIO_MLB_8710/29/20133427 CELL: BASEBAND (1 OF 2) RADIO_MLB_8710/29/20133326 CELL: BASEBAND PMU (2 OF 2) RADIO_MLB_8710/29/20133225 CELL: BASEBAND PMU (1 0F 2) RADIO_MLB_8710/29/20133024 CELL:AP INTERFACE & DEBUG CONNECTORS N/A N/A2923 CAMERA: REAR CONN & FILTERS J85 MLB_C12/05/122822 SENSOR: PROX CONTENTS DATESYNC MASTERPDF CSA N/A N/A2721 SENSOR: ACCEL, COMPASS, GYRO SYNC MASTERCONTENTS DATECSAPDF TABLE OF CONTENTS N/A N/A11 PCB11820-4124 PCBF,MLB-C1,X200 1 SCH1051-0886 SCH,MLB-C1,X200 J72_MLB_C11/26/20129453 TEST: EE TP/PPCAMERA: FF-ALS CONN & FILTERS J85 MLB_C12/03/20122620 SENSOR: OSCAR J72_MLB_C11/26/20122419 NAND STORAGE 05/04/20121412 TEST: TP/HOLES/FIDUCIALS 50 03/31/2011 MLB SOC: I/OS
  • 3. Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT HSIC2 HSIC1 I2C2 I2S1 ALS I2C3 CSA 27CSA 27CSA 27 BATTERY I2S3 I2S4 CSA 13 SPI2 I2S2 CSA 14 CSA 28 1-3 CSA 17 HALL EFF OSCAR I2C0 CSA 24 FMI0 COMPASS SPI1 I2C0 CUMULUS CSA 81-84 FRONT CAMERA UART3 DISPLAY/ BUTTON FLEX AMP LEFT SPEAKER USB2.0 WIFI/BT ANT WIFI/BT ANT CSA 58 TRISTAR REAR CAMERA BT_I2S MIPI1C MIPI0C ISP1_I2C ISP0_I2C UART2 UART6 SPI XSP HP FMI1 NAND FLASH UART4 DWI UART5 EDP CSA 75 I2C1 PMU BACKLIGHT TOUCH PANEL SPI BUS GYROACCELEROMETER HOME BUTTON PROX SENSOR ANYA PRIMARY CELLULAR ANT NOT ON CELLULAR/ JTAG GRAPE GPS DIVERSITY CELLULAR ANT HSIC1 WIFI-ONLY CONFIG WIFI/BTUART1 GPS ANT SIM CARD USART ALCATRAZ MBUS CSA 31-46 MIMO MIC1 MIC2 CSA 19 L81 CODEC AUDIO RIGHT USB ASPI2S0 CSA 20 CSA 20 UART0 AMP SPEAKER CUMULUS SYNC_DATE=04/02/2013SYNC_MASTER=J85_MLB_B BLOCK DIAGRAM: SYSTEM 051-0886 A.0.0 2 OF 121 2 OF 54
  • 4. TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD REFERENCE DESIGNATOR(S) BOM OPTION TABLE_5_HEAD QTY DESCRIPTIONPART# TABLE_5_ITEM Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT BOM OPTIONSBOM GROUP TABLE_BOMGROUP_HEAD TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_5_ITEM TABLE_5_ITEM TABLE_BOMGROUP_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_5_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) REFERENCE DESIGNATOR(S) BOM OPTION TABLE_5_HEAD QTY DESCRIPTIONPART# TABLE_5_ITEM WIFI 4.3UF CAP U2200 338S1233 ST MICRO - DISQUAL’ED PMU 338S1191 OLD ACCEL - ST MICRO 338S1114 OLD ACCEL - ST MICRO 338S1158 OLD GYRO - ST MICRO OLD INVENSENSE P/N 338S1200 (3/22/13) OLDER INVENSENSE P/N 338S1135 GYRO MECHANICAL PARTS Page Notes ACCEL Power aliases required by this page: 128GB_PROD ANDGATE_TI FERRITE_TY JTAG_DAP DEVELOPMENT_JTAG_TAP COMMON BOM OPTIONS 64GB_PROD ALTERNATE MLB (WDOG TO PMU) BOM options provided by this page: 32GB_PROD 16GB_PROD FERRITE_TDK Signal aliases required by this page: (NONE) WIFI BOM OPTIONS SOC (NONE) FLASH CONFIGURATIONS BARCODE LABEL/EEEE CODES NOTE: FOLLOWING J72, U2200 USES 353S3672 FOOTPRINT (353S4272 HAS SMALLER PADS DUE TO NEW DFM RULES) U5800339S0213339S0223 RDAR #13988471C1009,C1015,...138S0657138S0702 132S0288 1 CRITICAL338S1163 IC,ACCEL,3-AXIS,DIG,BMA282,LGA14 U2700 CRITICALU81001343S0656 IC,PMU,ANYA,D2089A1,OTPXX,FCCSP342 1 U1400TOS,19NM,PPN1.5,C,12DP,64GB 96GB335S0929 SYNC_DATE=11/26/2012SYNC_MASTER=J72_MLB_C BOM TABLES FENCE,RADIO,MLB,C BRD,X221806-7613 1 PD_CAN_RADIO CRITICAL 1 CRITICALPD_FENCE_MLB806-6207 FENCE,TALL,MLB,X221 BASIC COMMON,ALTERNATE C2726CAP 0.1UF 16V 0201 CRITICAL GYRO_INVENSENSE1 C2726CAP 0.01UF 25V 0201132S0391 CRITICAL GYRO_STMICRO1 U27201 GYRO_INVENSENSECRITICAL338S1218 TOS,19NM,PPN1.5,C,QDP,32GB335S0922 32GB1 U1400 1 U1400 64GB335S0923 TOS,19NM,PPN1.5,C,ODP,64GB CRITICAL EEEE_X200C_BETTER_IVSFNJFEEEE FOR 639-5389 (X200C1 BETTER IVS)1825-7639 CRITICAL GYRO_STMICRO338S1192 1 GYRO, ST MICRO U2720 U0652H6P + 1GB ELPIDA339S0207 1 CRITICAL HYNIX DDRU0652339S0207339S0208 335S0923 HYNIX 20NM PPN1.5 64GB64GB U1400335S0932 335S0931 335S0922 HYNIX 20NM PPN1.5 32GB32GB U1400 U140016GB HYNIX 20NM PPN1.5 16GB335S0921335S0930 U14001 TOS,19NM,PPN1.5,C,16DP,128GB 128GB335S0924 EEEE FOR 639-5391 (X200C1 BEST+ IVS) EEEE_X200C_BEST+_IVSFNJ7 CRITICAL1825-7639 EEEE_X200C_ULTIMATEFNJ6EEEE FOR 639-5387 (X200C1 ULTIMATE)825-7639 1 CRITICAL EEEE_X200C_BESTFNJ9EEEE FOR 639-5385 (X200C1 BEST)825-7639 1 CRITICAL EEEE_X200C_BETTERFNJ5EEEE FOR 639-5394 (X200C1 BETTER) CRITICAL825-7639 1 EEEE_X200C_GOODFNJDEEEE FOR 639-5393 (X200C1 GOOD)1 CRITICAL825-7639 EEEE_X200C_GOOD_IVSFNJ8EEEE FOR 639-5388 (X200C1 GOOD IVS)825-7639 CRITICAL1 EEEE_X200C_ULTIMATE_IVSFNJGEEEE FOR 639-5392 (X200C1 ULTIMATE IVS) CRITICAL1825-7639 EEEE_X200C_BEST_IVSFNJCEEEE FOR 639-5390 (X200C1 BEST IVS) CRITICAL1825-7639 EEEE_X200C_BEST+FNJHEEEE FOR 639-5386 (X200C1 BEST+)825-7639 1 CRITICAL U14001 16GB335S0921 TOS,19NM,PPN1.5,C,DDP,16GB U2200IC,SLG5AP1423V,PWR SW,GREENFET3,4A,TDFN8353S4272 1 GYRO, INVENSENSE 051-0886 A.0.0 4 OF 121 3 OF 54
  • 5. SYM 1 OF 13 HSIC2_STB USB_VSSA0 USB_ANALOGTEST TESTMODE USB_DP USB_DM WDOG TST_CLKOUT FAST_SCAN_CLK USB_REXT USB_VBUS USB_ID JTAG_SEL JTAG_TRST* JTAG_TDO JTAG_TDI HSIC_VSS120 JTAG_TCK JTAG_TMS JTAG_TRTCK XI0 XO0 HSIC0_DATA HSIC0_STB HSIC2_DATA HSIC_VSS121 HSIC_VSS122 RESET* CFSB HOLD_RESET FUSE1_FSRC HSIC1_DATA HSIC1_STB USB_VDD330 USB_DVDD VDD_ANA_PLL_CCC ANALOGMUXOUT HSIC_VDD120 HSIC_VDD122 HSIC_VDD121 VDD_ANA_PLL IN BI BI OUT IN IN IN BI BI BI BI IN IN IN IN TP IN IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT H6P: JTAG, USB, PLL, HSIC, XTAL USBHS ON/OFF TOLERANCE 5V/1.98V NOTE: NEW USB_REXT VALUE FOR H6 = 200 OHM TBD: XTAL PASSIVES WILL CHANGE ON H6P WITH FIRST HW BUILD OLD (H5) VALUE: 44.2 OHM (REPLACE WITH XW LATER?) NOTE: CANDIDATE FOR COST-SAVINGS (25MA) (25MA) (5.4MA) (6X1MA) (1MA) VDDIO18_GRP4 VDDIO18_GRP1 (3X13MA) HSIC_VDD120 HSIC_VDD122 HSIC_VDD121 VDDIO18_GRP3 1.8V TOLERANT C0630 20% 0.1UF 01005 X5R-CERM 6.3V R0642 MF 1% 01005 200 1/32W R0622 010050.00 C0608 X5R 10% 0.01UF 6.3V 01005 C0648 10% X5R 6.3V 0.01UF 0100501005 0.1UF 20% C0651 6.3V X5R-CERM C0690 0.22UF 6.3V 20% X5R 0201 U0652 H6P FCMSP POP-1GB-DDR OMIT C0607 12PF 16V CERM 01005 5% 100K 1% R0617 01005 MF 1/32W C0618 10% 6.3V X5R-CERM 01005 1000PF R0651 68.1K 1/32W MF 1% 01005 46 11 52 11 52 10 81011244852 1052 C0613 5% 16V CERM 12PF 01005 1052 100K R0647 1% 01005 MF 1/32W R0646 1/32W MF 01005 1% 100K 1/32W MF 01005 1% 100K R0645 4453 4453 242753 242753 41152 41152 Y06021.60X1.20MM-SM 24.000MHZ-30PPM-9.5PF-60OHM 10 452 TP-P55 TP0600 10 10 52 C0691 0.22UF 6.3V 20% X5R 0201 R0655 01005 1% 1/32W MF 1.00M MF 1/32W 1% 01005 R0640 1.33K C0627 6.3V 10% 01005 0.01UF X5R SOC: MAIN SYNC_DATE=04/18/2011SYNC_MASTER=N/A =PP1V8_SOC =PP1V0_USB_SOC XTAL_SOC_24M_I XTAL_SOC_24M_O =PP3V3_USB_SOC PP1V8_PLL_SOC_F =PP1V2_HSIC_SOC RESET_SOC_L SOC_24M_O USB_VBUS_DETECT USB_REXT =PP1V8_PLL_SOC NC_USB_ANALOGTEST SOC_TESTMODE USB_SOC_P USB_SOC_N WDOG_SOC SOC_TEST_CLKOUT SOC_FAST_SCAN_CLK USB_VBUS_DETECT_R NC_USB_ID TP_JTAG_SOC_TDO NC_JTAG_SOC_TRTCK NC_HSIC0_DATA NC_HSIC0_STB NC_ANALOGMUXOUT JTAG_SOC_SEL JTAG_SOC_TMS JTAG_SOC_TDI JTAG_SOC_TCK SOC_HOLD_RESET JTAG_SOC_TCK JTAG_SOC_TMS JTAG_SOC_TDI =PP1V8_SOC MAKE_BASE=TRUE HSIC2_WLAN_STB HSIC2_BB_STB HSIC2_BB_DATA HSIC1_WLAN_STB MAKE_BASE=TRUE HSIC1_BB_DATA JTAG_SOC_TRST_L HSIC1_BB_STB MAKE_BASE=TRUE HSIC2_WLAN_DATA MAKE_BASE=TRUE HSIC1_WLAN_DATA 6 OF 121 A.0.0 4 OF 54 051-0886 2 1 1 2 1 2 2 1 2 1 2 1 2 1 AM34 H23 D26 AB3 B29 A29 AD4 AC3 AD3 E23 D23 E24 D28 E28 E27 F27 H20 C28 F28 D27 F25 E25 A26 B26 AM33 H21 AM32 F29 E29 D29 H16 A27 B27 F23 F24 AE20 E26 G22 AM31 G23 U16 1 2 1 2 2 1 1 2 1 2 1 2 1 2 42 13 2 1 1 2 1 2 2 1 457101854 54 54 52 54 54 52 41152 41152 452 457101854
  • 6. OUT OUT IN OUT IN IN IN IN IN IN IN OUT OUT OUT OUT IN OUT OUT OUT IN OUT OUT OUT IN OUT IN OUT IN IN IN IN IN IN IN BI IN OUT OUT OUT OUT IN OUT OUT OUT OUT IN IN IN OUT IN OUT OUT IN IN OUT IN OUT IN OUT OUT IN OUT IN IN OUT OUT OUT OUT IN OUT IN OUT SYM 2 OF 13 GPIO4 UART6_TXD UART6_RXD UART5_RTXD UART4_RTSN UART4_CTSN UART3_RXD UART3_RTSN UART3_CTSN UART2_TXD UART2_RXD UART2_RTSN UART2_CTSN UART1_TXD UART1_RXD UART1_RTSN UART1_CTSN UART0_TXD UART0_RXD TMR32_PWM2 TMR32_PWM1 TMR32_PWM0 GPIO8 GPIO7 GPIO6 GPIO5 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32 GPIO31 GPIO3 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO2 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO1 GPIO0 UART4_RXDGPIO29 GPIO30 UART3_TXD UART4_TXD GPIO10 GPIO9 SPI3_SSIN SPI3_MOSI SPI3_MISO SPI2_SSIN SPI2_SCLK SPI2_MOSI SPI2_MISO SPI1_SSIN SPI1_SCLK SPI1_MOSI SPI1_MISO SPI0_SSIN SPI0_SCLK SPI0_MOSI SPI0_MISO SOCHOT1 SOCHOT0 SIO_7816UART1_SCL SIO_7816UART1_RST SIO_7816UART0_SCL SEP_7816UART1_SCL SEP_7816UART0_RST I2S4_MCK I2S4_LRCK I2S4_DOUT I2S4_DIN I2S4_BCLK I2S3_MCK I2S3_LRCK I2S3_DOUT I2S3_DIN I2S3_BCLK I2S2_MCK I2S2_LRCK I2S2_DOUT I2S2_DIN I2S2_BCLK I2S1_MCK I2S1_LRCK I2S1_DOUT I2S1_DIN I2S1_BCLK I2S0_MCK I2S0_LRCK I2S0_DOUT I2S0_DIN I2S0_BCLK I2C3_SDA I2C3_SCL I2C2_SDA I2C2_SCL I2C1_SDA I2C1_SCL I2C0_SDA I2C0_SCL DWI_DO DWI_DI DWI_CLK SIO_7816UART0_SDA SIO_7816UART0_RST SEP_7816UART1_SDA SEP_7816UART1_RST SEP_7816UART0_SCL SEP_7816UART0_SDA SIO_7816UART1_SDA SPI3_SCLK DISP_VSYNC SYM 3 OF 13 OUT OUT BI BI BI BI OUT OUT OUT OUT IN OUT IN IN IN IN OUT IN IN IN OUT OUT OUT IN IN IN IN OUT IN BI OUT IN OUTOUT OUT OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT VDDIO18_GRP2VDDIO18_GRP2 (SCREEN ROTATION LOCK) VDDIO18_GRP1 VDDIO18_GRP1 VDDIO18_GRP1 VDDIO18_GRP2 VDDIO18_GRP1 SOC I/OS VDDIO18_GRP2 VDDIO18_GRP2 VDDIO18_GRP1 VDDIO18_GRP1 PMU TRISTAR SPK AMPS PROX ALS R0700 1/32W 5% 2.2K MF 01005 MF 01005 2.2K 5% 1/32W R0701 MF 01005 1.8K 1/32W 5% R0702 MF 01005 1.8K 1/32W 5% R0703 01005 MF 2.2K 5% 1/32W R0705R0704 5% 1/32W 2.2K MF 01005 13 1352 1352 1352 220K 1/32W MF 5% 01005 R0771 220K 5% 1/32W MF 01005 R0770 R0765 5% MF 1/32W 220K 01005 1/32W 1% MF 01005 R0738 100K 1/32W 100K 1% MF 01005 R0737 100K 1/32W 1% 01005 MF R0736R0735 01005 1% 100K MF 1/32W 51348 51748 22 242652 10 10 11 24 28 52 11 24 28 52 15 15 15 15 1553 1553 15 15 10 10 10 10 48 53 48 52 1% MF 01005 33.2 1/32W R0720 1553 10 10 10 17 17 51748 10 45 48 1653 1653 1653 1653 1553 1553 1553 15 1% 1/32W 33.2 01005 MF R0721 1653 548 48 10 1352 1352 44 44 44 53 44 53 11 52 11 52 19 48 19 19 53 19 53 4453 24 28 24 28 10 19 13 52 242752 242752 242752 242752 242752 11 52 11 52 FCMSP H6P POP-1GB-DDR U0652 OMIT CRITICAL OMIT H6P FCMSP POP-1GB-DDR CRITICAL U0652 13 5 51 5 51 5 16 52 5 11 48 52 5 19 5 16 52 5 19 5 11 48 52 5 48 R0751 1/32W 5% 2.2K MF 01005 R0750 01005 MF 2.2K 1/32W 5% R0753 NOSTUFF 1/32W 5% 2.2K MF 01005 R0752 NOSTUFF 01005 MF 2.2K 1/32W 5% 100K 5% MF 1/32W 01005 R0754 1/32W 100K 01005 MF 5% R0755 44 53 44 53 10 10 10 1552 2852 20 2428 552 19 242652 18 1148 16 28 28 516 R0739 1/32W MF 100K 1% 01005 28 5 20 22 5 20 22 16 5 16 5214 14 SYNC_DATE=05/05/2011SYNC_MASTER=N/A SOC: I/OS GPIO_SOC2BEACON_EN GPIO_SOC2AJ_HS3_SHUNT_EN DISPLAY_SYNC GPIO_SOC2AJ_HS4_SHUNT_EN =PP1V8_SOC NC_SPI1_NAVAJO_MISO NC_SPI1_NAVAJO_MOSI NC_SPI1_NAVAJO_SCLK NC_GPIO_NAVAJO2SOC_INT GPIO_SPKAMP_RST_L GPIO_SOC2PMU_KEEPACT HSIC1_SOC2WLAN_HOST_RDY HSIC2_BB2SOC_REMOTE_WAKE HSIC2_BB2SOC_DEVICE_RDY HSIC2_SOC2BB_HOST_RDY SOCHOT1_L SOCHOT0_L I2C2_SCL_1V8 GPIO_BTN_VOL_UP_L HSIC1_SOC2WLAN_HOST_RDY GPIO_FORCE_DFU GPIO_SPKAMP_KEEPALIVE HSIC1_WLAN2SOC_REMOTE_WAKE NC_SEP_7816UART1_SDA DWI_AP_DO PMU_GPIO_OSCAR2PMU_HOST_WAKE UART3_SOC2BB_TX UART2_WLAN2SOC_TX UART2_SOC2WLAN_TX UART1_SOC2BT_TX UART1_BT2SOC_TX UART1_BT2SOC_RTS_L UART1_SOC2BT_RTS_L UART0_SOC_RXD GPIO_OSCAR_RESET_L GPIO_BTN_VOL_DOWN_L GPIO_BTN_ONOFF_L UART0_SOC_TXD UART3_BB2SOC_TX UART3_SOC2BB_RTS_L UART3_BB2SOC_RTS_L SOCHOT1_L =PP1V8_S2R_MISC GPIO_BTN_SRL_L I2C1_SOC2OSCAR_SWDIO_1V8 I2C1_SOC2OSCAR_SWDCLK_1V8 =PP1V8_SOCGPIO_BTN_HOME_L GPIO_BTN_ONOFF_L =PP1V8_S2R_MISC =PP1V8_ALWAYS NC_SEP_7816UART0_RST SEP_I2C0_SDA HSIC1_WLAN2SOC_DEVICE_RDY NC_SEP_7816UART1_SCL I2C0_SCL_1V8 I2C1_SOC2OSCAR_SWDIO_1V8 I2C0_SDA_1V8 I2S2_CODEC_XSP_LRCK I2S2_CODEC_XSP_DIN I2S1_SPKAMP_DOUT I2S1_SPKAMP_MCK I2S0_CODEC_ASP_LRCK SPI2_CODEC_CS_L SPI2_CODEC_SCLK SPI2_CODEC_MOSI SPI2_CODEC_MISO SPI1_GRAPE_CS_L SPI1_GRAPE_SCLK SPI1_GRAPE_MOSI NC_SPI0_SSIN GPIO_BOARD_ID1 BB_JTAG_TCK BB_JTAG_TDI BB_JTAG_TMS I2S3_SOC2BT_DATA I2S3_BT2SOC_DATA I2S2_CODEC_XSP_BCLK I2S0_CODEC_ASP_MCK_R I2S0_CODEC_ASP_DOUT I2S0_CODEC_ASP_DIN I2S0_CODEC_ASP_BCLK OSCAR_TIME_SYNC_HOST_INT GPIO_BTN_SRL_L GPIO_BTN_HOME_L I2S0_CODEC_ASP_MCK I2S2_CODEC_XSP_DOUT I2S3_SOC2BT_BCLK SPI1_GRAPE_MISO GPIO_BOARD_ID0 I2S1_SPKAMP_LRCK I2S1_SPKAMP_DIN UART6_TS_ACC_RXD UART6_TS_ACC_TXD UART4_SOC2OSCAR_TXD CLK_32K_SOC2CUMULUS UART5_BATT_RTXD UART4_OSCAR2SOC_RXD NC_UART2_CTS NC_UART2_RTS I2C3_SDA_1V8 I2C3_SCL_1V8 SEP_I2C0_SDA SEP_I2C0_SCL BB_JTAG_TDO BB_JTAG_TRST_L I2C2_SCL_1V8 I2C0_SDA_1V8 I2C0_SCL_1V8 I2C2_SDA_1V8 TP_SOC_TST_CPUSWITCH_OUT SEP_I2C0_SCL NC_SEP_7816UART1_RST I2S3_SOC2BT_LRCK GPIO_BOARD_REV0 GPIO_BOARD_REV1 GPIO_BOARD_REV2 GPIO_CODEC_IRQ_L GPIO_SOC2BB_WAKE_MODEM GPIO_GRAPE_IRQ_L BB_IPC_GPIO GPIO_ALS_IRQ_L GPIO_BOARD_ID3 GPIO_BB2SOC_RESET_DET_L GPIO_BOOT_CONFIG0 GPIO_PMU2SOC_IRQ_L GPIO_SOC2PMU_KEEPACT GPIO_GRAPE_RST_L GPIO_BB2SOC_GPS_SYNC GPIO_SOC2BB_RADIO_ON_L GPIO_BOOT_CONFIG1 GPIO_FORCE_DFU TP_GPIO_DFU_STATUS GPIO_SOC2OSCAR_DBGEN GPIO_BOOT_CONFIG2 GPIO_BOOT_CONFIG3 GPIO_SOC2BB_RST_L GPIO_PROX_IRQ_L GPIO_SPKAMP_RST_L GPIO_TS2SOC2PMU_INT GPIO_SPKAMP_LEFT_IRQ_L GPIO_SOC2LCD_PWREN GPIO_BT_WAKE GPIO_BB2SOC_GSM_TXBURST I2C1_SOC2OSCAR_SWDCLK_1V8 GPIO_BOARD_ID2 I2C2_SDA_1V8 I2C3_SCL_1V8 I2C3_SDA_1V8 DWI_AP_CLK GPIO_SPKAMP_RIGHT_IRQ_L GPIO_SPKAMP_KEEPALIVE NC_GPIO_BB_HSIC_DEV_RDY NC_GPIO_GYRO_IRQ1 I2S1_SPKAMP_BCLK I2S1_SPKAMP_MCK_R =PP1V8_S2R_MISC SOCHOT0_L 051-0886 A.0.0 7 OF 121 5 OF 54 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 AD5 Y31 W31 AM5 AU3 AV3 AP1 AN4 AN3 AM1 AM2 AM3 AL5 AK3 AK4 AL4 AL2 AR18 AR19 AC32 AD34 AC31 AE5 AE2 AF1 AE4 AT17 AT16 AR16 AP16 AT15 AT14 AR14 AP15 AD1 AV13 AT13 AT12 AN14 AR13 AP12 AP13 AK2 AJ4 AB2 AJ5 AG5 AH4 AH2 AH3 AG4 AG3 AG1 AF2 AB1 AC5 AT3AP14 AU13 AN1 AT2 AF4 AF3 AP11 AN12 AV10 AN8 AP7 AR6 AU6 AR5 AU4 AV4 AU5 AV5 AT5 AP5 AN6 AP17 AP18 AA32 AA33 AA31 AR2 AR1 AE31 AE32 AE33 AD31 AF33 AG31 AH33 AG34 AF31 AG32 E30 AJ34 AH34 AH31 AJ33 AL33 AK33 AK34 AJ32 AL34 C30 AL31 AK31 AJ31 AL32 W32 W30 AR11 AT11 AU7 AP8 AR7 AV6 AT19 AT18 AP19 AB31 AB33 AP4 AR4 AP3 AP2 AA34 AT10 AN17 1 2 1 2 1 2 1 2 1 2 1 2 1 2 457101854 5 16 5 48 5 44 53 28 24 28 24 28 5 49 52 5 44 53 5 52 5 16 52 44 53 5 48 55154 5 17 48 519 519 4571018545 13 48 5 17 48 55154 54 44 53 52022 52022 551 551 51652 5114852 5114852 51652 55154 5 49 52
  • 7. OUT OUT OUT OUT OUT BI BI BI BI BI BI BI BI OUT BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT PPN0_ALE PPN0_CEN0 PPN0_CEN1 PPN0_CLE PPN0_DQS PPN0_IO0 PPN0_IO1 PPN0_IO2 PPN0_IO3 PPN0_IO4 PPN0_IO5 PPN0_IO6 PPN0_IO7 PPN0_REN PPN0_VREF PPN0_WEN PPN0_ZQ PPN1_ALE PPN1_CEN0 PPN1_CEN1 PPN1_CLE PPN1_IO0 PPN1_IO1 PPN1_IO2 PPN1_IO3 PPN1_IO4 PPN1_IO5 PPN1_IO6 PPN1_REN PPN1_VREF PPN1_WEN PPN1_ZQ PPN1_DQS PPN1_IO7 SYM 4 OF 13 VSS VSS SYM 11 OF 13 VSSVSS SYM 12 OF 13 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT VDDIO18_GRP3 1252 12 12 12 12 12 12 12 1253 12 12 12 12 100K 1/32W 1% MF 01005 R0831 MF R0832 100K 1% 1/32W 01005 12 52 12 12 12 12 12 12 12 12 1253 12 12 12 12 12 10% 0.01UF X5R 01005 6.3V C0860 C0861 10% 0.01UF X5R 01005 6.3V R0860 50K MF 1/32W 01005 1% R0861 50K MF 1/32W 1% 01005 U0652 POP-1GB-DDR H6P FCMSP OMIT CRITICAL 01005 R0870 1% 240 1/32W MF 01005 R0871 1% 240 MF 1/32W FCMSP POP-1GB-DDR H6P U0652 OMIT CRITICAL FCMSP POP-1GB-DDR H6P U0652 OMIT CRITICAL SYNC_DATE=04/18/2011SYNC_MASTER=N/A SOC: NAND NC_PPN1_CEN1NC_PPN0_CEN1 FMI1_CE0_L PPVREF_FMI_SOC FMI0_AD<4> FMI0_AD<0> FMI0_CE0_L FMI0_WE_L FMI0_AD<7> FMI0_AD<6> FMI0_AD<5> FMI0_AD<2> FMI0_AD<1> FMI0_DQS FMI0_ALE FMI1_AD<1> FMI1_AD<0> FMI1_AD<2> FMI1_AD<4> FMI1_AD<3> FMI1_AD<7> FMI1_AD<6> FMI1_AD<5> FMI1_CLE FMI1_ALE FMI1_DQS =PP1V8_NAND_SOC FMI0_ZQ FMI1_ZQ FMI1_WE_L FMI1_RE_LFMI0_RE_L FMI0_CLE FMI0_AD<3> =PP1V8_NAND_SOC 051-0886 A.0.0 8 OF 121 6 OF 54 1 2 1 2 2 1 2 1 1 2 1 2 A31 G32 H31 B31 D34 B32 C32 C33 C34 F32 F33 F34 G34 D33 D31 A32 E33 N34 R32 P32 P31 M34 M33 L32 M32 K32 J32 H33 L31 N31 N32 K33 L34 H34 1 2 1 2 A11 A1 AA3 AF29 AJ30 A3 A4 A5 A7 A9 A13 A14 A16 A18 A25 A28 A30 A33 A34 AA1 AA2 AA4 AA8 AA10 AA12 AA14 AA16 AA18 AA22 AA24 AA26 AA28 AA30 AB5 AB7 AB9 AB11 AB15 AB17 AB19 AB21 AB23 AB25 AB27 AB29 AB32 AC4 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 AC24 AC26 AC28 AC30 AC34 AD2 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD21 AD23 AD25 AD29 AD32 AE3 AE8 AE10 AE12 AE16 AE18 AE22 AE24 AE26 AE28 AF5 AF7 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF23 AF32 AG2 AG8 AG10 AG12 AG14 AG16 AG18 AG20 AG22 AG24 AG26 AG28 AG30 AH5 AH7 AH9 AH11 AH13 AH15 AH17 AH19 AH21 AH23 AH25 AH27 AH29 AH32 AJ1 AJ3 AJ8 AJ10 AJ12 AJ14 AJ16 AJ18 AJ22 AJ24 AJ26 AK5 AK7 AK9 AK11 AK13 AK15 AK17 AK19 AK21 AK23 AK27 AK29 AK32 AL3 AL6 AL8 AL10 AL12 AL14 AL16 AL18 AL20 AL22 AL24 AL26 AL28 AL30 AM4 AM7 AM18 AM30 AN2 AN5 AN7 AB6 AM9 AM11 AM13 AN16 AM15 AN19 AN20 AN21 AN22 AN23 AN24 AJ28 A2 AB13 AE14 AN31 AP25 AP26 E10 E11 E12 G28 G26 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G1 F31 F30 F26 F15 F14 F13 F12 F10 F9 F8 F7 F6 F5 F4 F3 F2 E34 E32 E31 E22 E21 E20 E19 E18 E15 E14 E13 E8 E7 E5 E4 E3 E1 D22 D21 D20 D19 D18 D17 D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C31 C29 C27 C26 C23 C22 C19 C18 C17 C16 C15 C13 C11 C10 C9 C7 C6 C5 C3 C2 C1 B34 B33 B30 B28 B25 B19 B18 B17 B16 B15 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B2 B1 AV34 AV33 AV20 AV18 AV16 AV14 AV11 AV9 AV2 AV1 AU34 AU33 AU21 AU18 AU16 AU11 AU2 AU1 AT32 AT31 AT30 AT29 AT28 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 AT6 AT4 AT1 AR32 AR20 AR17 AR15 AR12 AR8 AR3 AP28 AP27 AP24 AN33 AN32 AR29 AR28 AR25 AR24 AR22 AR21 E9 C12 AP21 AP20 AP6 AN34 AP32 AR23 E6 C24 AP30 AP31 D32 D16 AP29 6 54 654
  • 8. OUT OUT OUT BI IN IN OUT OUT OUT OUT BI OUT OUT OUT IN IN IN IN DP_PAD_AUXN DP_PAD_AUXP DP_PAD_AVDD_AUX DP_PAD_AVDD0 DP_PAD_AVDD1 DP_PAD_AVDD2 DP_PAD_AVDD3 DP_PAD_AVDDP0 DP_PAD_AVDDX DP_PAD_AVSS_AUX DP_PAD_AVSS0 DP_PAD_AVSS1 DP_PAD_AVSS2 DP_PAD_AVSS3 DP_PAD_AVSSP0 DP_PAD_AVSSX DP_PAD_DC_TP DP_PAD_DVDD DP_PAD_DVSS DP_PAD_R_BIAS DP_PAD_TX0N DP_PAD_TX0P DP_PAD_TX1N DP_PAD_TX1P DP_PAD_TX2N DP_PAD_TX2P DP_PAD_TX3N DP_PAD_TX3P EDP_HPD SYM 6 OF 13 MIPI0C_DPDATA0 SENSOR1_RST SENSOR1_CLK MIPI1C_DPDATA0 SENSOR0_RST SENSOR0_ISTRB SENSOR0_CLK MIPI1D_VREG_0P4V MIPI1D_VDD18 MIPI1C_DPDATA1 MIPI1C_DPCLK MIPI1C_DNDATA1 MIPI1C_DNDATA0 MIPI1C_DNCLK MIPI0D_VREG_0P4V MIPI0D_VDD18 MIPI0D_DPCLK MIPI0D_DNCLK MIPI0C_DPDATA2 MIPI0C_DPDATA1 MIPI0C_DNDATA2 MIPI0C_DNDATA1 MIPI_VSS ISP0_SDA ISP0_SCL ISP1_SCL MIPI0C_DPDATA3 MIPI0C_DNDATA3 MIPI0C_DPCLK MIPI0D_DNDATA3 MIPI0D_DPDATA3 MIPI0D_DNDATA2 MIPI0D_DPDATA2 MIPI0D_DNDATA1 MIPI0D_DPDATA1 MIPI0C_DNCLK MIPI0D_DPDATA0 MIPI0D_DNDATA0 MIPI_VDD10 SENSOR1_ISTRB MIPI0C_DNDATA0 ISP1_SDA SENSOR0_XSHUTDOWN SENSOR1_XSHUTDOWN SYM 5 OF 13 OUT OUT OUT OUT OUT OUT IN BI BI OUT OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (2MA) (2MA) (55MA) VDDIO18_GRP1 VDDIO18_GRP1 MIPI_VDD10 (50MA) (50MA) (1MA) (50MA) (14MA) (50MA) VDDIO18_GRP3 (14MA) (10MA) DISPLAYPORT 20 52 20 52 20 52 20 52 20 53 20 53 R0940 49.9 01005 01005 5% 2.2K 1/32W MF R0932 1/32W R0933 01005 5% 2.2K MF 20 53 20 53 R0941 01005 100 23 52 23 52 01005 5% 2.2K 1/32W MF R0931 01005 2.2K 5% 1/32W MF R0930 23 52 23 52 2353 2353 2353 2353 2353 2353 CRITICAL OMIT U0652 FCMSP POP-1GB-DDR H6P C0962 20% 0.1UF X5R-CERM 6.3V 01005 20% 0204 1UF 4V X6S C0930 CRITICAL OMIT U0652 POP-1GB-DDR H6P FCMSP C0957 1.0UF 0201-1 6.3V X5R 20% 18 53 18 53 18 53 18 53 18 53 18 53 18 18 18 18 53 18 53 R0900 01005 MF 1/32W 4.99K 1% NOSTUFF 01005 6.3V X5R 0.01UF 10% C0950 C0958 01005 16V NP0-C0G-CERM 8.2PF +/-0.5PF 1/32W 0% 0.00 MF R0901 01005 C0951 16V 01005 5% 56PF NP0-C0G C0952 01005 16V NP0-C0G-CERM 8.2PF +/-0.5PF 01005 NP0-C0G C0953 56PF 5% 16V 0201 20% X5R 6.3V C0954 0.22UF C0955 0201-1 6.3V X5R 1.0UF 20% C0956 0201-1 6.3V X5R 1.0UF 20% SOC: DP,MIPI SYNC_MASTER=MLB SYNC_DATE=05/04/2012 =PP1V8_MIPI_SOC NC_MIPI1D_VREG NC_MIPI0D_VREG NC_SENSOR1_XSHUTDOWN NC_SENSOR1_ISTRB NC_SENSOR0_ISTRB NC_SENSOR0_XSHUTDOWN NC_MIPI0C_CAM_REAR_DATA_P2 NC_MIPI0C_CAM_REAR_DATA_N2 MIPI0C_CAM_REAR_DATA_P<0> EDP_DATA_P<1> PP1V8_EDP_AVDD_AUX =PP1V8_SOC ISP0_CAM_REAR_SCL ISP0_CAM_REAR_SDA ISP0_CAM_REAR_CLK ISP1_CAM_FRONT_CLK_R MIPI1C_CAM_FRONT_DATA_P<0> ISP0_CAM_REAR_CLK_R NC_MIPI1C_CAM_FRONT_DATA_P1 MIPI1C_CAM_FRONT_CLK_P NC_MIPI1C_CAM_FRONT_DATA_N1 MIPI1C_CAM_FRONT_DATA_N<0> MIPI1C_CAM_FRONT_CLK_N NC_MIPI0D_DPCLK NC_MIPI0D_DNCLK MIPI0C_CAM_REAR_DATA_P<1> MIPI0C_CAM_REAR_DATA_N<1> NC_MIPI0C_CAM_REAR_DATA_P3 NC_MIPI0C_CAM_REAR_DATA_N3 MIPI0C_CAM_REAR_CLK_P NC_MIPI0D_DNDATA3 NC_MIPI0D_DPDATA3 NC_MIPI0D_DNDATA2 NC_MIPI0D_DPDATA2 NC_MIPI0D_DNDATA1 NC_MIPI0D_DPDATA1 MIPI0C_CAM_REAR_CLK_N NC_MIPI0D_DPDATA0 NC_MIPI0D_DNDATA0 MIPI0C_CAM_REAR_DATA_N<0> =PP1V0_MIPI_SOC =PP1V8_EDP_SOC SOC_EDP_R_BIAS EDP_AUX_N EDP_AUX_P TP_EDP_PAD_DC_TP EDP_DATA_N<0> EDP_DATA_P<0> EDP_DATA_N<1> EDP_DATA_N<2> EDP_DATA_P<2> EDP_DATA_N<3> EDP_DATA_P<3> EDP_HPD ISP1_CAM_FRONT_SDA ISP1_CAM_FRONT_SCL ISP0_CAM_REAR_SHUTDOWN_L ISP1_CAM_FRONT_CLK ISP1_CAM_FRONT_SHUTDOWN_L =PP1V0_EDP_PAD_DVDD_SOC 051-0886 A.0.0 9 OF 121 7 OF 54 1 2 1 2 1 2 1 2 1 2 1 2 B20 A20 F18 F19 F20 F21 F22 G18 F17 G17 H19 G19 G20 G21 H18 H17 E16 F16 G16 E17 B21 A21 B22 A22 B23 A23 B24 A24 D30 2 1 2 1 AU27 AT9 AU9 AT33 AN28 AT8 AN10 AV8 AR30 AR31 AP33 AR33 AP34 AT34 AR34 AR27 AR26 AU30 AV30 AU24 AU26 AV24 AV26 AM28 AM27 AM26 AM25AN29 AV7 AT7 AU8 AU23 AV23 AU25 AV28 AU28 AV29 AU29 AV31 AU31 AV25 AU32 AV32 AN25 AN26 AN27 AM29 AL25 AR10 AV27 AP9 AR9 AP10 2 1 1 2 2 1 2 1 1 2 2 1 2 1 2 1 2 1 2 1 2 1 54 4 5 10 18 54 54 54 54
  • 9. DDR1_VREF_CA DDR0_VREF_CA DDR1_RREF_DQ VSS DDR0_CKEIN DDR0_VDD_CKE DDR1_RREF_CA DDR0_RREF_CA DDR0_RREF_DQ DDR0_VREF_DQ DDR1_VREF_DQ VDDCA VDD2 VDD1 VDDQ DDR1_VDD_CKE DDR1_CKEIN SYM 7 OF 13 VDDIOD_DDR1CA VDDIOD_DDR0CA VDDIO18_GRP4 VSS VDDIO18_GRP2 VDDIO18_GRP1 VDDIOD_DDRDQ VDDIO18_GRP3 SYM 9 OF 13 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (DDR IMPEDANCE CONTROL) ON 5/6/12, BY MANU G NOTE: CKEIN CONFIRMED 1.8V TOLERANT CAPS FOR VDDIOD ARE SHARED WITH VDDQ (45MA) (500MA) SHARED WITH VDDIOD) (CURRENT CONSUMPTION (CURRENT CONSUMPTION SHARED WITH VDDIOD) (<1MA) (<1MA) (1000MA) (20MA) (31MA) (2MA) (65MA) (GPIO,UART,SPI,I2C) (SENSOR,SOCHOT,PMU) CAPS FOR VDDIO18_X ARE SHARED WITH VDDIODX NOSTUFF 0.01UF 10% 6.3V C1056 X5R 01005 R1056 01005 1.00K MF 1% 1/32W R1055 01005 1/32W MF 1% 1.00K X5R 6.3V 01005 NOSTUFF C1054 0.01UF 10% R1053 01005 MF 1% 1.00K 1/32W R1054 01005 1% 1/32W 1.00K MF 0204 1UF 20% 4V X6S C1007 1UF 0204 20% 4V X6S C1006 R1031 MF 01005 240 1% 1/32W 01005 MF R1001 240 1/32W 1% 01005 0.1UF C1000 20% 6.3V X5R-CERM C1009 0610 4V 4.3UF X5R-CERM 20% 20% 4V X7S 0204 0.47UF C1004 20% 4V X5R-CERM 0610 4.3UF C1015 0610 4V 20% X5R-CERM 4.3UF C1027 OMIT CRITICAL U0652 H6P POP-1GB-DDR FCMSP 4V 0204 20% X6S 1UF C1029 4V 0204 X7S 20% 0.47UF C1026 X6S 1UF 4V 0204 20% C1028 20% 0.47UF X7S 0204 4V C1031 X6S 0204 1UF 20% 4V C1071 20% 4V X7S 0.47UF 0204 C1073 402 4.7UF X5R 6.3V 20% C1070 X6S 4V 20% 1UF 0204 C1072 H6P POP-1GB-DDR FCMSP OMIT CRITICAL U0652 0201 FL1000 1KOHM-25%-0.2A X5R-CERM 10V 20% 1.0UF 0201-1 C1042 01005 MF R1000 240 1/32W 1% R1030 MF 01005 240 1% 1/32W NOSTUFF X5R 10% 01005 0.01UF 6.3V C1002 R1005 01005 1/32W MF 2.21K 1% R1006 01005 MF 2.21K 1% 1/32W NOSTUFF 6.3V C1052 0.01UF X5R 10% 01005 01005 MF 2.21K 1% 1/32W R1051 R1052 01005 MF 1/32W 1% 2.21K SOC: SRAM, IO PWRS SYNC_MASTER=N/A SYNC_DATE=04/18/2011 DDR0_CA_ZQ DDR0_DQ_ZQ DDR1_CA_ZQ =PP1V2_S2R_DDR_SOC PPVREF_DDR1_DQ MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0.6V VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM MAX_NECK_LENGTH=3 MM PPVREF_DDR1_CA VOLTAGE=0.6V MIN_LINE_WIDTH=0.3MM MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2MM PPVREF_DDR0_DQ MIN_LINE_WIDTH=0.3MM MAX_NECK_LENGTH=3 MM VOLTAGE=0.6V PPVREF_DDR0_CA =PP1V2_VDDQ_DDR =PP1V2_S2R_DDR =PP1V2_VDDQ_DDR =PP1V2_S2R_DDR PPVREF_DDR1_DQ PPVREF_DDR0_DQ =PP1V2_VDDQ_DDR =PP1V8_S2R_DDR RESET_SOC_L =PP1V8_VDDIO18_SOC =PP1V2_VDDIOD_SOC PP1V8_XTAL PPVREF_DDR1_CA =PP1V2_S2R_DDR DDR1_DQ_ZQ PPVREF_DDR0_CA 051-0886 A.0.0 10 OF 121 8 OF 54 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.15 MM NET_SPACING_TYPE=PWR 2 11 2 1 2 2 1 1 2 1 2 2 1 2 1 1 2 1 2 2 1 2 1 2 1 2 1 2 1 Y33 AU17 T4 H27 K9 H25 J31 J20 G30 G31 G33 H1 H2 H3 H4 H5 H29 H32 J2 J3 J4 J5 J10 J12 J18 J22 J24 J26 J28 J30 K1 K3 K4 K7 K11 K13 K15 K17 K19 K21 K23 K25 K27 K29 K31 K34 L2 J6 J8 J14 K5 AP22 AP23 AC33 AU15 F11 D14 U4 AB34 AF34 AV12 AV15 R34 W34 AC2 AD33 C20 G2 J33 L3 P33 U2 U33 Y34 AJ2 AG33 AU10 AU14 AU22 AV17 AU20 C8 C4 C14 D24 AK1 AE34 B3 D25 B14 E2 J34 P34 V33 U1 AU12 AV22 AU19 A6 A8 C25 C21 J1 F1 L1 R1 N1 V1 A10 A12 A15 A17 A19 AE1 AC1 AH1 AL1 Y1 K2 J16 U31 U32 AV21 AV19 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 AG6 AE6 AC6 Y30 AM17 Y19 Y21 Y23 Y27 Y29 Y32 AM8 AM12 Y17 Y15 Y13 Y9 Y5 Y4 Y2 W33 W28 W26 W24 W22 W20 W18 W16 W12 W8 W5 W3 V34 V32 V30 V27 V25 V15 V13 V9 V7 V5 V4 V3 V2 U34 U30 V29 U29 T29 R29 AM24 AM23 AM22 AM21 AM20 Y6 W10 W14 U6 T6 G29 G24 P30 H30 K30 M30 W2 T11 T9 T7 V23 V21 V19 V17 U22 U20 U18 U14 U12 U10 U8 U5 U3 T34 T33 T32 T31 T30 T27 T25 T23 T21 T19 T17 T15 T13 T5 T3 T2 T1 R33 AH30 AD30 AM19 AM10 AH6 AD6 V11 Y3 Y7 Y11 AA6 H10 H11 H12 H13 H14 H15 M6 N6 P6 R6 V6 W6 AM14 AM16 H9 W4 W1 U28 U26 H6 H7 H8 U24 G27 G25 AJ6 AE30 21 2 1 1 2 1 2 2 1 1 2 1 2 2 1 1 2 1 2 54 8 8 8 8 854 854 854 854 8 8 854 54 41011244852 954 54 52 8 854 8
  • 10. VDD_SENSE VDDVDD SYM 10 OF 13 SYM 8 OF 13 VDD_ANA_TMPSADC0 VDD_ANA_TMPSADC1 VDD_ANA_TMPSADC2 VDD_ANA_TMPSADC3 VDD_SRAM_SOC VSS VDD_SRAM_CPU VDD_GPUVDD_CPU VDD_GPU_SENSE VDD_SENSE_CPU SYM 13 OF 13 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (VDD BALLS = VDD_SOC PWR DOMAIN) 7,500MA FOR G3 GPU @125C @1.1V/1.2GHZ 10,800MA FOR CPU0+1 @1.1V @125C (2.5MA) (2.5MA) (2.5MA) (2.5MA) @125C @1.0V (1500MA) 1,500MA FOR CYCLONE + M$ SRAM (THERMAL VIRUS) @1.0V @125C 2,500MA FOR VDD_SOC POP-1GB-DDR H6P FCMSP U0652 OMIT CRITICAL 20% 4V 0610 4.3UF X5R-CERM C1148 20% C1151 1UF 4V X6S 0204 4V 0.47UF 20% C1153 X7S 0204 0204 X6S C1150 1UF 20% 4V X7S 4V 20% 0204 C1152 0.47UF FCMSP POP-1GB-DDR H6P U0652 OMIT CRITICAL C1160 20% 0.1UF 01005 6.3V X5R-CERM OMIT POP-1GB-DDR H6P U0652 CRITICAL FCMSP CRITICAL C1103 4V X5R-CERM 4.3UF 0610 20% C1102 X5R-CERM 4.3UF 0610 20% 4V CRITICAL C1101 4V 20% X5R-CERM 4.3UF 0610 CRITICALCRITICAL C1100 0610 20% 4V X5R-CERM 4.3UF C1109 CRITICAL 0204 X6S 4V 20% 1UF C1114 +/-0.5PF 8.2PF 01005 NP0-C0G-CERM 16V C1108 CRITICAL 1UF 20% 4V X6S 0204 C1107 CRITICAL 1UF 20% 4V X6S 0204 0201 0.22UF 20% X5R 6.3V C1113 C1106 20% 1UF 4V 0204 X6S CRITICAL 4V 20% 1UF C1105 0204 X6S CRITICAL 0201 0.22UF 20% X5R 6.3V C1112C1111 0.47UF 20% 0204 X7S 4V CRITICAL 0204 X6S 20% C1104 1UF 4V CRITICAL 0204 20% 0.47UF C1110 CRITICAL X7S 4V C1118 CRITICAL 4V X5R-CERM 0610 4.3UF 20% C1117 CRITICAL 4.3UF 4V 20% 0610 X5R-CERM C1122 4V 20% X5R-CERM 4.3UF 0610 CRITICAL C1126 20% 1UF 4V 0204 X6S CRITICAL C1121 CRITICAL 4V 20% X5R-CERM 4.3UF 0610 C1125 1UF 20% 4V X6S 0204 CRITICAL C1116 20% X5R 4V 0402 15UF C1115 20% X5R 4V 0402 15UF 4.3UF 0610 X5R-CERM 20% 4V CRITICAL C1120 C1124 20% 1UF 4V X6S 0204 CRITICAL 4.3UF X5R-CERM 0610 20% 4V CRITICAL C1119 C1123 20% 1UF 4V 0204 X6S CRITICAL C1130 20% 1UF 4V X6S 0204 CRITICAL C1129 20% 1UF 4V X6S 0204 CRITICAL C1134 01005 8.2PF NP0-C0G-CERM 16V +/-0.5PF 0201 0.22UF 20% C1133 6.3V X5R C1128 20% 1UF 4V 0204 X6S CRITICAL C1127 1UF 20% 4V 0204 X6S CRITICAL C1132 CRITICAL 0204 X6S 4V 20% 1UF C1131 CRITICAL 0204 X6S 4V 20% 1UF C1138 4V 0204 0.47UF 20% CRITICAL X7S 0.47UF 4V 20% 0204 CRITICAL C1142 X7S C1137 4V 20% 0204 0.47UF CRITICAL X7S CRITICAL 4V 20% 0204 C1141 0.47UF X7S 0201 6.3V X5R C1145 0.22UF 20% C1136 20% 0204 4V 0.47UF CRITICAL X7S C1140 CRITICAL 4V 0204 0.47UF 20% X7S 20% CRITICAL C1135 0.47UF 4V X7S 0204 C1139 CRITICAL 20% 0.47UF 0204 4V X7S 01005 20% 6.3V X5R 0.22UF C1144 01005 20% 6.3V 0.22UF X5R C1143 CRITICAL C1187 X7S 4V 20% 0.47UF 0204 CRITICAL C1186 20% 4V 0204 0.47UF X7S CRITICAL C1185 0.47UF 20% 0204 X7S 4V CRITICAL C1184 20% 0204 X7S 4V 0.47UF CRITICAL C1183 0204 4V 1UF 20% X6S CRITICAL C1182 4V 1UF 20% X6S 0204 C1194 8.2PF +/-0.5PF 01005 NP0-C0G-CERM 16V 0.22UF X5R 6.3V 20% 01005 C1193C1192 01005 20% 6.3V X5R 0.22UF C1191 01005 20% 6.3V X5R 0.22UF C1190 01005 20% 6.3V X5R 0.22UF CRITICAL 20% 1UF 4V 0204 X6S C1181 CRITICAL 20% 0204 1UF 4V X6S C1180 CRITICAL 20% 1UF 4V X6S C1179 0204 CRITICAL X6S 4V 20% 1UF 0204 C1178 CRITICAL 0610 4V 20% X5R-CERM 4.3UF C1177 CRITICAL 4V X5R-CERM 4.3UF 0610 20% C1176 CRITICAL 20% X5R-CERM 4.3UF 0610 4V C1175 CRITICAL 4.3UF 0610 4V 20% X5R-CERM C1174 CRITICAL 4V 20% 4.3UF 0610 X5R-CERM C1173 CRITICAL X5R-CERM 4V 20% 4.3UF 0610 C1172 15UF 0402 4V X5R 20% C1171 15UF 0402 4V 20% X5R C1170 0.47UF 0204 4V X7S 20% C1189 CRITICAL 0204 4V X7S 20% 0.47UF CRITICAL C1188 SOC: VDD, SRAM, CPU, GPU PWRS SYNC_MASTER=N/A SYNC_DATE=04/18/2011 =PPVDD_CPU =PPVDD_GPU PPVDD_CPU_SOC_SENSE PPVDD_GPU_SOC_SENSE =PP1V8_VDDIO18_SOC =PPVDD_SRAM_SOC PPVDD_SOC_SOC_SENSE =PPVDD_SOC 051-0886 A.0.0 11 OF 121 9 OF 54 P20 P22 K10 K8 K18 K16 K14 K12 K6 J29 J27 J23 J21 J19 J17 J15 J13 J11 AK6 AK20 R7 V31 R17 U23 R25 V22 J25 N27 N17 N15 N13 AN11 Y20 Y18 Y16 W19 W17 W7 V28 V26 V24 V20 V18 V16 V14 U27 U25 U21 U19 U17 U7 T28 T26 T24 T22 T20 T18 T16 T14 R27 R23 R21 R19 R15 R13 P28 P24 P18 P16 P14 P12 P10 P8 N29 N25 N23 N21 N19 N11 N9 N7 M26 M24 M22 M20 M18 M16 M14 M12 M10 L27 L25 L23 L21 L19 L17 L15 L13 L11 L9 L7 K28 J9 J7 H28 H24 AN9 AL23 AK30 AN18 AF30 AF20 AF6 AE21 AN15 AD20 AN13 AB20 AB14 AA17 K20 AA7 U15 P26 M28 L29 AA19 R11 R9 K26 K24 K22 H26 AH20 AB30 M8 2 1 2 1 2 1 2 1 2 1 R28 R30 R31 AJ20 AA20 AB4 H22 AA9 AA11 AA13 AA15 AB8 T10 T12 U11 L4 L5 L6 L8 L10 L12 L14 L16 L18 L20 L22 L24 L26 L28 L30 L33 M1 M2 M3 M4 M5 M7 M9 M11 M13 M15 M17 M19 M21 N3 N5 N8 N10 N12 N14 N16 N18 N20 N22 N24 N26 N28 N30 P1 P2 P3 P4 P7 P9 P11 P13 P17 P19 P21 P23 P25 P27 P29 R2 R3 R4 R5 R8 R10 R16 R18 R24 R26 T8 U9 W13 V10 V8 U13 W15 W11 W9 V12 Y8 AD24 AD26 AD28 AE23 AE25 AE27 AF24 AF26 AF28 AK25 Y25 M23 M25 M27 M29 M31 N2 N4 N33 P5 P15 R12 R22 R14 R20 Y14 Y12 Y10 2 1 AL29 AL9 AL7 AL19 AC29 AD22 AL13 AL11 AK8 AK14 AK10 AJ9 AJ19 AJ17 AJ15 AH8 AH16 AH12 AG13 AB18 AF8 AF18 AF10 AE9 AE7 AE19 AE17 AB16 AE13 AE11 AD8 AD18 AD16 AD14 AD12 AD10 AB10 AB26 AB24 Y28 Y26 Y24 Y22 W27 W25 W21 AA29 AL27 AL21 AK28 AJ29 AJ25 AJ23 AA27 AJ21 AH26 AH24 AH22 AG21 AB12 AC9 AC19 AF27 AF25 AC27 AC25 AB28 AC23 AC21 AE15 AG9 AG7 AC11 AA25 AA23 AC17 AC15 AC13 AF12 AF14 AF16 AG23 AG27 AF22 AE29 AD27 AK12 AJ7 AJ13 AH18 AH14 AH10 AG15 AC7 AA21 AB22 AG11 AG17 AJ11 AK16 AK18 AL15 AL17 AA5 AM6 AN30 AG19 AG25 AG29 AH28 AJ27 AK22 AK24 AK26 W29 W23 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 54 54 53 854 54 53 54
  • 11. OUT CLK RESET DETGND GND GND GND GND GND I/O DETECT VCC VPP OUT BIIN IN SCHEMATIC DEFINED CONSTRAINTS (YES/NO) CKPLUS RULE EXCEPTIONS TABLE_DASHBOARD_INFO REQUIRED Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT EVT101 BOARD_ID[1] MLB_C SIM CARD SPI0 TEST MODE MLB BOARD REVISION S/W READ FLOW 2. DISABLE PU AND ENABLE PD 1. SET GPIO AS INPUT BOARD_ID[0] ID[3-0] SYSTEM 1. SET GPIO AS INPUT BOOT_CONFIG[3-0] 2. DISABLE PU AND ENABLE PD BOOT_CONFIG[3] (GPIO29) S/W READ FLOW BOOT_CONFIG[0] (GPIO18) BOOT_CONFIG[2] (GPIO28) BOARD ID 3. READ BOARD_ID[3] BOARD_ID[2] BRD_REV[2-0] 3. READ 1. SET GPIO AS INPUT S/W READ FLOW 3. READ BOOT_CONFIG[1] (GPIO25) BOOT CONFIG ID 1010 J85 AP 1011 J85 DEV 1100 J86 AP 1101 J86 DEV 1110 J87 AP 1111 J87 DEV MLB_B 0000 0010 JTAG SPI0 0011 0001 2. ENABLE PU AND DISABLE PD NAND <-- SELECTED NAND TEST MODE ID_J85_J87 2.2K 5% 01005 1/32W MF R1205 01005 5% MF 1/32W 2.2K R1201 NOSTUFFNOSTUFF 2.2K 1/32W 5% R1200 MF 01005 01005 5% 2.2K 1/32W MF R1203 NOSTUFF MF 1/32W 2.2K 5% R1206 ID_DEV 01005 ID_J86_J87 5% 2.2K 01005 1/32W MF R1204 R1260 5% 100 MF 1/32W 01005 01005 1/32W 2.2K 5% MF R1213 4 52 100 5% 1/32W MF 01005 R1210 01005 R1250 0% 0.00 1/32W MF NOSTUFF SIM-CARD-X113-X223 F-ST-SM CELL J3000 24 28 52 24 28 52242852 242852 C3002 CELL CERM 6.3V 5% 100PF 01005 01005 MF 1/32W 1% CELL 15.00K R3000 C3001 0402 X5R 10% 16V 1.0UF CELL 01005 MF 1/32W 5% 2.2K R1202 1/32W 5% 100 R1211 01005 MF NOSTUFF 2.2K 01005 5% MF R1207 1/32W 2.2K MF 5% R1208 01005 1/32W NOSTUFF 5% 2.2K 01005 1/32W MF R1209 NO SYNC_DATE=04/11/2011SYNC_MASTER=N/A SOC: MISC & ALIASES GPIO_BOOT_CONFIG2 SIMCRD_CLK_CONN SIMCRD_RST_CONN PP_LDO6_RUIM_1V8 NC_J3000_5 SIMCRD_IO_CONN SIM_TRAY_DETECT MAKE_BASE=TRUE WDOG_SOC WDOG_SOC2PMU_RESET_IN MAKE_BASE=TRUE I2S3_BT2SOC_DATA I2S4_BT2SOC_DATA I2S3_SOC2BT_DATA MAKE_BASE=TRUE I2S4_SOC2BT_DATA I2S3_SOC2BT_BCLK MAKE_BASE=TRUE I2S4_SOC2BT_BCLK I2S3_SOC2BT_LRCK MAKE_BASE=TRUE I2S4_SOC2BT_LRCK RESET_SOC_LJTAG_SOC_TRST_L JTAG_SOC_SEL GPIO_BOARD_ID1 GPIO_BOARD_REV1 SOC_FAST_SCAN_CLK GPIO_BOARD_ID2 GPIO_BOARD_REV2 GPIO_BOOT_CONFIG3 GPIO_BOARD_REV0 GPIO_BOARD_ID3 SOC_HOLD_RESET SOC_TESTMODE =PP1V8_SOC =PP1V8_SOC GPIO_BOARD_ID0 GPIO_BOOT_CONFIG0 GPIO_BOOT_CONFIG1 051-0886 A.0.0 12 OF 121 10 OF 54 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 3 2 8 11 10 12 4 9 6 7 1 5 2 1 1 2 2 1 1 2 1 2 1 2 1 2 1 2 5 24252752 4 48 5 44 5 44 5 44 5 44 4 8 11 24 48 52452 5 5 4 5 5 5 5 5 4 4 52 457101854 457101854 5 5 5
  • 12. OUT IN OUT OUT OUT DIG_DP DVSS DVSS DVSS DIG_DN USB1_DP USB1_DN USB0_DP UART0_TX USB0_DN UART1_TX UART0_RX UART2_TX UART1_RX JTAG_CLK UART2_RX JTAG_DIO ACC_PWR VDD_3V0 VDD_1V8 P_IN ACC1 ACC2 DP1 DN1 DP2 DN2 CON_DET_L HOST_RESET SWITCH_EN SDA INT SCL BYPASS POW_GATE_EN* BRICK_ID Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 343S0658 = TRISTAR 2, A1 TRISTAR 343S0614 = TRISTAR 1 TO USB BB MUX (T’S OFF TO H4A UART4) AP USB ACCESSORY UART AP DEBUG UART TRISTAR BYPASS FOR 3V LDO BB DEBUG UART 343S0639 = TRISTAR 2, A0 998-5855 = TRISTAR 2, TC 46 4 8 10 24 48 52 48 CRITICAL C1303 1.0UF X5R-CERM 10V 20% 0201-1 0.1UF 6.3V C1302 10% CERM-X5R 0201 0.1UF X5R-CERM C1300 01005 6.3V 20% 0.1UF 20% 6.3V X5R-CERM 01005 C1301 5 48 +/-0.5PF 16V 01005 8.2PF C1321 NP0-C0G-CERM C1320 16V 01005 NP0-C0G-CERM 8.2PF +/-0.5PF C1322 16V NP0-C0G-CERM 01005 +/-0.5PF 8.2PF R1370 MF 0.00 0% 1/32W 01005 15 C1360 10V 20% X5R-CERM 1.0UF 0201-1 CRITICAL C1361 10% 1UF 402 X5R 25V CBTL1610A1UK U1300 CRITICAL WLCSP SYNC_DATE=N/ASYNC_MASTER=N/A IO: TRISTAR MIKEY_TS_P MIKEY_TS_N USB_BB_P USB_BB_N USB_SOC_P UART6_TS_ACC_TXD USB_SOC_N UART0_SOC_TXD UART6_TS_ACC_RXD UART3_BB2SOC_TX UART0_SOC_RXD JTAG_SOC_TCK UART3_SOC2BB_TX JTAG_SOC_TMS =PP3V0_S2R_TRISTAR PPVBUS_PROT PPOUT_E75_ACC_ID1 PPOUT_E75_ACC_ID2 E75_DPAIR1_P E75_DPAIR1_N E75_DPAIR2_P E75_DPAIR2_N TS_CON_DET_L TS2PMU_RESET_IN RESET_SOC_L I2C0_SDA_1V8 GPIO_TS2SOC2PMU_INT I2C0_SCL_1V8 TRISTAR_BYPASS NET_SPACING_TYPE=PWR VOLTAGE=3V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM MAX_NECK_LENGTH=0.5MM OVP_SW_EN_L PMU_USB_BRICKID L81_MBUS_REF =PP1V8_S2R_TRISTAR =PP3V3_ACC 051-0886 A.0.0 13 OF 121 11 OF 54 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 2 1 C3 F5 C1 A6 C4 A1 B1 A3 E2 B3 F2 E1 D2 F1 A5 D1 B5 D5 F4 F3 F6 C5 E5 A2 B2 A4 B4 E3 B6 E4 D3 C6 D4 E6 D6 C2 1552 1552 245253 245253 452 552 452 552 552 5242852 552 452 5242852 452 54 46 52 43 43 43 43 43 43 43 5 48 52 5 48 52 48 54 54
  • 13. IN IN IN IN IN IN IN IN IN IN IN IN BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI IO0-1 IO7-1 IO6-1 IO3-1 IO4-1 IO5-1 IO1-1 IO2-1 IO7-0 IO5-0 IO6-0 IO4-0 IO2-0 IO3-0 IO1-0 IO0-0 VCC CLE1 CE1* CLE0 CE0* WE0* ALE0 RE0 RE0* DQS0* R/B0* DQS0 ALE1 WE1* RE1 RE1* DQS1 DQS1* R/B1* ZQ VREF VSSQVSS VCCQ VDDI TMSC TCKC Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT ENSURE TRACE INDUCTANCE < 2NH LAYOUT NOTE FOR U1400 VDDI: C1413 2.2UF X5R-CERM 0201 20% 4V 20% C1412 15UF 4V 0402 X5R 20% C1411 15UF 4V 0402 X5R 20% C1410 4V X5R 15UF 0402 C1404 20% 4V X7S 0.47UF 0204 C1407 1UF 20% X5R 6.3V 02010204 20% C1405 X6S 4V 1UF 6 52 6 6 6 6 6 53 6 52 6 6 6 6 6 R1454 MF 1% 243 1/32W 01005 0201 20% 4V C1450 2.2UF X5R-CERM 6 6 6 653 6 6 6 6 6 6 6 6 6 6 6 6 OMIT LGA-12X17 U1400 CRITICAL XXNM-XGBX8-MLC-PPN1.5-ODP R1460 01005 1% 1/32W MF 50K R1461 01005 1% 1/32W MF 50K 6.3V 01005 C1460 X5R 0.01UF 10% 6.3V 01005 C1461 X5R 0.01UF 10% 16V 5% 01005 NP0-C0G C1491 27PF 16V 5% 01005 NP0-C0G 27PF C1490 27PF 16V 5% 01005 NP0-C0G C1492 NP0-C0G 01005 5% 16V 27PF C1494 27PF NP0-C0G 01005 5% 16V C1493 10UF 6.3V CERM-X5R 0402-2 20% C1402 20% CERM-X5R 6.3V 0402-2 10UF C1401 6.3V 20% 10UF CERM-X5R 0402-2 C1400 20% 0402-2 CERM-X5R 6.3V 10UF C1480 1UF 20% C1406 6.3V X5R 0201 SYNC_DATE=05/04/2012 NAND STORAGE SYNC_MASTER=MLB =PP3V3_NAND FMI1_AD<3> FMI1_AD<4> FMI0_AD<4> FMI0_CE0_L NC_U1400_RE0 FMI1_CE0_L FMI_ZQ_U1400 FMI0_AD<5> FMI0_RE_L PPVREF_FMI_NAND =PP1V8_NAND FMI1_AD<0> FMI1_AD<7> FMI1_AD<6> FMI1_AD<5> FMI1_AD<1> FMI0_AD<7> FMI0_AD<6> FMI0_AD<2> FMI0_AD<3> FMI0_AD<1> FMI0_AD<0> FMI1_CLE FMI0_CLE FMI0_WE_L FMI0_ALE FMI0_DQS FMI1_ALE FMI1_WE_L NC_U1400_RE1 FMI1_RE_L FMI1_DQS NC_U1400_DQS1 TP_TMSC_U1400 TP_TCKC_U1400 TP_U1400_RB0 NC_U1400_DQS0 TP_U1400_RB1 =PP1V8_NAND PPVDDI_NAND FMI1_AD<2> 051-0886 A.0.0 14 OF 121 12 OF 54 2 1 2 1 2 1 2 12 1 2 1 2 1 1 2 2 1 G1 G7 J7 N3 N5 L7 J1 L1 H6 K6 J5 L5 J3 K2 H2 G3 F2 M6 B6 C3 C5 A3 A5 E3 C1 B4 C7 F4 E5 H4 D2 E1 D4 D6 M4 K4 E7 A1 G5 OA8 OF8 G0 OE0 OD8 OC8 N7 OE8 OD0 OC0 A7 M2 L3 F6 B2 OF0 G8 N1 OB8 OB0 OA0 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 12 1 2 1 2 1 2 1 2 1 54 12 48 54 53 53 53 53 12 48 54
  • 14. CAP ON S D VDD GND Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TOUCH SUBSYSTEM (PLUG - FLEX 998-4527) RCPT - MLB 998-4526 -> 516S1054 LAYOUT NOTE: PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION 0.38 DCR 1/32W MF R1752 0.000% 01005 J1700 503304-2010 CRITICAL F-ST-SM-1 MF R1790 1/32W 1.00K 1% 01005 R1753 0.00 01005 MF 0% 1/32W NOSTUFF C1761 27PF 5% NP0-C0G 16V 01005 0201 C1702 X7R-CERM 16V 1000PF 10% X5R 10V 10% 1UF 402 C1701 27PF 01005 16V NP0-C0G 5% C1700 L1700 0201 240OHM-350MA 1000PF 16V X7R-CERM 0201 C1705 10% C1704 0201 X5R 6.3V 20% 1UF 0201 10% 1000PF X7R-CERM C1708 16V X5R 6.3V 20% 1UF 0201 C1707 5% 27PF NP0-C0G C1703 16V 01005 240OHM-350MA 0201 L1701 0201-2 240-OHM-0.2A-0.8-OHM L1702 01005 5% 27PF NP0-C0G 16V C1706 6.3V X5R 1UF 20% 0201 C1752 CRITICAL SLG5AP302 U1700 TDFN CRITICAL C1750 0201 10% 0.1UF X5R-CERM 16V CRITICAL C1751 10% X7R 10V 4700PF 201 CRITICAL 1% 100K R1751 MF 1/32W 01005 X5R-CERM 10UF C1753 20% 0402-2 10V CRITICAL 01005 150OHM-25%-200MA-0.7DCR L1760 C1760 27PF 5% NP0-C0G 16V 01005 TOUCH: SUPPORT CKT & CONN SYNC_MASTER=N/A SYNC_DATE=06/21/2010 PP1V8_GRAPE_SW GPIO_BTN_HOME_L GPIO_BTN_HOME_FILT_LGPIO_BTN_HOME_R_L PP3V0_S2R_HALL_FILT DISPLAY_SYNC_R SPI1_GRAPE_MOSI SPI1_GRAPE_MISO GPIO_GRAPE_IRQ_L CLK_32K_SOC2CUMULUS SPI1_GRAPE_CS_L PP1V8_GRAPE_FILT GPIO_GRAPE_RST_L GPIO_BTN_HOME_FILT_L NC_PMU_GPIO_HALL_IRQ_4 PMU_GPIO_MB_HALL3_IRQ PMU_GPIO_MB_HALL2_IRQ PMU_GPIO_MB_HALL1_IRQ PP5V25_GRAPE_FILT SPI1_GRAPE_SCLK_RSPI1_GRAPE_SCLK DISPLAY_SYNC =PP3V0_S2R_HALL PP3V0_S2R_HALL_FILT VCC_MAIN_GRAPE_RAMP =PP1V8_GRAPE =PPVCC_MAIN_GRAPE =PP1V8_S2R_GRAPE =PP5V25_GRAPE PP5V25_GRAPE_FILT PP1V8_GRAPE_FILT 051-0886 A.0.0 17 OF 121 13 OF 54 1 2 13 17 24 23 19 11 15 9 7 5 1 3 18 20 12 14 16 8 10 6 4 2 22 21 1 2 1 2 2 1 2 1 2 1 2 1 21 2 1 2 1 2 1 2 1 2 1 21 21 2 1 2 1 7 2 5 3 18 2 1 2 11 2 2 1 21 2 1 52 548 13 52 1352 52 552 552 552 552 552 1352 552 13 52 48 48 48 13 52 525 5 54 13 52 54 54 54 54 13 52 13 52
  • 15. Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (P/N 510S0761 - FLEX) P/N 510S0760 - MLB AUDIO_JACK_FLEX RET1 AUDIO_JACK_FLEX MIC2 AUDIO_JACK_FLEX MIC1 AUDIO_JACK_FLEX RET2 PER DAVE BREECE J1800 CRITICAL AA07A-S016VA1 F-ST-SM-COMBO 0201-2 L1800 240-OHM-0.2A-0.8-OHM C1800 NP0-C0G 16V 27PF 5% 01005 0.1UF 10% 6.3V C1801 CERM-X5R 0201 NP0-C0G 16V 27PF 5% 01005 C1802 R1850 0% 0.00 MF 1/32W 01005 NOSTUFF NP0-C0G 16V 5% C1850 01005 27PF 01005 5% 16V NP0-C0G 56PF C1821 5% 16V NP0-C0G 56PF C1820 01005 01005 C1822 56PF NP0-C0G 16V 5%5% 16V NP0-C0G 56PF 01005 C1830 AUDIO: HP FLEX CONN SYNC_DATE=03/31/2011SYNC_MASTER=N/A MIN_NECK_WIDTH=0.06 MMVOLTAGE=2.65VPP_LDO14_2V65 LAT_SW2_CTL GPIO_SOC2AJ_HS3_SHUNT_EN PP1V8_DMIC_FILT LAT_SW1_CTL CONN_HP_LEFT_FILT CONN_HP_RIGHT_FILT CONN_HP_HS3_FILT CONN_HP_HEADSET_DET_FILT CONN_HP_HS3_REF_FILT GPIO_SOC2AJ_HS4_SHUNT_EN DMIC1_FF_SCLK_FILT DMIC1_FF_SD CONN_HP_HS4_REF_FILT CONN_HP_HS4_FILT DMIC1_FF_SCLK =PP1V8_DMIC 051-0886 A.0.0 18 OF 121 14 OF 54 20 19 18 17 15 13 11 9 7 1 16 14 12 10 8 6 4 2 5 3 21 2 1 2 1 2 1 1 2 2 1 2 1 2 1 2 1 2 1 2532333940 2852 5 242852 15 15 15 15 15 5 15 15 15 15 54
  • 16. IN IN IN IN IN IN IN IN IN IN IN OUT OUT IN OUT IN OUT OUT IN IN IN IN BI BI OUT OUT SYM 2 OF 2 DMIC1_SCLK DMIC2_SD MCLK GND13 GND0 TSTI2 TSTI1 TSTI0 GND18 GND17 GND16 GND15 GND14 GND12 GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1 RESET* WAKE* INT* CDOUT CDIN CCLK XSP_SDOUT XSP_SDIN_DAC2_MUTE XSP_LRCK_FSYNC XSP_SCLK ASP_SDOUT ASP_SDIN ASP_LRCK ASP_SCLK DMIC2_SCLK DMIC1_SD CS* MBUS_REF SYM 1 OF 2 FLYP MIC4_BIAS_FILT AIN3+ AIN1- FLYN GNDA MIC1_BIAS MIC2_BIAS_FILT_IN MIC2_BIAS_FILT MIC2_BIAS AIN2+ AIN2M MIC2_BIAS_IN AIN3- MIC3_BIAS MIC3_BIAS_FILT AIN4+ AIN4- MIC4_BIAS GNDP GNDD GNDHS +VCP_FILT FILT- FILT+ LINEOUT_REF LINEOUTB LINEOUTA HPDETECT HS4_REF HS3_REF HS4 HS3 HPOUTB HPOUTA DN DP AOUT2- AOUT2+ AOUT1_M AOUT1+ GNDCP -VCP_FILT VA VCP1 VD VP0 VL VP1 VPROG_CP VPROG_MB SPEAKER_VQ AIN1+ MIC1_BIAS_FILT GNDHS FLYC VCP0 IN IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEADDIGITAL MIC TO HEADPHONE JACK TO THE HP CONNECTOR U1900 DECAPS CHANGED ON 5/24/12 PER RADAR #11485846 NOTE: PLACE R1930 & R1931 CLOSE TO U3600 MIKEY BUS FILTER PLACE L1900 TO 1905 CLOSE 14 0402 10UF CERM-X5R CRITICAL 20% 6.3V C1910 XW1900 SHORT-8L-0.25MM-SM NOSTUFF CRITICAL 20% X5R 4.7UF C1907 402 6.3V CRITICAL 4.7UF X5R 20% 402 6.3V C1908 22 010055%1/32W MF R1912 22 MF1/32W 5% 01005 R1913 14 14 5 5 22 01005MF5%1/32W R1910 MF 010055% 22R19111/32W 5 5 5 553 553 5 5 553 553 553 553 552 4852 48 C1912 X5R 6.3V 402 20% 4.7UF MF 1/20W 2.21K 1% R1901 201 0201-1 20% 1.0UF C1911 X5R 6.3V 1.00K 5% 1/32W MF 01005 NOSTUFF R1940 14 14 11 XW1902 NOSTUFF SHORT-8L-0.25MM-SM 0201 CERM-X5R 0.1UF 10%6.3V C1916 0201 CERM-X5R 0.1UF 10%6.3V C1917 SHORT-8L-0.25MM-SM XW1903 NOSTUFF R1931 5% MF 12 201 1/20W R1930 5% MF 201 1/20W 12 C1932 5% 25V 0201 NP0-CERM 100PF SIGNAL_MODEL=EMPTY C1931 5% 100PF 0201 NP0-CERM 25V NOSTUFF C1930 5% NP0-CERM 25V 100PF 0201 SIGNAL_MODEL=EMPTY 11 52 11 52 L1900 FERR-33-OHM-0.8A-0.09-OHM 0201 L1901 FERR-33-OHM-0.8A-0.09-OHM 0201 L1902 FERR-33-OHM-0.8A-0.09-OHM 0201 L1903 FERR-33-OHM-0.8A-0.09-OHM 0201 L1904 01005 120-OHM-210MA L1905 120-OHM-210MA 01005 14 14 C1990 01005 16V NP0-C0G 100PF 5% C1991 5% 100PF NP0-C0G 16V 01005 0201 R1950 1.00 1% 1/20W MF-LF 0201-1 1.0UF 20% 6.3V CRITICAL X5R C1951 X5R C1950 4.7UF CRITICAL 20% 402 6.3V 0201 R1951 1/20W 1% 1.00 MF-LF MF 1/20W 1% R1952 255K 201 C1913 0.1UF 10% 0201 X5R-CERM 10V 5% 1/20W MF 0 R1953 201 U1900 WLCSP CS42L81-CWZR-A1 CRITICAL WLCSP U1900 CS42L81-CWZR-A1 0.1UF 0201 X5R-CERM 10V C1914 10% CRITICAL X5R-CERM 4.7UF 20% 10V 0402 C1909C1904 10V X5R-CERM 0201 10% 0.1UF 20% 6.3V X5R-CERM 01005 C1915 0.1UF 20% 01005 X5R-CERM 6.3V 0.1UF C1902 0201 10% 0.1UF X5R-CERM 10V CRITICAL C1903 4.7UF CRITICAL 6.3V C1901 X5R 402 20% 4.7UF C1905 X5R 6.3V 20% 402 C1906 20% 4.7UF 6.3V 402 X5R 14 L1920 240-OHM-0.2A-0.8-OHM 0201-2 C1920 4700PF 10% 10V X7R 201 NOSTUFF R1920 01005 3.3K 1/32W 5% MF 14 SYNC_DATE=01/18/2012 AUDIO: L81 CODEC SYNC_MASTER=KAVITHA 338S1213 338S1116 RADAR:13373870 SSMC FABU1900 155S0773 155S0453 L1904,L1905 RADAR:11100717 =PP1V7_VA_VCP NO_TEST=TRUENC_MIC4_BIAS MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM CODEC_HP_HS4_REF =PP1V8_AUDIO L81_FLYP 0.15MM 0.3MM L81_FLYC 0.15MM 0.3MM GND_AUDIO_CODEC MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.15MM PP1V7_VCP VOLTAGE=1.7V NO_TEST=TRUEAIN1P NO_TEST=TRUEAIN1N L81_MIC2_BIAS L81_MIC2_BIAS_FILT_IN HP_MIC_POS MIC1_BIAS_FILT NO_TEST=TRUE SPI2_CODEC_MISO SPI2_CODEC_MOSI SPI2_CODEC_SCLK SPI2_CODEC_CS_L L81_MBUS_REF I2S2_CODEC_XSP_DOUT L81_FILT 0.30MML81_PVCP 0.15MM GND_AUDIO_CODEC L81_NVCP 0.30MM0.15MM NO_TEST=TRUE NC_RIGHT_CH_OUT_N NO_TEST=TRUE NC_RIGHT_CH_OUT_P L81_AIN2_POS VOLTAGE=4.2V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.15MM PPVCC_VPROG_CP =PPVCC_MAIN_AUDIO GND_AUDIO_CODEC MIC4_BIAS_FILT NO_TEST=TRUE MIN_NECK_WIDTH=0.15MM PPVCC_VPROG_MB VOLTAGE=4.2V MIN_LINE_WIDTH=0.3MM L81_FLYN 0.15MM 0.3MM PPVCC_VPROG_MB_F MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.3MM VOLTAGE=4.2V 0.15MM 0.20MM GND_AUDIO_CODEC VOLTAGE=0V I2S2_CODEC_XSP_SDOUTI2S2_CODEC_XSP_DIN DMIC1_FF_SCLK DMIC1_FF_SD I2S0_CODEC_ASP_SDOUTI2S0_CODEC_ASP_DIN L81_DMIC1_FF_SD NC_DMIC2_SCLK NO_TEST=TRUE I2S0_CODEC_ASP_BCLK I2S0_CODEC_ASP_LRCK I2S0_CODEC_ASP_DOUT I2S2_CODEC_XSP_BCLK I2S2_CODEC_XSP_LRCK GPIO_CODEC_IRQ_L PMU_GPIO_CODEC_HS_INT_L I2S0_CODEC_ASP_MCK L81_DMIC1_FF_SCLK PMU_GPIO_CODEC_RST_L =PP1V8_AUDIO CODEC_MIC_BIAS_FILT MAKE_BASE=TRUE NC_MIC3_BIAS NO_TEST=TRUE NO_TEST=TRUENC_MIC1_BIAS AIN4P AIN4N MAKE_BASE=TRUE CODEC_AIN AIN3P AIN3N AIN1N AIN1P MIC1_BIAS_FILT MIC4_BIAS_FILT MIC3_BIAS_FILT L81_MIC2_BIAS_IN L81_AIN2_NEG CODEC_HP_HS3 CODEC_HP_RIGHT MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MMCODEC_HP_HS3 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MMCODEC_HP_HS4 MIN_NECK_WIDTH=0.15MMCODEC_HP_LEFT MIN_LINE_WIDTH=0.20MM L81_MBUS_P CONN_HP_HS3_FILT MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.20MM CONN_HP_RIGHT_FILT MIN_LINE_WIDTH=0.20MM CONN_HP_LEFT_FILT MIN_NECK_WIDTH=0.15MM CODEC_HP_DET_R MIN_LINE_WIDTH=0.50MM CONN_HP_HS4_FILT MIN_NECK_WIDTH=0.20MM L81_MBUS_N AIN4N NO_TEST=TRUE MIC3_BIAS_FILT NO_TEST=TRUE NO_TEST=TRUEAIN3N NO_TEST=TRUEAIN3P CONN_HP_HEADSET_DET_FILTCODEC_HP_DET NO_TEST=TRUE NC_LEFT_CH_OUT_N CODEC_HP_DET CODEC_HP_HS4 HP_MIC_NEG NO_TEST=TRUEAIN4P NO_TEST=TRUE NC_LEFT_CH_OUT_P NO_TEST=TRUE NC_CODEC_LINE_OUT_R NC_CODEC_LINE_OUT_LNO_TEST=TRUE MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM CONN_HP_HS3_REF_FILT MIN_NECK_WIDTH=0.1MM CONN_HP_HS4_REF_FILT MIN_LINE_WIDTH=0.15MM L81_MIC2_BIAS_FILT CODEC_HP_HS3_REF MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM L81_MBUS_N L81_MBUS_P MIKEY_TS_P MIKEY_TS_N NC_SPEAKER_VQ 051-0886 A.0.0 19 OF 121 15 OF 54 2 1 21 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 1 2 2 1 1 2 1 22 1 1 2 1 2 2 1 2 1 2 1 21 21 21 21 21 21 2 1 2 1 1 2 2 1 2 1 1 2 1 2 2 1 1 2 B2 B7 C8 G5 C6 D4 C7 C4 J5 H7 H5 G7 G6 F8 F7 F6 F5 E7 E6 E5 D8 D7 D6 D5 D3 C9 B10 B9 A7 B8 A6 A4 A5 B5 B4 A1 A2 B3 A3 B6 B1 C5 K5 H10 F2 C3 E4 K10 G2 H2 K3 F3 G4 C1 D1 J3 C2 H4 G3 D2 E2 F4 E10 A10 J2 H9 F1 E1 H6 J6 K6 H8 J7 K7 K1 J1 K8 J8 K4 J4 D9 D10 F9 F10 J9 K9 G1 G9 A9 E8 A8 E9 G10 H1 C10 E3 H3 K2 J10 G8 2 1 2 1 2 1 2 1 2 1 2 1 2 1 12 12 21 2 1 1 2 1654 52 1554 1552 15 15 15 15 52 1654 1552 15 15 52 1554 15 15 15 15 15 15 15 15 15 1552 52 1552 1552 52 15 52 15 15 15 15 15 15 15 1552 15 52 15 15
  • 17. FILT+ SCL VP SDA VA ADO VBST SW GNDA IREF+ OUT+ OUT- ISENSE+ ISENSE- VSENSE+ VSENSE- LDO_FILT GNDP INT* RESET* ALIVE MCLK SCLK LRCK/FSYNC SDIN SDOUT VER1 FILT+ SCL VP SDA VA ADO VBST SW GNDA IREF+ OUT+ OUT- ISENSE+ ISENSE- VSENSE+ VSENSE- LDO_FILT GNDP INT* RESET* ALIVE MCLK SCLK LRCK/FSYNC SDIN SDOUT VER1 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT SPEAKER CONNECTOR UPDATED: DEC 13 BY MARCH 2013. C0 FIXES PROCESS ISSUES. 2. THE CURRENT VERSION OF L19 IS B0 AND WILL CHANGE TO C0 REMOVED BASED ON PERFORMANCE ON J65 1. ALL THE EMI/DESSENSE FILTER COMPONENTS HAVE BEEN I2C ADDRESS: 1000000X PLACE XWS CLOSE TO CONNECTOR LEFT SPEAKER AMP I2C ADDRESS: 1000001X RIGHT SPEAKER AMP TFA302610A-SM 2.2UH-20%-3.3A-0.115OHM L2050 U2040 WLCSP CS35L19B-CWZR/C0 WLCSP U2050 CS35L19B-CWZR/C0 CRITICAL 0402-1 X5R-CERM 20% 10V 10UF C2094C2092 0.1UF 10% 10V X5R-CERM 0201 C2093 10V 10% 0.1UF X5R-CERM 0201 X5R-CERM 10UF CRITICAL C2095 10V 20% 0402-1 CRITICAL X5R-CERM 0402-1 20% 10V 10UF C2091 CRITICAL C2090 10V 20% 0402-1 X5R-CERM 10UF 10V C2042 CRITICAL X5R-CERM 4.7UF 0402 20% SIGNAL_MODEL=EMPTY SM XW2051 SIGNAL_MODEL=EMPTY SM XW2050 SIGNAL_MODEL=EMPTY SM XW2040 SIGNAL_MODEL=EMPTY SM XW2041 C2054 10V 0201 10% 0.1UF X5R-CERM C2055 603 X5R 10V 20% 10UF CRITICAL R2051 201 MF 1% 44.2K 1/20W 6.3V CERM-X5R 0.1UF 10% C2056 0201 4.7UF X5R-CERM1 CRITICAL C2058 6.3V 20% 402 402 C2057 20% CRITICAL 4.7UF X5R-CERM1 6.3V R2041 201 MF 1% 1/20W 44.2K X5R-CERM1 4.7UF C2048 402 20% 6.3V CRITICAL 20% 0402 10V X5R-CERM C2041 CRITICAL 4.7UF CRITICAL C2051 0402 10V 20% 4.7UF X5R-CERM C2043 0402 X5R-CERM 10V CRITICAL 4.7UF 20% CRITICAL TFA302610A-SM L2040 2.2UH-20%-3.3A-0.115OHM 10% C2044 X5R-CERM 0.1UF 10V 0201 CRITICAL 10UF C2045 20% 10V X5R 603 CERM-X5R 10% 6.3V 0.1UF C2046 0201 X5R-CERM1 CRITICAL C2047 20% 6.3V 4.7UF 402 MF 1% 1/4W 0.100 R2050 CRITICAL 0402 1% MF 1/4W CRITICAL 0.100 R2040 0402 CRITICAL C2052 X5R-CERM 4.7UF 0402 10V 20% CRITICAL C2053 20% 10V 0402 4.7UF X5R-CERM SIGNAL_MODEL=EMPTY XW2077 SM XW2076 SM SIGNAL_MODEL=EMPTY XW2075 SIGNAL_MODEL=EMPTY SM SIGNAL_MODEL=EMPTY SM XW2074 SYNC_MASTER=KAVITHA AUDIO: CS35L19A AMPS SYNC_DATE=01/18/2012 GPIO_SPKAMP_KEEPALIVE I2C2_SDA_1V8 I2S1_SPKAMP_MCK SPKR_L_CONN_P SPKR_L_CONN_P MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM I2S1_SPKAMP_DIN SPKR_R_VSENSE_N SPKR_R_VSENSE_N SPKR_R_CONN_P SPKR_R_CONN_PMIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM =PP1V7_VA_VCP SPKR_R_SES_P SPKR_L_SES_P SPKR_L_VSENSE_N SPKR_L_VSENSE_N =PPVCC_MAIN_AUDIO SPKR_L_VSENSE_P SPKR_L_VSENSE_P SPKR_R_VSENSE_P SPKR_R_VSENSE_P L19_R_SWITCH PP1V7_VA_VCP I2S1_SPKAMP_BCLK I2S1_SPKAMP_LRCK GPIO_SPKAMP_RIGHT_IRQ_L L19_L_LDO_FILT L19_R_LDO_FILT GPIO_SPKAMP_RST_L NET_SPACING_TYPE=PWRL19_L_VBOOST L19_R_IREF L19_L_FILTL19_L_SWITCH L19_L_IREF GPIO_SPKAMP_LEFT_IRQ_L I2S1_SPKAMP_BCLK I2S1_SPKAMP_LRCK I2S1_SPKAMP_DOUT I2C2_SDA_1V8 GPIO_SPKAMP_KEEPALIVE I2C2_SCL_1V8 GPIO_SPKAMP_RST_L I2S1_SPKAMP_MCK MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM SPKR_L_CONN_N SPKR_L_CONN_N SPKR_L_P MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM SPKR_L_SES_N MIN_LINE_WIDTH=0.5 MM SPKR_R_CONN_N MIN_NECK_WIDTH=0.2 MM SPKR_R_CONN_N SPKR_R_P MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM L19_R_FILT I2C2_SCL_1V8 I2S1_SPKAMP_DIN I2S1_SPKAMP_DOUT NET_SPACING_TYPE=PWR L19_R_VBOOST =PPVCC_MAIN_AUDIO SPKR_R_SES_N =PP1V7_VA_VCP 20 OF 121 A.0.0 051-0886 4 OF 416 OF 54 21 F2 D1 D6 A4 B1 C1 D5 F5 C7 A5 A1 A2 D4 F4 F3 B5 B6 C6 E4 C4 C3 B4 B3 B7 D2 C2 E1 F1 E2 E3 C5 D3 A3 A7 A6 D7 E7 E6 F6 F7 E5 B2 F2 D1 D6 A4 B1 C1 D5 F5 C7 A5 A1 A2 D4 F4 F3 B5 B6 C6 E4 C4 C3 B4 B3 B7 D2 C2 E1 F1 E2 E3 C5 D3 A3 A7 A6 D7 E7 E6 F6 F7 E5 B2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 1 2 1 2 1 2 1 2 2 1 2 1 2 1 21 2 1 2 1 2 1 1 2 1 2 1 2 2 1 2 1 1 2 1 2 1 2 1 2 51652 51652 51653 16 43 5216 43 52 51653 16 16 16 43 5216 43 52 15 16 54 16 16 151654 16 16 16 16 475254 51653 51653 5 516 5 51653 51653 51653 51652 51652 51652 516 51653 16 43 5216 43 52 16 43 52 16 43 52 51652 51653 51653 151654 15 16 54
  • 18. Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT BUTTON CONNECTOR (MOVED HERE TO SUPPORT COST FORMAT) (REF DES PRESERVED FOR LAYOUT) 516S0828 01005 MF 1% 1/32W 1.00K R2900 01005 MF 1/32W 1% 1.00K R2901 01005 MF 1% 1/32W 1.00K R2902 01005 1/32W MF 1% 1.00K R2903 12.8V-100PF 201-1 DZ2960 12.8V-100PF 201-1 DZ2961 201-1 12.8V-100PF DZ2962 12.8V-100PF 201-1 DZ2963 CRITICAL J2960 F-ST-SM 503548-1010 25V 0201 CERM 82PF 5% C2963 0201-2 240-OHM-0.2A-0.8-OHM L2963 82PF 5% 25V 0201 CERM C2962 0201-2 240-OHM-0.2A-0.8-OHM L2962 82PF 25V 0201 CERM 5% C2961 0201-2 240-OHM-0.2A-0.8-OHM L2961 CERM 0201 25V 82PF 5% C2960 0201-2 240-OHM-0.2A-0.8-OHM L2960 BUTTON: CONN SYNC_DATE=N/ASYNC_MASTER=N/A GPIO_BTN_ONOFF_R_L GPIO_BTN_VOL_UP_R_L GPIO_BTN_VOL_DOWN_R_L GPIO_BTN_SRL_R_L GPIO_BTN_VOL_DOWN_L GPIO_BTN_VOL_UP_L GPIO_BTN_ONOFF_L GPIO_BTN_SRL_L GPIO_BTN_ONOFF_L_FILT GPIO_BTN_VOL_UP_L_FILT GPIO_BTN_SRL_L_FILT GPIO_BTN_VOL_DOWN_L_FILT 051-0886 A.0.0 21 OF 121 17 OF 54 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 5 3 10 8 6 4 9 7 2 13 11 12 14 2 1 21 2 1 21 2 1 21 2 1 215 5 548 548 52 52 52 52
  • 19. OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN NCIN OUT SYM_VER-2 SYM_VER-2 SYM_VER-2 SYM_VER-2 SYM_VER-2 IN IN IN IN IN IN IN IN IN IN IN GND VDD D SON CAP Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM REVIEW: 4700PF 0201 132S0187 EDP CONNECTOR SUPPORT LAYOUT NOTE: PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION REVIEW: CAN/SHOULD WE USE 132S0316, 0.1UF 20%, 01005 RDAR://PROBLEM/12579948 RDAR://PROBLEM/12579963 TO REDUCE THE 2.5V FROM THE TCON TO 1.8V TO THE AP? REVIEW: WILL THE DISPLAY INCLUDE A VOLTAGE DIVIDER RDAR://PROBLEM/12579981 P/N 516S1056 NOTE: HOWEVER TO BE CONSERVATIVE, DIVIDER CKT IS NOT REMOVED PER GREG DE MERCEY, EDP_HPD PIN IS 2.5V TOLERANT BACK-UP DELAYED PWREN CKT 7 C2221 NP0-C0G-CERM 50V 56PF 2% 0201 18 18 18 53 18 53 18 53 18 53 18 53 18 53 18 53 18 53 L2240 01005 240-OHM-25%-0.20A-1.0DCR C2260 27PF NP0-C0G 16V 5% 01005 5% R2243 MF 1/32W 01005 100K 18 53 18 53 18 53 18 53 18 53 18 53 18 53 18 53 18 18 C2232 16V 01005 NP0-C0G-CERM 15PF 5% F-ST-SM-1 CRITICAL AA07A-S032-VA1 J2201 L2201 0402A CRITICAL FERR-120-OHM-1.5A 47 47 47 47 47 1852 47 CERM C2230 82PF 0201 5% 25V 1852 1/32W MF 01005 R2250 7.5K 5% U2201 CRITICAL SOT891 74LVC1G32 LCM_PWR_EN_OR_GATE LCM_PWR_EN_OR_GATE 0.1UF 6.3V 20% 01005 X5R-CERM C2270 518 01005 0.000% R2290 MF 1/32W LCM_PWR_EN_OR_GATE CRITICAL C2202 20% 10UF 0402 6.3V CERM-X5R 518 1/32W MF 0% 0.00 R2291 01005 LCM_PWR_EN_RES 0.1UF X5R-CERM C2203 0201 16V 10% R2242 1/32W 01005 MF 5% 20.0K +/-0.5PF C2233 50V C0G-CERM 8.2PF 201 0402 220-OHM-1A L2200 CRITICAL 3.25-OHM-0.1A-2.4GHZ L2242 CRITICAL TAM0605-4SM 5% R2241 100K MF 01005 1/32W 3.25-OHM-0.1A-2.4GHZ L2212 CRITICAL TAM0605-4SM 3.25-OHM-0.1A-2.4GHZ L2222 CRITICAL TAM0605-4SM 3.25-OHM-0.1A-2.4GHZ CRITICAL L2232 TAM0605-4SM C2250 01005 0.1UF 6.3V X5R-CERM20% C2251 6.3V 0.1UF X5R-CERM20%01005 C2242 0.1UF 6.3V X5R-CERM20%01005 20% 0.1UFC2243 6.3V X5R-CERM01005 0.1UFC2244 X5R-CERM20%01005 6.3V 0.1UFC2245 6.3V X5R-CERM20%01005 0.1UFC2246 6.3V X5R-CERM20%01005 0.1UFC2247 6.3V X5R-CERM20%01005 0.1UFC2248 6.3V X5R-CERM20%01005 3.25-OHM-0.1A-2.4GHZ L2202 CRITICAL TAM0605-4SM C2249 0.1UF 6.3V X5R-CERM20%01005 0201 16V 0.1UF X5R-CERM C2239 10% 518 7 7 MF 100K 5% 1/32W 01005 R2205 753 753 753 753 753 753 753 753 TDFN CRITICAL U2200 SLG5AP304V OMIT C2240 0201 0.1UF X5R-CERM 16V 10% 0402 10% X7R 3900PF C2241 50V VIDEO: EDP SUPPORT & CONN SYNC_MASTER=J85 MLB_C SYNC_DATE=12/05/2012 155S0667 155S0583 RDAR://PROBLEM/8616060, RADAR://PROBLEM/9015335 L2242,L2810,L2811,L2812,L2813,L2814,L2710,L2711,L2712,L6030,L6031 EDP_DATA_EMI_CONN_P<0> EDP_DATA_EMI_CONN_N<0> EDP_DATA_EMI_CONN_P<1> EDP_DATA_EMI_N<1> EDP_DATA_EMI_P<1> EDP_AUX_EMI_N EDP_AUX_EMI_PEDP_AUX_P LCM_OFF_L EDP_DATA_N<1> EDP_DATA_N<0> EDP_DATA_P<0> EDP_DATA_N<2> PPVCC_MAIN_LCD_SW_CONN =PPLED_REG_A PPLED_BACK_REG_A GPIO_SOC2LCD_PWREN LCD_RAMP EDP_AUX_EMI_CONN_N EDP_AUX_EMI_CONN_P EDP_DATA_EMI_CONN_N<1> EDP_DATA_EMI_CONN_P<2> EDP_DATA_EMI_CONN_N<2> EDP_DATA_EMI_CONN_P<3> EDP_DATA_EMI_CONN_N<3> EDP_AUX_N EDP_DATA_EMI_P<0> EDP_DATA_EMI_N<0> EDP_DATA_EMI_N<2> EDP_DATA_P<1> EDP_DATA_EMI_P<2> EDP_DATA_EMI_P<3> EDP_DATA_P<2> EDP_DATA_N<3> EDP_DATA_P<3> PPVCC_MAIN_LCD_SW EDP_HPDEDP_HPD_2P5EDP_HPD_EMI PPVCC_MAIN_LCD_SW_CONN EDP_DATA_EMI_CONN_N<2> EDP_DATA_EMI_CONN_P<2> EDP_DATA_EMI_CONN_N<1> EDP_DATA_EMI_CONN_P<1> EDP_DATA_EMI_CONN_N<3>EDP_HPD_EMI EDP_AUX_EMI_CONN_P EDP_DATA_EMI_CONN_N<0> EDP_DATA_EMI_CONN_P<0> EDP_AUX_EMI_CONN_N EDP_DATA_EMI_CONN_P<3> LED_IO_5_A LED_IO_6_A LED_IO_4_A LED_IO_2_A LED_IO_3_A LED_IO_1_A PPLED_BACK_REG_A =PPVCC_MAIN_LCD GPIO_SOC2LCD_PWREN NC_U2201_5 GPIO_SOC2LCD_PWREN GATE2LCD_PWREN =PP1V8_SOC EDP_DATA_EMI_N<3> 051-0886 A.0.0 22 OF 121 18 OF 54 2 1 21 2 1 1 2 2 1 9 11 13 15 17 3 7 14 16 18 12 10 8 4 6 2 31 29 19 21 23 25 27 32 30 26 28 24 22 20 5 1 3334 3536 21 2 1 1 2 2 6 1 4 35 2 1 1 2 2 1 1 2 2 1 1 2 2 1 21 4 32 1 1 2 4 32 1 4 32 1 4 32 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 4 32 11 2 2 1 1 2 81 3 52 7 2 1 2 1 53 53 18 52 54 18 52 53 53 53 53 53 18 18 54 4571054 53
  • 20. OUT OUT OUT IN IN IN VSS VSS RESET* P0_10 P0_9 P0_8 P0_7 P0_4 P0_5 P0_3 P0_2 P0_1 P0_0 DBGEN P0_20 P0_21 P0_22 P0_18 P0_19 P0_15 P0_17 P0_16 P0_14 P0_12 P0_11 VDDC VDDIO VDDC P0_13 P0_6 OUT IN IN BI IN IN OUT OUT OUT IN IN IN IN IN OUT OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT RDAR://PROBLEM/12580012 COMPARE SENSOR CONNECTIONS WITH N51, IDENTIFY AND UNDERSTAND DIFFERENCES REVIEW: N51 HAS OSCAR I2C CONNECTED TO RF CAM I2C OSCAR CORE = 1.2V HIBERNATE (NEED TO RUN IN S2R) APN 337S4416 NOTE: I2C1 IS ASSUMED TO USE PUSH-PULL INSTEAD OF OPEN-DRAIN OSCAR REVIEW:NEED PU ON CS? RDAR://PROBLEM/12579997 OSCAR VDDIO = 1.8V HIBERNATE (NEED TO WAKE HOST) 28 44 52 28 44 52 21 21 MF 5% 15.0 01005 1/32W R2405 R2406 MF 1/32W 5% 15.0 01005 21 5 MF 1/32W 0.00 0% R2450 01005 CRITICAL WLCSP U2400 LPC18A1UK-CPA1 0201-1 6.3V X5R 20% 1.0UF C2400 X5R 6.3V 1.0UF 20% 0201-1 C2401 5% 100K R2400 01005 1/32W MF 5 53 5 53 5 5 48 52 5 548 5 21 21 21 21 21 21 21 21 SENSOR: OSCAR SYNC_MASTER=J72_MLB_C SYNC_DATE=11/26/2012 GPIO_OSCAR_RESET_L GPIO_SOC2OSCAR_DBGEN TP_OSCAR_P0_22 GPIO_SOC2OSCAR_DBGEN_R SPI_OSCAR_MISO SPI_OSCAR2ACCEL_CS_L SPI_OSCAR2GYRO_CS_L =PP1V2_S2R_OSCAR UART4_OSCAR2SOC_RXD I2C1_SOC2OSCAR_SWDCLK_1V8 OSCAR2RADIO_CONTEXT_A OSCAR2RADIO_CONTEXT_B SPI_OSCAR_SCLK SPI_OSCAR_MOSI I2C1_SOC2OSCAR_SWDIO_1V8 PMU_GPIO_OSCAR2PMU_HOST_WAKE OSCAR_TIME_SYNC_HOST_INT SPI_OSCAR2COMPASS_CS_L COMPASS2OSCAR_INT ACCEL2OSCAR_INT2 GYRO2OSCAR_INT1 GYRO2OSCAR_INT2 ACCEL2OSCAR_INT1 =PP1V8_S2R_OSCAR SPI_OSCAR_MOSI_R =PP1V8_S2R_OSCAR SPI_OSCAR_SCLK_R UART4_SOC2OSCAR_TXD PMU_GPIO_CLK_32K_OSCARNC_ISP0_CAM_REAR_SDA NC_ISP0_CAM_REAR_SCL 051-0886 A.0.0 24 OF 121 19 OF 54 1 2 1 2 1 2 D6 B1 E4 A2 A3 E1 D4 D5 E2 C5 E6 E5 E3 D2 B6 D1 A6 C3 C4 B4 B5 A5 B3 B2 A1 C1 C2 C6 A4 D3 2 1 2 1 1 2 54 19 54 1954
  • 21. IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND OUT IN BI IN BI OUT IN IN OUT OUT OUT SYM_VER-2 SYM_VER-2 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT ISP1_CAM_FRONT_SHUTDOWN_L HIGH = TURN ON CAMERA LOW = SHUT DOWN CAMERA VGA FRONT CAMERA CONNECTOR 516S0876 RCPT MLB 516S0869 PLUG FLEX F-ST-SM 503548-1820 CRITICAL J2601 10% 01005 6.3V X5R-CERM 1000PF C2602 X5R 1UF 6.3V 0201 20% C2601 0201 240OHM-350MA L2600 C2600 5% 16V 56PF 01005 NP0-C0GSM XW2600 R2601 1/32W MF 01005 1% 100K 1208 U2601400MHZ-0.1A-27PF X5R-CERM 1000PF 01005 10% 6.3V C2605 0201 20% 6.3V 1UF X5R C2604 56PF C2603 5% NP0-C0G 16V 01005 6.3V 10% 1000PF 01005 X5R-CERM C2608 1UF 0201 20% 6.3V X5R C2607 5% 16V 56PF C2606 01005 NP0-C0G 1208 400MHZ-0.1A-27PF U2600 7 53 0201 240OHM-350MA L2601 240-OHM-0.2A-0.8-OHM 0201-2 L2602 752 752 752 522 5 522 752 7 53 7 53 7 53 90-OHM-50MA TCM0605-1 L2610 90-OHM-50MA TCM0605-1 L2611 150OHM-25%-200MA-0.7DCR 01005 L2660 SYNC_DATE=12/03/2012SYNC_MASTER=J85 MLB_C CAMERA: FF-ALS CONN & FILTERS ISP1_CAM_FRONT_SHUTDOWN_L_F I2C3_SCL_1V8_F GPIO_ALS_IRQ_L_F PP1V8_CAM_FRONT_FILT ISP1_CAM_FRONT_SHUTDOWN_L I2C3_SCL_1V8 GPIO_ALS_IRQ_L I2C3_SDA_1V8 ISP1_CAM_FRONT_CLK ISP1_CAM_FRONT_SDA ISP1_CAM_FRONT_SCL =PP3V0_ALS =PP1V8_CAM_FRONT ISP1_CAM_FRONT_CLK_F I2C3_SDA_1V8_F ISP1_CAM_FRONT_SCL_F ISP1_CAM_FRONT_SDA_F =PP2V9_CAM_FRONT MIPI1C_CAM_FRONT_CLK_FILT_N MIPI1C_CAM_FRONT_CLK_FILT_P MIPI1C_CAM_FRONT_DATA_FILT_N<0> MIPI1C_CAM_FRONT_DATA_FILT_P<0> GPIO_ALS_IRQ_L_F I2C3_SCL_1V8_F I2C3_SDA_1V8_F ISP1_CAM_FRONT_CLK_F_R ISP1_CAM_FRONT_SHUTDOWN_L_F ISP1_CAM_FRONT_SDA_F ISP1_CAM_FRONT_SCL_F PP2V9_AVDD_CAM_FRONT_FILT GND_AVDD_CAM_FRONT PP1V8_CAM_FRONT_FILT PP3V0_ALS_FILT ISP1_CAM_FRONT_CLK_F_R ISP1_CAM_FRONT_CLK_F MIPI1C_CAM_FRONT_DATA_FILT_N<0> MIPI1C_CAM_FRONT_DATA_FILT_P<0> MIPI1C_CAM_FRONT_DATA_P<0> MIPI1C_CAM_FRONT_DATA_N<0> MIPI1C_CAM_FRONT_CLK_FILT_N MIPI1C_CAM_FRONT_CLK_FILT_P MIPI1C_CAM_FRONT_CLK_P MIPI1C_CAM_FRONT_CLK_N NC_U2601_5NC_U2601_1 PP3V0_ALS_FILT GND_AVDD_CAM_FRONT VOLTAGE=0V NET_SPACING_TYPE=GND MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.15 MM PP2V9_AVDD_CAM_FRONT_FILT MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR VOLTAGE=2.9V 051-0886 A.0.0 26 OF 121 20 OF 54 6 21 17 15 13 11 9 7 5 3 12 4 8 10 12 14 16 18 1920 22 2 1 2 1 21 2 1 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 21 21 4 32 1 4 32 1 21 20 20 20 20 54 54 20 20 20 20 54 2053 2053 2053 2053 20 20 20 20 20 20 20 20 20 20 20 20 20 2053 2053 2053 2053 20 20 20
  • 22. OUT IN IN IN IN OUT OUT IN OUT IN IN IN OUTDRDY SCL/SK SDA/SI VDD RSV SO VSS TST1 TRG VID CAD0 CAD1 RST* CSB* INT2 DEN INT1 GND CS SDO/SA0 SDA/SDI/SDO SCL/SPC VDD_IO DRDY/ RES2 RES1 RES0 VDD RES/VDD CAP GND INT2 INT1 RES RES RES CS RES RES SDO/SA0 SCL/SPC SDA/SDI/SDO VDD VDD_IO GND OUT IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 11V CHARGE PUMP COMPASS TO VID WHEN NOT USED APN 338S1014 TIE CSB* TO VID FOR I2C MODE GYRO ACCELEROMETER MF 1/32W 01005 0.00 0% R2727 19 0% 0.00 MF 1/32W 01005 R2757 19 21 19 21 C2701 20% 6.3V 01005 0.1UF X5R-CERM C2700 CERM-X5R 6.3V 20% 10UF 0402-2 19 21 120-OHM-25%-250MA-0.5DCR 01005 L2700 19 19 19 20% 6.3V C2725 0.1UF X5R-CERM 010050402-2 10UF CERM-X5R 6.3V 20% C2723 19 21 20% 6.3V C2721 0.1UF X5R-CERM 01005 01005 120-OHM-25%-250MA-0.5DCR L2702 19 21 01005 MF 1/32W 15.0 5% R2747 01005 L2741 120-OHM-25%-250MA-0.5DCR 19 21 19 21 C2726 0.1UF 0201 10% 16V X5R-CERM OMIT 19 19 C2711 6.3V 01005 20% X5R-CERM 0.1UF C2710 6.3V 20% X5R 0201-1 1.0UF XW2700 SHORT-10L-0.25MM-SM CSP U2710 AK8963C CRITICAL 01005 120-OHM-25%-250MA-0.5DCR L2701 CKPLUS_WAIVE=PWRTERM2GND CRITICAL AP3GDL20HAB18TR U2720 LGA OMIT MF 1/32W 0.00 0% R2750 01005 SHORT-10L-0.25MM-SM XW2701 X5R-CERM 0.1UF 01005 6.3V 20% C2750 OMIT AP2DHAB26TR CRITICAL U2700 LGA 19 19 SYNC_DATE=N/ASYNC_MASTER=N/A SENSOR: ACCEL, COMPASS, GYRO NO_TEST=TRUENC_COMPASS_TST1 GND_COMP GYRO_DEN SPI_OSCAR_MISO_GYRO PP3V0_COMP GYRO_RES_VDD GYRO2OSCAR_INT1 SPI_OSCAR2GYRO_CS_L SPI_OSCAR_MOSI SPI_OSCAR_SCLK =PP1V8_S2R_GYRO GYRO2OSCAR_INT2 PP3V0_GYRO GYRO_PUMP SPI_OSCAR_MISO =PP3V0_S2R_ACCEL SPI_OSCAR_MISO =PP3V0_S2R_GYRO =PP3V0_S2R_COMP SPI_OSCAR2COMPASS_CS_L PP1V8_COMP NO_TEST=TRUENC_COMPASS_TRG SPI_OSCAR_MISO_COMP1NC_COMPASS_RSV NO_TEST=TRUE SPI_OSCAR_MOSI SPI_OSCAR_SCLK COMPASS2OSCAR_INT =PP1V8_S2R_COMP SPI_OSCAR_MISO PP1V8_COMP GND_COMP GND_COMP =PP1V8_S2R_ACCELPP3V0_ACCEL SPI_OSCAR_MOSI SPI_OSCAR_SCLK SPI_OSCAR_MISO_ACCEL SPI_OSCAR2ACCEL_CS_L ACCEL2OSCAR_INT2 ACCEL2OSCAR_INT1 051-0886 A.0.0 27 OF 121 21 OF 54 1 2 1 2 2 1 2 1 21 2 1 2 1 2 1 21 1 2 21 2 1 2 1 2 1 21 A1 A3 A4 B1 B3 B4 C1 C2 C3 C4 D1 D2 D4 A2 21 8 7 13 5 4 3 2 1 6 11 10 9 16 15 14 12 1 2 2 1 5 6 13 14 12 4 11 10 3 1 2 8 7 9 21 54 19 21 54 19 21 54 54 21 5421 21 21 54
  • 23. ADD0 SCLK CIN1 CIN3 CIN4 CIN12 CIN11 CIN6 CIN9 CIN8 CIN10 CIN2 CIN5 CIN0 ACSHIELD GND BIAS SDA VDRIVEVCC ADD1 INT* GPIO CIN7 TPNC NC NC NC NC NC NC NC NC NC BI IN OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 516S0872 PROX SENSOR CHOSE CIN NUMBERS FOR LAYOUT EASE PCB: ENSURE ACSHIELD PLANE UNDER VDRIVERAIL READ: 0X59, WRITE: 0X58 353S2964 CONNECTED TO MLB INTERCONNECT. THEREFORE,PROX GPIO IS NOT PROX GPIO WILL NOT BE USED. INT IS 1.8V LEVEL. 1.8 MA MAX 0.5 PF REF CAP TO MEASURE NEED EXTERNAL JUST IN CASE U3200, NO GND PLANE NEAR PROX_CIN NETS.. INT* IS OPEN DRAIN PU RAIL MATCH VDRIVE VDRIVE FOR: I2C AND GPIO CIN9 SENSOR ELECTRODE CIN7 DUMMY AND ALSO TIE TO CONNECTOR. A PLANE UNDER PROX_CIN NETS PCB: ACSHIELD NEEDS TO BE I2C ADDRESS: 0101100+R/W PROX C2804 6.3V 0.1UF X5R-CERM 20% 01005 PROX C2805 68PF 5% 6.3V NP0-C0G 01005 PROX R2800 MF 2.0K 1/32W 1% 01005 PROX R2801 MF 100K 1% 1/32W 01005 PROX 0201 0.01UF C2802 10% 10V X5R-CERM PROX C2800 X5R 402 10% 6.3V 2.2UF PROX C2803 +/-0.05PF 201 CERM 25V 0.5PF PROX C2801 0.1UF 6.3V X5R-CERM 20% 01005 PROX C2806 5% 68PF 6.3V NP0-C0G 01005 PROX C2807 NP0-C0G 201 25V 27PF 1% PROX U2800 WLCSP AD7149 CRITICAL PROX L2801 68NH-2%-320MA-1.0OHM 0402 CRITICAL PROX CRITICAL L2807 68NH-2%-320MA-1.0OHM 0402 PROX CRITICAL 0603 L2808 390NH-2%-170MA-4.0OHM PROX 0603 L2802 CRITICAL 390NH-2%-170MA-4.0OHM PROX L2803 68NH-2%-320MA-1.0OHM 0402 CRITICAL PROX 0603 L2804 CRITICAL 390NH-2%-170MA-4.0OHM 520 PROX 0201-2 240-OHM-0.2A-0.8-OHM L2800 520 PROX J2800 503548-0620 CRITICAL F-ST-SM 5 SENSOR: PROX SYNC_MASTER=J85 MLB_C SYNC_DATE=12/05/12 ACSHIELD_SB NC_J2800_6 NC_J2800_2 NC_J2800_4 PROX_CIN9_CONN PROX_ACSHIELD_CONN =PP1V8_PROX PP3V0_SENSOR_PROX_FILT I2C3_SCL_1V8 PROX_GPIO PROX_CIN9 CIN9 ACSH_SB PROX_CIN1 TP_PROX_CIN2 PROX_CIN7 CIN7 GPIO_PROX_IRQ_L =PP3V0_PROX I2C3_SDA_1V8 PROX_CIN7_CONN PROX_BIAS =PP1V8_PROX 051-0886 A.0.0 28 OF 121 22 OF 54 2 1 2 1 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 D1 C1 A3 A4 C3 E5 D5 B4 C5 C4 D4 B3 A5 D3 E4 E2 E3 E1 C2 D2 B1 A1 A2 B5 B2 2 1 2 12 1 2 1 2 12 1 2 1 8 21 109 3 4 5 6 7 2254 54 2254
  • 24. BI IN IN SYM_VER-2 SYM_VER-2 SYM_VER-2 OUT OUT OUT OUT OUT OUT IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT REAR CAMERA CONNECTOR APN: 516S0973 PLUG: 516S0974 X5R-CERM 10% 01005 6.3V 1000PF C2902C2901 402 1UF 10% 10V X5R 5% 16V C2900 56PF 01005 NP0-C0G L2900 240OHM-350MA 0201 752 6.3V X5R-CERM 10% 1000PF 01005 C2905C2904 10% 402 1UF 10V X5R 16V 5% 56PF NP0-C0G 01005 C2903 240OHM-350MA 0201 L2901 C2908 10% 01005 X5R-CERM 6.3V 1000PF C2907 X5R 10V 1UF 402 10%5% 16V 56PF NP0-C0G C2906 01005 240OHM-350MA 0201 L2902 10% C2911 X5R-CERM 6.3V 1000PF 01005 1UF 10V 402 10% X5R C2910 16V 5% 56PF NP0-C0G 01005 C2909 240OHM-350MA 0201 L2903 752 C2970 5% 56PF NP0-C0G 16V 01005 5% 16V 56PF 01005 NP0-C0G C2971 16V 5% NP0-C0G C2972 56PF 01005 C2973 16V 5% NP0-C0G 56PF 01005 F-ST-SM AA07-S022VA1 J2950 CRITICAL 7 52 90-OHM-50MA TCM0605-1 L2910 TCM0605-1 L2911 90-OHM-50MA 90-OHM-50MA TCM0605-1 L2912 7 53 7 53 7 53 7 53 7 53 7 53 XW2950SM XW2951SM 150OHM-25%-200MA-0.7DCR 01005 L2950 752 1000PF 6.3V 01005 10% X5R-CERM C2980R2950 01005 1/32W MF 100K 1% CAMERA: REAR CONN & FILTERS SYNC_MASTER=N/A SYNC_DATE=N/A =PP2V9_CAM_REAR CAM_REAR_VSYNC VOLTAGE=2.9V PP2V9_AVDD_CAM_REAR_FILT MIN_NECK_WIDTH=0.2 mm MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 mm NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=5 MM NET_SPACING_TYPE=GND MIN_NECK_WIDTH=0.1 MM VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm GND_CAM_AVDD =PP1V3_CAM_REAR =PP2V6_CAM_REAR_AF =PP1V8_CAM_REAR ISP0_CAM_REAR_CLK_F MIPI0C_CAM_REAR_CLK_FILT_P MIPI0C_CAM_REAR_DATA_FILT_P<0> MIPI0C_CAM_REAR_DATA_FILT_N<0> MIPI0C_CAM_REAR_DATA_FILT_P<1> MIPI0C_CAM_REAR_CLK_FILT_N MIPI0C_CAM_REAR_DATA_FILT_N<1> ISP0_CAM_REAR_CLK MIPI0C_CAM_REAR_DATA_N<0> MIPI0C_CAM_REAR_DATA_P<0> MIPI0C_CAM_REAR_CLK_N MIPI0C_CAM_REAR_CLK_P MIPI0C_CAM_REAR_DATA_N<1> MIPI0C_CAM_REAR_DATA_P<1> MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM PP2V6_CAM_REAR_AF_FILT VOLTAGE=2.6V GND_AF_AVDD MAX_NECK_LENGTH=5 MM NET_SPACING_TYPE=GND MIN_NECK_WIDTH=0.1 MM VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm PP1V8_CAM_REAR_FILT ISP0_CAM_REAR_SDA ISP0_CAM_REAR_SCL ISP0_CAM_REAR_SHUTDOWN_L PP1V3_CAM_REAR_FILT 051-0886 A.0.0 29 OF 121 23 OF 54 2 1 2 1 2 1 21 2 1 2 1 2 1 21 2 1 2 1 2 1 21 2 1 2 1 2 1 21 2 1 2 1 2 1 2 1 25 26 24 23 22 20 18 16 10 14 12 8 6 4 2 21 19 17 15 7 9 11 13 5 3 1 4 32 1 4 32 1 4 32 1 1 2 1 2 21 2 1 1 254 54 54 54 53 53 53 53 53 53
  • 25. PP PP PP PP PP PP PP PP PP PP OUT OUT IN OUT OUT OUT OUT IN OUT OUT OUT OUT BI BI IN OUT IN IN IN OUT OUT IN OUT IN IN OUT OUT OUT IN IN OUT BI BI Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST GPIO53/BOOT_CONFIG_1 SIM CARD ESD PROTECTION 48 PROBE POINTS GPIO48/BOOT_CONFIG_6 DEBUG CONNECTOR BOOT_HSIC_OPTION BOOT_NAND_OPTION SW REGISTER GPIO53/BOOT_CONFIG_1 GPIO48/BOOT_CONFIG_6 ENABLE SAHARA PROTOCOL BOOT_USB_OPTION 0X03 BOOT_DEFAULT_OPTION BOOT OPTIONS 0X00 0X01 0X08 47 X 0X02 VALUE X X X 6 GPIO/BOOT_CONFIG CONFIGURATION 0 1 1 1 1 0 0 1 0 X X X 0 0 0 0 000 0 0 5 49 0 34 0 50 0 51 1 0 100 1 10 0 52 2 53 0 54 0 1 0 X X X X 55 0 BOOT_CONFIG X AP INTERFACE & DEBUG CONNECTORS GPIO51/BOOT_CONFIG_3 GPIO54/BOOT_CONFIG_0 SM P4MM PP3002 P4MM SM PP3001 SM P4MM PP3000 NOSTUFF F-ST-SM MM4829-2702 J3001 NOSTUFF F-ST-SM MM4829-2702 J3002 P4MM SM PP3009 SM P4MM PP3008 SM P4MM PP3010 P4MM SM PP3011 SM P4MM PP3012 SM P4MM PP3013 SM P4MM PP3003 NOSTUFF 10K MF 01005 5% 1/32W R3002 NOSTUFF 5% 10K 1/32W MF 01005 R3003 28 2428333940 284852 283940 14242852 2752 52752 52752 52752 52752 52752 2752 27 27 2627 264852 NOSTUFF M-ST-SM AXE654124 J3003 5 28 5 28 5 28 27 48 52 5 28 5 28 5 11 28 52 28 5 11 28 52 4 8 10 11 48 52 52652 2652 25 33 34 35 36 37 38 54 24 25 27 28 30 52 5 26 52 115253 NOSTUFF SHORT-10L-0.25MM-SM XW3002 NOSTUFF SHORT-10L-0.25MM-SM XW3003 115253 CELL 12V-33PF01005-1 C3000 CELL ESD0P2RF-02LS TSSLP-2-1 U3001 CELL TSSLP-2-1 ESD0P2RF-02LS U3000 CELL TSSLP-2-1 ESD0P2RF-02LS U3003 CELL TSSLP-2-1 ESD0P2RF-02LS U3002 CELL:AP INTERFACE & DEBUG CONNECTORS UART3_BB2SOC_RTS_L PMU_GPIO_BB_VBUS_DET PMU_GPIO_BB2PMU_HOST_WAKE GPIO_51 ANT_SEL_1 ANT_SEL_2 LAT_SW1_CTL BB_JTAG_RTCLK BB_JTAG_TDI BB_JTAG_TDO BB_JTAG_TCK BB_JTAG_TRST_L BB_JTAG_TMS DEBUG_RST_L USB_BB_DEBUG_P USB_BB_DEBUG_N PMIC_RESOUT_L PMU_GPIO_PMU2BBPMU_RST_L HSIC2_SOC2BB_HOST_RDY GPIO_BB2SOC_RESET_DET_L HSIC2_BB2SOC_DEVICE_RDY UART3_SOC2BB_RTS_L UART3_SOC2BB_TX UART3_BB2SOC_TX RESET_SOC_L CKPLUS_WAIVE=SINGLE_NODENET GPIO_SOC2BB_RADIO_ON_L PS_HOLD_PMIC =PPBATT_VCC_BB PP_SMPS3_MSME_1V8 GPIO_SOC2BB_RST_L USB_BB_N USB_BB_P GPIO_DEBUG_LED SIM_TRAY_DETECT SIMCRD_CLK_CONN SIMCRD_IO_CONN SIMCRD_RST_CONN PP_LDO6_RUIM_1V8 UART_BB2WLAN_LTE_COEX SLEEP_CLK_32K WTR_SSBI_PRX_DRX WTR_RF_ON 19P2M_MDM PMIC_SSBI BB_ERROR_FLAG LAT_SW1_CTL PP_SMPS3_MSME_1V8 WTR_SSBI_TX_GPS WTR_RX_ON HSIC2_BB_DATA HSIC2_BB_STB UART_WLAN2BB_LTE_COEX ANT_SEL_1 051-0886 A.0.0 30 OF 121 24 OF 54 1 1 1 4 2 3 1 4 2 3 1 1 1 1 1 1 1 1 1 2 1 2 50 42 44 46 48 32 34 36 38 40 26 22 24 28 30 16 14 12 18 20 2 10 8 6 4 49 47 45 43 41 33 31 29 27 25 23 21 35 37 39 7 5 3 1 19 17 15 9 11 13 52 54 51 53 55 58 57 56 21 21 1 2 21 21 2 1 2 1 10 28 52 10 28 52 102852 102852 10 25 27 52 28 44 26 27 28 29 28 29 26 27 26 27 28 14242852 24 25 27 28 30 52 28 29 28 29 4 27 53 4 27 53 28 44 2428333940
  • 26. IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN VDD_S4 VSW_S5 VSW_S3 VSW_S2 VREG_XO VREG_S5 VREG_S4 VREG_RFCLK VREG_L9 VREG_L8 VREG_L7 VREG_L6 VREG_L5 VREG_L4 VREG_L3 VREG_L2 VREG_L14 VREG_L13 VREG_L12 VREG_L11 VREG_L10 VOUT_LVS1 VDD_XO VDD_S5 VDD_S2 VDD_S1 VDD_L9 VDD_L8 VDD_L7 VDD_L5_L6_L13_L14 VDD_L4 VDD_L2_L3 VDD_L12 VDD_L10_L11 REF_GND REF_BYP VSW_S5_2 VREG_S3 VSW_S4 VDD_S3 VSW_S1 VREG_S1 VREG_S2 VREG (SYM 5 OF 5) OUT OUT OUT OUT OUT OUT OUT OUT OUT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT INTERNAL USE ONLY INTERNAL USE ONLY PMU (1 OF 2) 2433343536373854 4.7UF 20% 0402 10V X5R-CERM C3204 X5R-CERM 0402 10V 20% 4.7UF C3205 4.7UF 20% 10V 0402 X5R-CERM C3206 X5R-CERM 4.7UF 10V 20% 0402 C3207 0402 X5R-CERM 10V 20% 4.7UF C3208 SHORT-10L-0.1MM-SM XW3200 X5R-CERM 6.3V 20% 0.1UF 01005 C3209 41 27 0402-2 20% 6.3V CERM-X5R 10UF C3200 26 27 2.2UH-20%-2.34A-0.113OHM 2520-SM CRITICAL L3204 2.2UH-20%-1.2A-0.15OHM 0806 CRITICAL L3203 22UF 6.3V X5R-CERM-1 603 20% C3224 22UF 20% 6.3V X5R-CERM-1 603 C3225 2.2UH-20%-1.2A-0.15OHM CRITICAL 0806 L3202 0806 2.2UH-20%-1.2A-0.15OHM CRITICAL L3201 X5R-CERM-1 22UF 603 20% 6.3V C3226 22UF X5R-CERM-1 603 20% 6.3V C3228 X5R-CERM-1 603 20% 22UF 6.3V C3229 25 52 27 25 30 52 NOSTUFF 4V X5R 01005 20% 0.1UF C3227 24 25 27 28 30 52 27 30 0806 2.2UH-20%-1.2A-0.15OHM CRITICAL L3200 1.0UF 6.3V X5R 20% 0201-1 C3230 27 52 27 2552 253052 242527283052 BGA PM8018-0 CRITICAL U3300 27 27 27 27 0402-2 6.3V CERM-X5R 20% 10UF C3201 27 27 14 32 33 39 40 27 10 24 27 52 6.3V X5R 1.0UF 20% 0201-1 C3210 6.3V 20% X5R 1.0UF 0201-1 C3212 1.0UF X5R 20% 6.3V 0201-1 C3214 20% 6.3V X5R 1.0UF 0201-1 C3217 X5R 20% 6.3V 1.0UF 0201-1 C3211 1.0UF X5R 6.3V 20% 0201-1 C3213 6.3V 20% X5R 1.0UF 0201-1 C3215 20% X5R 1.0UF 6.3V 0201-1 C3216 0402-2 CERM-X5R 20% 6.3V 10UF C3202 1.0UF X5R 6.3V 20% 0201-1 C3219 10UF 0402-2 CERM-X5R 20% 6.3V C3221 0402-2 CERM-X5R 10UF 6.3V 20% C3223 0402-2 6.3V 20% 10UF CERM-X5R C3218 0402-2 CERM-X5R 10UF 6.3V 20% C3220 10UF 20% 6.3V CERM-X5R 0402-2 C3222 1.0UF 6.3V X5R 20% 0201-1 C3231 01005 5% 56PF NP0-C0G 16V C3203 CELL: BASEBAND PMU (1 0F 2) S1_GND S2_GND S3_GND S4_GND S5_GND PP_LDO4_VDDA_3V3 PP_LDO5_GPS_LNA_2V5 PP_LDO1 REF_BYP PP_LDO3_AMUX_1V8 PP_LDO2_XO_HS_1V8 S5_GND PP_SMPS5_DSP_1V05 S4_GND S3_GND S2_GND S1_GND PP_LVS1 PP_VREG PP_SMPS4_RF2_2V05 PP_SMPS3_MSME_1V8 PP_SMPS5_DSP_1V05 PP_LDO6_RUIM_1V8 PP_LDO14_2V65 PP_LDO13_VDDPX_2V95 PP_LDO7_DAC_1V8 PP_LDO8_VDDPX_1V2 PP_LDO12_MDSP_SW_1V05 PP_LDO9_PLL_1V05 PP_LDO11_MDSP_FW_1V05 PP_LDO10_ADSP_1V05 PP_SMPS1_MSMC_1V05 PP_VSW_S1 REF_GND PP_VSW_S2 PP_SMPS2_RF1_1V3 PP_VSW_S3 =PPBATT_VCC_BB PP_SMPS4_RF2_2V05 PP_SMPS3_MSME_1V8 PP_VSW_S5 PP_VSW_S4 051-0886 A.0.0 32 OF 121 25 OF 54 2 1 2 1 2 1 2 1 2 1 21 2 1 2 1 1 2 21 2 1 2 1 21 21 2 1 2 1 2 1 2 1 21 2 1 98 24 88 82 87 48 42 90 20 76 105 13 77 54 63 17 11 84 32 31 29 23 43 55 65 53 8 101 89 95 104 70 58 75 5 78 44 64 59 34 28 100 12 81 18 6 92 97 79 83 1022 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 25 26 25 26 25 26 25 26 25 26 52 25 26 25 26 25 26 25 26 25 26
  • 27. IN OUT MPP_06 MPP_05 MPP_04 MPP_03 MPP_02 MPP_01 GPIO_06 GPIO_05 GPIO_04 GPIO_03 GPIO_02 GPIO_01 (SYM 4 OF 5) MPP MISC NC NC NC NC NC NC NC NC BI IN IN IN IN GND_S3 GND_S2 GND_S1 GND_S4 GND_S5 GND VCOIN (SYM 3 OF 5) INPUT PWR NC OPT_1 PM_RESIN_N KPD_PWR* BAT_ID LED_DRV_N OPT_2 PM_MDM_INT_N PM_USR_INT_N PON_RESET* PON_TRIG SSBI PS_HOLD (SYM 1 OF 5) CONTROL NC NC OUT OUT NC OUT IN NC NC OUT IN OUT OUT GND0 XTAL_32K_OUT XTAL_32K_IN XTAL_19M_OUT XTAL_19M_IN XOADC_GND XO_THERM XO_OUT_D0_EN XO_OUT_D0 XO_OUT_A1 XO_OUT_A0 SLEEP_CLK RSVD GND1 (SYM 2 OF 5) CLOCKS IN CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PMU (2 OF 2) 1 (1.8V) 0 (NC, PD) BB GPIO_29 JXX NXX BOARD_ID 1.3V 1.1V PRODUCT_ID PROTO1 PA_ID 0.3V 0.5V 1.1V 7.5 7.6 7.7 8.7 8.6 8.5 TO MINIMIZE THERMAL DRIFT GND NEEDS TO BE CLEARED UNDER THIS CRYSTAL 1.3V 0.1V AP SECTION NEEDS ITS OWN THERMISTOR PLACED NEAR THE PA’S. PVT DVT PROTO2 PROTO2 MAV VER 1.7V 1.5V EVT2 EVT1 0.7V 0.9V REVISION 1.5V1.5V 28 27 BGA CRITICAL PM8018-0 U3300 1% MF 01005 1/32W 100K R3304 1/32W 100K MF 1% 01005 R3305 2427 52452 28 244852 52452 20.0K 5% 01005 MF 1/32W R3301 1.00K 1/32W 01005 5% MF R3300 PM8018-0 BGA U3300 SM XW3304 SHORT-10L-0.25MM-SM XW3303 SM XW3302 SHORT-10L-0.25MM-SM XW3301 SM XW3300 PM8018-0 BGA U3300 28 28 24 27 252627 19.200MHZ 2.0X1.6-SM CRITICAL Y3300 24 27 27 24 27 29 SHORT-10L-0.1MM-SM XW3305 100K MF 1/32W 1% 01005 R3303 X5R-CERM 01005 10% 6.3V 1000PF C3300 PM8018-0 BGA U3300 MF 1/32W 1% 499K 01005 R3307 1% MF 1/32W 01005 100K R3306 252627 CELL: BASEBAND PMU (2 OF 2) VREF_DAC_BIAS VDDPX_BIAS GPIO_SOC2BB_RST_L S3_GND S4_GND S5_GND S1_GND S2_GND PMIC_SSBI PS_HOLD_PMIC PMU_GPIO_PMU2BBPMU_RST_L GPIO_SOC2BB_RADIO_ON_L PM_USR_IRQ_L PM_MDM_IRQ_L PMIC_RESOUT_L PP_LDO3_AMUX_1V8 19P2M_XTAL_OUT 19P2M_MDM 19P2M_CLK_EN SLEEP_CLK_32K 19P2M_XTAL_IN 19P2M_WTR XO_THERM_Y1 XO_GND PS_HOLD BOARD_ID PA_ID PP_LDO3_AMUX_1V8 051-0886 A.0.0 33 OF 121 26 OF 54 80 73 72 66 67 85 49 71 60 50 38 33 1 2 1 2 1 2 1 2 56 30 96 103 91 36 93 99 94 39 51 61 46 52 40 57 1 2 21 1 2 21 1 2 62 16 69 35 86 74 14 21 4 41 68 47 3 24 1 2 1 1 2 2 1 27 15 3 2 1 22 10 9 25 37 19 26 7 45 1 2 1 2 25 25 25 25 25 2452