1. TU2B-5
Electromagnetic Coupling Effects in RFCMOS Circuits
A.O.Adan, M. Fukumi, K. Higashi, T. Suyama', M. Miyamoto', M. Hayashi
IC Development Group, SHARP Corp., 26 13-1, Ichinomoto-cho, Tenri, Nara, JAPAN
'Advanced Research Labs., S H A R P Corp., 26 13-1, Ichinomoto-cho, Tenri, Nara, JAPAN
~bsrrucr: The electromagnetic isolation and interconnects and injection by well ties and pn
coupling characteristics of basic structures, namely diffusions. Fig. 1 shows the metal pad-to-pad
metal pads, spiral inductors, and spiral-transistors, structures and the measured magnitude of coupling
implemented in a corelogic CMOS process are
evaluated and modeled. The models provide design S1, versus frequency. The pad spacing and size are
guidelines on the isolation characteristics of guard-rings lOOum and lOOum x 100um, respectively. The metal
and shield layers for RF cross-talk suppression between pad is coupled to the substrate capacitively. These
circuit blocks. The importance of electromagnetic effects can be well modeled by the equivalent circuit
coupling to layout interconnectsis demonstrated. shown in Fig.2, where CO's are the ILD capacitances,
Rp, Cp are the substrate resistance and capacitance to
I. INTRODUCTION ground, and Rc, Cc are the substrate lateral coupling
resistance and capacitance, respectively. The guard
Integration of RF transceiver circuits in core ring and the P+ grounded layer underneath the pad
CMOS process is actively pursued [l] in an effort to modify the substrate resistances Rp. In Fig.1, using
increase functionality and reduce cost. In mixed mode different metal stacks varied the ILD capacitance
Logic-RF IC's digital switching noise coupled effect. Using a P+ grounded shield underneath the
through the substrate, as well as electromagnetic pad or a P+ guard ring are the most effective ways to
coupling (EMC) between RF circuit blocks is a suppress coupling. At 2GHz, --17dB reduction in S 1 2
concern, and several papers have reported these is achieved by the P+ grounded shield layer, as
effects [2,3]. However, solutions have been proposed compared with the non-shielded pad. As the model
like the use of deep trenches [2], or the use of SO1 shows, the guard ring and shielding layers act
substrate [4], which are not compatible with standard reducing EMC by shorting out the substrate
CMOS. resistances Rp. The extracted Rp values are 50R,
In this work, the measured and modeled RF 12R and 5R for the reference, the P+ guard ring and
interaction characteristics of basic structures, namely the P+ grounded shield, respectively.
metal pads, spiral inductors, and spiral-transistors,
implemented in a core-logic CMOS process are III. SPIRAL-TO-SPIRAL COUPLING
evaluated. Furthermore, the effects of shielding layers
(P+ diffusion) and guard rings are presented. These Planar spiral inductors occupy a large Si area and
simple test structures give insight in the coupling are widely used in RF circuits. The EMC of planar
mechanisms and allow the derivation of guidelines to spiral inductors must be modeled to determine the
reduce EMC effects. effect on gain and reverse isolation of amplifiers [3],
The experimental evaluation was conducted on a as well as between large signal circuit blocks (output
standard 0.25um, 4-level Metal, logic-CMOS process amp) and sensitive Low-Noise Amplifiers (LNA).
on IOR.cm p-type bulk wafers. The process features The spiral coupling was studied using the patterns in
standard twin-wells and Shallow Trench Isolation. Fig.3. The spiral inductors are lOOum separated and
have a length of 3810um, L=6.3nH, with metal width
11. PADS CAPACFIVE COUPLING and spacing of 15um and 5um, respectively. The
isolation effects of (1) a grounded P+ diffision-top
The simplest EM couplings to the substrate are due metal barrier in between the inductors and (2)
to capacitive interaction of metal pads or metal Salicided P+ grounded shield underneath one of the
293
0-7803-7246-8/02/$10.000 2002 IEEE 2002 IEEE Radio Frequency Integrated Circuits Symposium

2. ......
...... 50Q u--t T"
......
......M2 12R ...
...... Rc
..... P+Guard Ring
.....I ? I
..... ?
5R
...... .....
Frequency, f [GHz]
... P+Shield"'
Fig.2: Equivalent circuit model for metal pad
structures in Fig.1. The guard rings and P+
shield layers affect the substrate resistances Rpl,
Fig.1: EM coupling Szl between metal pads and Rp2 and Rc.
the effect of guard rings and P+ grounded shields.
The extracted substrate resistances Rp are indicated.
01 , , i I 1
I O
GND Separation : 0.1
v,
-
U
y -20
n
UJ
Y
-30
X
1.103
100
-40
Spacing, S [um]
50
Frequency,f [GHz]
Fig.3: Measured (symbols) and model calculated (lines) magnetic coupling k and S2, for EM coupling between planar
spiral inductors on bulk-Si 10R.m p-substrate. The spirals spacing is S=100um. The GND separation is a P+ grounded
diffusion-Top metal barrier between the spirals. The P+GND shield is a salicided P+ diffusion layer underneath the
right-side spiral.
Parameter Unit Reference GND P+GND
Separation Shield
L nH 6.3 c c
Rs R 8 c c
k 0.07 0.015 0.04
RPl R 29 28 25
RP2 R 29 28 3
cp fF 200 c c
Rc R 73 110 73
cc fF 10 1 10
Fig.4: Equivalent circuit for Spiral-to-Spiralcoupling. CO I fF I 320 I t t
Cf I fF I 20 I c c
294

3. inductors were evaluated to gain insight into the transistor transconductance. The coupling coefiiceint
coupling mechanisms. Fig.4 shows the proposed is k-0.05 as estimated from layout. At low
circuit model to analyze the EMC. In Fig.3, the frequencies, the Szl increases due to the magnetic
measured (symbols) and calculated (lines) frequency coupling, and the amplification action of the
response of Szl for the three structures, and the transistor. As frequency increases Szl decreases since
magnetic coupling factor k for the reference pair of the gate capacitance of the transistor, C , shorts the
,
spirals are reported. Good agreement is observed coupling to ground. As a result of the two behaviors
between the model results and measurements. The described by (I), a peak is seem in the Szl
model parameters are summarized in Table I. A characteristic. At further high frequencies, the
maximum Szl of --25dB is observed at 1.5 GHz for substrate-coupling path becomes dominant. The
the reference pattem. At low frequencies, magnetic substrate capacitively and resistively couples the
coupling (k) dominates spiral isolation. The grounded interference to the interconnect lines, the back gate of
P+ diffksion-top metal separation effectively reduces the transistor, and the drain-substrate capacitance of
SZIto -37dB at ISGHz. At high frequencies, the the transistor.
substrate coupling resistance (Rc) is dominant, These results clearly show how the transistor
however, a grounded shield undemeath the spiral action amplifies the coupled interference which
completely shorts out the coupling to S21=-40dB. results in Szl--20dB at ISGHz, i.e. stronger effect
From the model and the experimental results, the than in the passive spiral-spiral coupling of Fig.3.
effectiveness of each structure can be assessed. When the transistor is OFF (Id=OmA curve), the
capacitive coupling to the substrate (CO, Cdb) and
transmission through the substrate (Rc, Cc) are
Iv. SPIRAL-TO-TRANSISTOR
COUPLING similar to the effect reported in Fig.1 for the metal
pads EMC. This test structure demonstrates the
Due to its large area, the spiral inductor can couple importance of modeling EMC effects between
significant EM energy not only to other spirals but passive components; interconnect lines, and active
also to sensitive transistors. Fig.5 shows the new test circuits.
structure proposed to evaluate this effect. This
structure is used to emulate the situation that might V. CONCLUSION
arise, for example, in the interference between the
transmitter and receiver paths of a RF transceiver. Characterization and analysis of the EMC effects
Fig.6 illustrates the measured S21at the transistor’s of basic structures (metal pads, spiral-spiral and
drain terminal, and with bias current as parameter. spiral-to-transistor), implemented on a standard logic
is
The general shape of SQ-VS-f similar to that for the CMOS process on p-type bulk wafers, were
spiral-spiral coupling structure. An equivalent circuit described. Compared with previous reports, a
is proposed in the Fig.7. comprehensive equivalent circuit modeling was
The magnetic coupling between the spiral and the introduced and validated with measured data. The
layout parasitics of the transistor, especially the gate effect and effectiveness of different guard rings, and
bias interconnect line, can be studied using the P+ grounded shield layers were also studied. From
equivalent circuit model. When the substrate coupling these results, it is observed that not only the substrate,
is neglected (Rp=O, Cc=O, Rc 3 00 ), but also the electromagnetic coupling to layout
interconnect must be considered in the
0 3 0, characterization and minimization of EMC at radio
frequencies.
where L I , L2 and M = k a are the spiral
inductor, gate line parasitic inductance, and the
mutual inductance, respectively, and g, is the
295

4. Gate Bias 0 ..
....
.....e..
I
e e e a .
I U
s
....
9
CN
O
- ....
. . . . . ..
Frequency, f [GHz]
Fig.5: Test pattem to evaluate Spiral-Transistor EM Fig.6: Measured coupling Szl of the
coupling. Transistor: L=O.25um, W=60 fingers X Spiral-Transistor structure at different bias
5um. conditions.
Port, Port,
---E Fig.7: Proposed equivalent circuit of the
Cdb Spiral-Transistor coupling.
L,: Planar spiral inductance, L2: parasitic
inductance of the gate bias line, k magnetic
coupling factor, Rb: Transistor equivalent body
resistance, Cdb: transistor drain-substrate junction
capacitance. CO: Spiral to substrate (ILD)
capacitance, Rp, Cp: substrate resistance and
capacitance to ground, respectively, Rc, Cc:
substrate coupling resistance and capacitance,
Rc respectively.
Rb
REFERENCES
[I] H. Samavati, H.R. Rategh, and T.H. Lee, “A [3] A.L.L. Pun, T. Yeung, K. Lau, F.J.R.Clement, and
fully-integrated SGHz CMOS wireless-LAN receiver”, D.K. Su, “Substrate noise coupling through planar
ISSCC Dig. Tech. Papers, pp. 208-209, Feb. 2001. spiral inductor”, IEEE J. Solid-state Circuits, vo1.33,
[2] C.S.Kim, P. Park, J-W. Park, N. Hwang, and H.K. Yu, No.6, pp.877-884, Jun.1998.
“Deep trench guard technology to suppress coupling [4] J.S. Hamel, S. Stefanou, M. Bain, B.M. Armstrong, and
between inductors in silicon RF ICs”, IEEE MMT-S H.S. Gamble, “Substrate crosstalk suppression
Symposium Digest, 2001. capability of Silicon-on-Insulator substrates with buried
ground planes (GPSOI)”, IEEE Microwave and Guided
Wave Lett., vol.lO, No.4, pp. 134-135, Apr. 2000.
296