CC13x2, CC26x2 SimpleLink™ Wireless MCU manual.pdf

CC13x2, CC26x2 SimpleLink™ Wireless MCU
Technical Reference Manual
Literature Number: SWCU185D
October 2019

2 SWCU185D–October 2019
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Copyright © 2019, Texas Instruments Incorporated
Contents
Contents
Preface....................................................................................................................................... 70
1 Architectural Overview........................................................................................................ 73
1.1 Target Applications......................................................................................................... 74
1.2 Overview..................................................................................................................... 74
1.3 Functional Overview ....................................................................................................... 77
1.3.1 Arm®
Cortex®
-M4F................................................................................................. 77
1.3.2 On-Chip Memory .................................................................................................. 78
1.3.3 Radio................................................................................................................ 79
1.3.4 Security Core ...................................................................................................... 79
1.3.5 General-Purpose Timers ......................................................................................... 80
1.3.6 Direct Memory Access............................................................................................ 80
1.3.7 System Control and Clock ....................................................................................... 81
1.3.8 Serial Communication Peripherals.............................................................................. 81
1.3.9 Programmable I/Os ............................................................................................... 84
1.3.10 Sensor Controller ................................................................................................ 84
1.3.11 Random Number Generator .................................................................................... 85
1.3.12 cJTAG and JTAG ................................................................................................ 85
1.3.13 Power Supply System ........................................................................................... 86
2 Arm®
Cortex®
-M4F Processor............................................................................................... 88
2.1 Arm®
Cortex®
-M4F Processor Introduction.............................................................................. 89
2.2 Block Diagram .............................................................................................................. 89
2.3 Overview..................................................................................................................... 90
2.3.1 System-Level Interface ........................................................................................... 90
2.3.2 Integrated Configurable Debug.................................................................................. 90
2.3.3 Trace Port Interface Unit ......................................................................................... 91
2.3.4 Floating Point Unit (FPU)......................................................................................... 91
2.3.5 Memory Protection Unit (MPU).................................................................................. 91
2.3.6 Arm®
Cortex®
-M4F System Component Details ............................................................... 91
2.4 Programming Model ....................................................................................................... 92
2.4.1 Processor Mode and Privilege Levels for Software Execution .............................................. 92
2.4.2 Stacks............................................................................................................... 92
2.4.3 Exceptions and Interrupts ........................................................................................ 92
2.4.4 Data Types......................................................................................................... 93
2.5 Arm®
Cortex®
-M4F Core Registers....................................................................................... 93
2.5.1 Core Register Map ................................................................................................ 94
2.5.2 Core Register Descriptions ...................................................................................... 94
2.6 Instruction Set Summary................................................................................................. 108
2.6.1 Arm®
Cortex®
-M4F Instructions ................................................................................ 108
2.6.2 Load and Store Timings ........................................................................................ 114
2.6.3 Binary Compatibility With Other Cortex®
Processors ....................................................... 115
2.7 Floating Point Unit (FPU) ................................................................................................ 116
2.7.1 About the FPU ................................................................................................... 116
2.7.2 FPU Functional Description .................................................................................... 116
2.7.3 FPU Programmers Model....................................................................................... 121
2.8 Memory Protection Unit (MPU) ......................................................................................... 122

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SWCU185D–October 2019
Contents
2.8.1 About the MPU................................................................................................... 122
2.8.2 MPU Functional Description.................................................................................... 122
2.8.3 MPU Programmers Model ...................................................................................... 122
2.9 Arm®
Cortex®
-M4F Processor Registers............................................................................... 123
2.9.1 CPU_DWT_map1 Registers ................................................................................... 124
2.9.2 CPU_FPB_map1 Registers .................................................................................... 151
2.9.3 CPU_ITM_map1 Registers ..................................................................................... 162
2.9.4 CPU_SCS_map1 Registers .................................................................................... 203
2.9.5 CPU_TPIU_map1 Registers ................................................................................... 305
3 Memory Map .................................................................................................................... 318
3.1 Memory Map .............................................................................................................. 318
4 Arm®
Cortex®
-M4F Peripherals ........................................................................................... 320
4.1 Arm®
Cortex®
-M4F Peripherals Introduction........................................................................... 321
4.2 Functional Description.................................................................................................... 321
4.2.1 SysTick............................................................................................................ 322
4.2.2 NVIC............................................................................................................... 322
4.2.3 SCB................................................................................................................ 323
4.2.4 ITM................................................................................................................. 324
4.2.5 FPB ................................................................................................................ 324
4.2.6 TPIU ............................................................................................................... 324
4.2.7 DWT ............................................................................................................... 325
5 Interrupts and Events........................................................................................................ 326
5.1 Exception Model .......................................................................................................... 327
5.1.1 Exception States ................................................................................................. 327
5.1.2 Exception Types ................................................................................................. 328
5.1.3 Exception Handlers.............................................................................................. 330
5.1.4 Vector Table...................................................................................................... 330
5.1.5 Exception Priorities .............................................................................................. 331
5.1.6 Interrupt Priority Grouping ...................................................................................... 331
5.1.7 Exception Entry and Return .................................................................................... 332
5.2 Fault Handling............................................................................................................. 334
5.2.1 Fault Types ....................................................................................................... 334
5.2.2 Fault Escalation and Hard Faults.............................................................................. 335
5.2.3 Fault Status Registers and Fault Address Registers........................................................ 335
5.2.4 Lockup............................................................................................................. 335
5.3 Event Fabric ............................................................................................................... 336
5.3.1 Introduction ....................................................................................................... 336
5.3.2 Event Fabric Overview .......................................................................................... 337
5.4 AON Event Fabric ........................................................................................................ 338
5.4.1 Common Input Event List....................................................................................... 338
5.4.2 Event Subscribers ............................................................................................... 338
5.5 MCU Event Fabric ........................................................................................................ 339
5.5.1 Common Input Event List....................................................................................... 339
5.5.2 Event Subscribers ............................................................................................... 343
5.6 AON Events ............................................................................................................... 344
5.7 Interrupts and Events Registers ........................................................................................ 344
5.7.1 cc26_aon_event_AON_EVENT_RMAP Registers .......................................................... 345
5.7.2 cc26_event_fabric_map1 Registers ........................................................................... 361
6 JTAG Interface ................................................................................................................. 487
6.1 Top-Level Debug System................................................................................................ 488
6.2 cJTAG ...................................................................................................................... 490
6.2.1 cJTAG Commands .............................................................................................. 492

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Contents
6.2.2 Programming Sequences....................................................................................... 494
6.3 ICEPick..................................................................................................................... 495
6.3.1 Secondary TAPs ................................................................................................. 496
6.3.2 ICEPick Registers ............................................................................................... 497
6.3.3 Router Scan Chain .............................................................................................. 500
6.3.4 TAP Routing Registers ......................................................................................... 501
6.4 ICEMelter .................................................................................................................. 505
6.5 Serial Wire Viewer (SWV) ............................................................................................... 506
6.6 Halt In Boot (HIB) ......................................................................................................... 506
6.7 Debug and Shutdown .................................................................................................... 506
6.8 Debug Features Supported Through WUC TAP ..................................................................... 507
6.9 Profiler Register........................................................................................................... 507
6.10 Boundary Scan............................................................................................................ 509
7 Power, Reset, and Clock Management (PRCM)..................................................................... 512
7.1 Introduction ................................................................................................................ 513
7.2 System CPU Mode ....................................................................................................... 514
7.3 Supply System ............................................................................................................ 514
7.3.1 Internal DC/DC Converter and Global LDO .................................................................. 514
7.4 Digital Power Partitioning ................................................................................................ 515
7.4.1 MCU_VD.......................................................................................................... 517
7.4.2 AON_VD .......................................................................................................... 517
7.5 Clock Management ....................................................................................................... 517
7.5.1 System Clocks ................................................................................................... 517
7.5.2 Clocks in MCU_VD .............................................................................................. 520
7.5.3 Clocks in AON_VD .............................................................................................. 522
7.6 Power Modes.............................................................................................................. 522
7.6.1 Start-Up State .................................................................................................... 523
7.6.2 Active Mode ...................................................................................................... 523
7.6.3 Idle Mode ......................................................................................................... 523
7.6.4 Standby Mode.................................................................................................... 524
7.6.5 Shutdown Mode.................................................................................................. 525
7.7 Reset ....................................................................................................................... 525
7.7.1 System Resets ................................................................................................... 525
7.7.2 Reset of the MCU_VD Power Domains and Modules ...................................................... 526
7.7.3 Reset of AON_VD ............................................................................................... 526
7.8 PRCM Registers .......................................................................................................... 526
7.8.1 OSC_DIG_map1 Registers..................................................................................... 527
7.8.2 cc26_prcm_cc26_prcm_registers Registers ................................................................. 548
8 Versatile Instruction Memory System (VIMS)........................................................................ 625
8.1 Introduction ............................................................................................................... 626
8.2 VIMS Configurations ..................................................................................................... 627
8.2.1 VIMS Modes...................................................................................................... 627
8.2.2 VIMS FLASH Line Buffers...................................................................................... 629
8.2.3 VIMS Arbitration.................................................................................................. 629
8.2.4 VIMS Cache TAG Prefetch..................................................................................... 629
8.3 VIMS Software Remarks................................................................................................. 629
8.3.1 FLASH Program or Update..................................................................................... 630
8.3.2 VIMS Retention .................................................................................................. 630
8.4 ROM ........................................................................................................................ 631
8.5 FLASH...................................................................................................................... 631
8.5.1 FLASH Memory Protection ..................................................................................... 631
8.5.2 Memory Programming .......................................................................................... 632
8.5.3 FLASH Memory Programming ................................................................................. 632

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8.5.4 Power Management Requirements ........................................................................... 632
8.6 ROM Functions ........................................................................................................... 634
8.7 VIMS Registers ........................................................................................................... 634
8.7.1 CC26_FLASH_MMR_MMAP2 Registers ..................................................................... 635
8.7.2 CC26_VIMS_MMR_RMAP1 Registers ....................................................................... 762
9 SRAM.............................................................................................................................. 765
9.1 Introduction ................................................................................................................ 766
9.2 Main Features ............................................................................................................. 766
9.3 Data Retention ............................................................................................................ 766
9.4 Parity and SRAM Error Support ........................................................................................ 766
9.5 SRAM Auto-Initialization ................................................................................................. 766
9.6 Parity Debug Behavior .................................................................................................. 766
9.7 SRAM Registers .......................................................................................................... 766
9.7.1 cc26_mcu_sram_mmr_map_sram Registers ................................................................ 767
9.7.2 cc26_mcu_sram_mem_map_sram Registers................................................................ 772
10 Bootloader....................................................................................................................... 778
10.1 Bootloader Functionality ................................................................................................. 779
10.1.1 Bootloader Disabling ........................................................................................... 779
10.1.2 Bootloader Backdoor ........................................................................................... 779
10.2 Bootloader Interfaces..................................................................................................... 779
10.2.1 Packet Handling ................................................................................................ 780
10.2.2 Transport Layer ................................................................................................. 782
10.2.3 Serial Bus Commands ......................................................................................... 783
11 Device Configuration......................................................................................................... 794
11.1 Customer Configuration (CCFG) ....................................................................................... 795
11.2 CCFG Registers .......................................................................................................... 795
11.2.1 cc26_ccfg_mmap1 Registers ................................................................................. 796
11.3 Factory Configuration (FCFG) .......................................................................................... 825
11.4 FCFG Registers........................................................................................................... 825
11.4.1 cc26_fcfg1_mmap1 Registers ................................................................................ 826
12 Cryptography ................................................................................................................... 911
12.1 AES and Hash Cryptoprocessor Introduction ......................................................................... 912
12.2 Functional Description.................................................................................................... 912
12.2.1 Debug Capabilities ............................................................................................. 913
12.2.2 Exception Handling............................................................................................. 913
12.3 Power Management and Sleep Modes ................................................................................ 913
12.4 Hardware Description .................................................................................................... 914
12.4.1 AHB Slave Bus.................................................................................................. 914
12.4.2 AHB Master Bus ................................................................................................ 914
12.4.3 Interrupts......................................................................................................... 914
12.5 Module Description ....................................................................................................... 915
12.5.1 Introduction ...................................................................................................... 915
12.5.2 Module Memory Map........................................................................................... 915
12.5.3 DMA Controller ................................................................................................. 918
12.5.4 Master Control and Select Module ........................................................................... 921
12.5.5 AES Engine...................................................................................................... 922
12.5.6 Key Area Registers ............................................................................................ 926
12.6 AES Module Performance ............................................................................................... 927
12.6.1 Introduction ...................................................................................................... 927
12.6.2 Performance for DMA-Based Operations ................................................................... 928
12.7 Programming Guidelines................................................................................................. 928
12.7.1 One-Time Initialization After a Reset......................................................................... 928

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Contents
12.7.2 DMAC and Master Control .................................................................................... 929
12.7.3 Hashing .......................................................................................................... 930
12.7.4 Encryption and Decryption .................................................................................... 937
12.7.5 Exceptions Handling............................................................................................ 945
12.8 Conventions and Compliances.......................................................................................... 965
12.8.1 Conventions Used in This Manual............................................................................ 965
12.8.2 Compliance ...................................................................................................... 966
12.9 Cryptography Registers.................................................................................................. 966
12.9.1 cc26_eip120t1_hw2_0_mmap Registers .................................................................... 967
13 I/O Controller (IOC).......................................................................................................... 1068
13.1 Introduction............................................................................................................... 1069
13.2 IOC Overview............................................................................................................ 1069
13.3 I/O Mapping and Configuration........................................................................................ 1070
13.3.1 Basic I/O Mapping............................................................................................. 1070
13.3.2 Mapping AUXIOs to DIO Pins ............................................................................... 1070
13.3.3 Control External LNA/PA (Range Extender) With I/Os................................................... 1070
13.3.4 Map the 32-kHz System Clock (LF Clock) to DIO ........................................................ 1071
13.4 Edge Detection on DIO Pins........................................................................................... 1071
13.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT.............................. 1071
13.5 Unused I/O Pins ......................................................................................................... 1072
13.6 GPIO ...................................................................................................................... 1072
13.7 I/O Pin Capability........................................................................................................ 1073
13.8 Peripheral PORTIDs .................................................................................................... 1074
13.9 I/O Pins ................................................................................................................... 1075
13.9.1 Input/Output Modes ........................................................................................... 1075
13.10 IOC Registers ........................................................................................................... 1076
13.10.1 cc26_aon_ioc_REGMAP Registers ....................................................................... 1077
13.10.2 cc26_mcu_gpio_map1 Registers.......................................................................... 1083
13.10.3 cc26_mcu_ioc_map1 Registers............................................................................ 1106
14 Micro Direct Memory Access (µDMA) ................................................................................ 1268
14.1 μDMA Introduction ...................................................................................................... 1269
14.2 Block Diagram ........................................................................................................... 1270
14.3 Functional Description .................................................................................................. 1270
14.3.1 Channel Assignments ........................................................................................ 1271
14.3.2 Priority .......................................................................................................... 1272
14.3.3 Arbitration Size ................................................................................................ 1272
14.3.4 Request Types ................................................................................................ 1272
14.3.5 Channel Configuration........................................................................................ 1273
14.3.6 Transfer Modes................................................................................................ 1275
14.3.7 Transfer Size and Increments ............................................................................... 1282
14.3.8 Peripheral Interface ........................................................................................... 1282
14.3.9 Software Request ............................................................................................. 1282
14.3.10 Interrupts and Errors ........................................................................................ 1283
14.4 Initialization and Configuration......................................................................................... 1284
14.4.1 Module Initialization ........................................................................................... 1284
14.4.2 Configuring a Memory-to-Memory Transfer ............................................................... 1284
14.5 µDMA Registers ......................................................................................................... 1285
14.5.1 cc26_dma_pl230_r0p0_map1 Registers................................................................... 1286
15 Timers ........................................................................................................................... 1307
15.1 General-Purpose Timers ............................................................................................... 1308
15.2 Block Diagram ........................................................................................................... 1309
15.3.1 GPTM Reset Conditions ..................................................................................... 1310

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15.3.2 Timer Modes................................................................................................... 1310
15.3.3 Synchronizing GPT Blocks................................................................................... 1318
15.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values ...................................... 1319
15.4.1 One-Shot and Periodic Timer Modes....................................................................... 1320
15.4.2 Input Edge-Count Mode ...................................................................................... 1320
15.4.3 Input Edge-Timing Mode ..................................................................................... 1321
15.4.4 PWM Mode..................................................................................................... 1321
15.4.5 Producing DMA Trigger Events ............................................................................. 1322
15.5 GPTM Registers......................................................................................................... 1322
15.5.1 cc26_gpt_map1 Registers ................................................................................... 1323
16 Real-Time Clock (RTC)..................................................................................................... 1360
16.1 Introduction............................................................................................................... 1361
16.2 Functional Specifications............................................................................................... 1361
16.2.1 Functional Overview .......................................................................................... 1361
16.2.2 Free-Running Counter........................................................................................ 1361
16.2.3 Channels ....................................................................................................... 1362
16.2.4 Events .......................................................................................................... 1363
16.3 RTC Register Information .............................................................................................. 1363
16.3.1 Register Access ............................................................................................... 1363
16.3.2 Entering Sleep and Wakeup From Sleep ................................................................. 1363
16.3.3 AON_RTC:SYNC Register................................................................................... 1364
16.4 RTC Registers ........................................................................................................... 1364
16.4.1 cc26_aon_rtc_AON_RTC_RMAP Registers............................................................... 1365
17 Watchdog Timer (WDT).................................................................................................... 1381
17.1 Introduction............................................................................................................... 1382
17.4 WDT Registers .......................................................................................................... 1383
17.4.1 wdtimerv2_0_nosync_wrapper_map1 Registers.......................................................... 1384
18 True Random Number Generator (TRNG)........................................................................... 1394
18.1 Introduction............................................................................................................... 1395
18.2 Block Diagram ........................................................................................................... 1395
18.3 TRNG Software Reset.................................................................................................. 1396
18.4 Interrupt Requests....................................................................................................... 1396
18.5 TRNG Operation Description .......................................................................................... 1397
18.5.1 TRNG Shutdown .............................................................................................. 1397
18.5.2 TRNG Alarms.................................................................................................. 1398
18.5.3 TRNG Entropy ................................................................................................. 1398
18.6 TRNG Low-Level Programing Guide ................................................................................. 1399
18.6.1 Initialization..................................................................................................... 1399
18.7 TRNG Registers ......................................................................................................... 1401
18.7.1 cc26_TRNG_map1 Registers ............................................................................... 1402
19 AUX Domain Sensor Controller and Peripherals ................................................................. 1428
19.1 Introduction............................................................................................................... 1429
19.1.1 AUX Block Diagram........................................................................................... 1430
19.2 Power and Clock Management........................................................................................ 1431
19.2.1 Operational Modes............................................................................................ 1431
19.2.2 Use Scenarios ................................................................................................. 1433
19.2.3 SCE Clock Emulation......................................................................................... 1434
19.2.4 AUX RAM Retention .......................................................................................... 1434
19.3 Sensor Controller........................................................................................................ 1434

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19.3.1 Sensor Controller Studio ..................................................................................... 1434
19.3.2 Sensor Controller Engine (SCE) ............................................................................ 1439
19.4 Digital Peripheral Modules ............................................................................................. 1451
19.4.1 Overview ....................................................................................................... 1451
19.4.2 AIODIO ......................................................................................................... 1452
19.4.3 SMPH........................................................................................................... 1454
19.4.4 SPIM ............................................................................................................ 1454
19.4.5 Time-to-Digital Converter (TDC) ............................................................................ 1458
19.4.6 Timer01......................................................................................................... 1468
19.4.7 Timer2 .......................................................................................................... 1470
19.5 Analog Peripheral Modules ............................................................................................ 1477
19.5.1 Overview ....................................................................................................... 1477
19.5.2 Analog-to-Digital Converter (ADC).......................................................................... 1479
19.5.3 COMPA......................................................................................................... 1482
19.5.4 COMPB......................................................................................................... 1484
19.5.5 Reference DAC................................................................................................ 1487
19.5.6 ISRC ............................................................................................................ 1491
19.6 Event Routing and Usage.............................................................................................. 1493
19.6.1 AUX Event Bus ................................................................................................ 1493
19.6.2 Event Observation on External Pin ......................................................................... 1496
19.6.3 Events From MCU Domain .................................................................................. 1496
19.6.4 Events to MCU Domain ...................................................................................... 1496
19.6.5 Events From AON Domain................................................................................... 1497
19.6.6 Events to AON Domain....................................................................................... 1498
19.6.7 µDMA Interface................................................................................................ 1498
19.7 Sensor Controller Alias Register Space.............................................................................. 1499
19.8 AUX Domain Sensor Controller and Peripherals Registers ....................................................... 1504
19.8.1 ADI_4_AUX_mmap1 Registers ............................................................................. 1505
19.8.2 cc26_aux_aiodio_MMAP_AUX_AIODIO Registers....................................................... 1518
19.8.3 cc26_aux_evctl_MMAP_AUX_EVCTL Registers ......................................................... 1541
19.8.4 cc26_aux_smph_MMAP_AUX_SMPH Registers......................................................... 1583
19.8.5 cc26_aux_tdc_MMAP_AUX_TDC Registers .............................................................. 1593
19.8.6 cc26_aux_timer01_MMAP_AUX_TIMER01 Registers................................................... 1610
19.8.7 cc26_aux_timer2_MMAP_AUX_TIMER2 Registers...................................................... 1623
19.8.8 cc26_aux_anaif_MMAP_AUX_ANAIF Registers.......................................................... 1665
19.8.9 cc26_aux_sysif_MMAP_AUX_SYSIF Registers .......................................................... 1682
20 Battery Monitor and Temperature Sensor (BATMON) .......................................................... 1734
20.1 Introduction............................................................................................................... 1735
20.3 BATMON Registers ..................................................................................................... 1735
20.3.1 cc26_aon_batmon_REGMAP Registers ................................................................... 1736
21 Universal Asynchronous Receiver/Transmitter (UART)........................................................ 1757
21.1 Introduction............................................................................................................... 1758
21.2 Block Diagram ........................................................................................................... 1759
21.3 Signal Description ....................................................................................................... 1759
21.4 Functional Description ................................................................................................. 1759
21.4.1 Transmit and Receive Logic ................................................................................. 1760
21.4.2 Baud-rate Generation......................................................................................... 1760
21.4.3 Data Transmission ............................................................................................ 1760
21.4.4 Modem Handshake Support ................................................................................. 1761
21.4.5 FIFO Operation................................................................................................ 1762
21.4.6 Interrupts ....................................................................................................... 1762
21.4.7 Loopback Operation .......................................................................................... 1763

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21.5 Interface to DMA ........................................................................................................ 1764
21.7 UART Registers ......................................................................................................... 1765
21.7.1 cc26_uart_pl011_r1p5_map1 Registers ................................................................... 1766
22 Synchronous Serial Interface (SSI).................................................................................... 1789
22.1 Introduction............................................................................................................... 1790
22.2 Block Diagram ........................................................................................................... 1791
22.4.1 Bit Rate Generation........................................................................................... 1792
22.4.2 FIFO Operation................................................................................................ 1793
22.4.3 Interrupts ....................................................................................................... 1793
22.4.4 Frame Formats ................................................................................................ 1794
22.5 DMA Operation .......................................................................................................... 1801
22.7 SSI Registers ............................................................................................................ 1802
22.7.1 cc26_ssp_pl022_r1p4_map1 Registers.................................................................... 1803
23 Inter-Integrated Circuit (I2
C).............................................................................................. 1815
23.1 Introduction............................................................................................................... 1816
23.2 Block Diagram ........................................................................................................... 1816
23.3.1 I2
C Bus Functional Overview ................................................................................ 1817
23.3.2 Available Speed Modes ...................................................................................... 1819
23.3.3 Interrupts ....................................................................................................... 1820
23.3.4 Loopback Operation .......................................................................................... 1820
23.3.5 Command Sequence Flow Charts .......................................................................... 1821
23.5 I2
C Registers ............................................................................................................. 1828
23.5.1 cc26_i2c_map1 Registers.................................................................................... 1829
24 Inter-IC Sound (I2
S).......................................................................................................... 1850
24.1 Introduction .............................................................................................................. 1851
24.2 Block Diagram ........................................................................................................... 1852
24.4.1 Dependencies ................................................................................................. 1853
24.4.2 Pin Configuration .............................................................................................. 1854
24.4.3 Serial Format Configuration.................................................................................. 1854
24.4.4 I2
S ............................................................................................................... 1854
24.4.5 Left-Justified (LJF) ............................................................................................ 1855
24.4.6 Right-Justified (RJF) .......................................................................................... 1856
24.4.7 DSP ............................................................................................................. 1857
24.4.8 Clock Configuration ........................................................................................... 1858
24.5 Memory Interface........................................................................................................ 1859
24.5.1 Sample Word Length ......................................................................................... 1859
24.5.2 Channel Mapping ............................................................................................. 1859
24.5.3 Sample Storage in Memory.................................................................................. 1860
24.5.4 DMA Operation ................................................................................................ 1861
24.6 Samplestamp Generator ............................................................................................... 1863
24.6.1 Samplestamp Counters ...................................................................................... 1863
24.6.2 Start-Up Triggers .............................................................................................. 1864
24.6.3 Samplestamp Capture........................................................................................ 1864
24.6.4 Achieving Constant Audio Latency ......................................................................... 1864
24.7 Error Detection........................................................................................................... 1865

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24.8 Usage ..................................................................................................................... 1865
24.8.1 Start-Up Sequence............................................................................................ 1865
24.8.2 Shutdown Sequence.......................................................................................... 1865
24.9 I2
S Registers ............................................................................................................. 1865
24.9.1 cc26_i2s_map1 Registers.................................................................................... 1866
25 Radio............................................................................................................................. 1898
25.1 RF Core................................................................................................................... 1899
25.1.1 High-Level Description and Overview ...................................................................... 1899
25.2 Radio Doorbell........................................................................................................... 1901
25.2.1 Special Boot Process ......................................................................................... 1901
25.2.2 Command and Status Register and Events ............................................................... 1902
25.2.3 RF Core Interrupts ............................................................................................ 1902
25.2.4 Radio Timer .................................................................................................... 1903
25.3 RF Core HAL ............................................................................................................ 1905
25.3.1 Hardware Support............................................................................................. 1905
25.3.2 Firmware Support ............................................................................................. 1905
25.3.3 Command Definitions......................................................................................... 1917
25.3.4 Immediate Commands for Data Queue Manipulation .................................................... 1939
25.4 Data Queue Usage...................................................................................................... 1942
25.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations..................... 1942
25.4.2 Radio CPU Usage Model .................................................................................... 1945
25.5 IEEE 802.15.4 ........................................................................................................... 1946
25.5.1 IEEE 802.15.4 Commands................................................................................... 1946
25.5.2 Interrupts ....................................................................................................... 1954
25.5.3 Data Handling.................................................................................................. 1954
25.5.4 Radio Operation Commands ................................................................................ 1955
25.5.5 Immediate Commands ....................................................................................... 1968
25.6 Bluetooth®
low energy .................................................................................................. 1969
25.6.1 Bluetooth®
low energy Commands.......................................................................... 1969
25.6.2 Interrupts ....................................................................................................... 1989
25.7 Data Handling............................................................................................................ 1990
25.7.1 Receive Buffers................................................................................................ 1990
25.7.2 Transmit Buffers............................................................................................... 1991
25.8 Radio Operation Command Descriptions ............................................................................ 1991
25.8.1 Bluetooth®
5 Radio Setup Command....................................................................... 1991
25.8.2 Radio Operation Commands for Bluetooth®
low energy Packet Transfer ............................. 1991
25.8.3 Coding Selection for Coded PHY ........................................................................... 1993
25.8.4 Parameter Override ........................................................................................... 1994
25.8.5 Link Layer Connection ....................................................................................... 1995
25.8.6 Slave Command............................................................................................... 1999
25.8.7 Master Command ............................................................................................. 2000
25.8.8 Legacy Advertiser ............................................................................................. 2001
25.8.9 Bluetooth®
5 Advertiser Commands ........................................................................ 2006
25.8.10 Scanner Commands......................................................................................... 2010
25.8.11 Initiator Command ........................................................................................... 2018
25.8.12 Generic Receiver Command ............................................................................... 2025
25.8.13 PHY Test Transmit Command ............................................................................. 2026
25.8.14 Whitelist Processing......................................................................................... 2028
25.8.15 Backoff Procedure ........................................................................................... 2028
25.8.16 AUX Pointer Processing .................................................................................... 2029
25.8.17 Dynamic Change of Device Address...................................................................... 2030
25.9 Immediate Commands.................................................................................................. 2030
25.9.1 Update Advertising Payload Command .................................................................... 2030

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11
Contents
25.10 Proprietary Radio ....................................................................................................... 2031
25.10.1 Packet Formats .............................................................................................. 2031
25.10.2 Commands ................................................................................................... 2031
25.10.3 Interrupts...................................................................................................... 2038
25.10.4 Data Handling ................................................................................................ 2038
25.10.5 Radio Operation Command Descriptions................................................................. 2039
25.10.6 Immediate Commands ...................................................................................... 2051
25.11 Radio Registers ......................................................................................................... 2051
25.11.1 cc26_rfcore_ig_rat_map_rat Registers ................................................................... 2052
25.11.2 cc26_rfcore_ig_rdbell_map_rdbell Registers ............................................................ 2062
25.11.3 cc26_rfcore_ig_rfcpwm_map_rfcpwm Registers ........................................................ 2080
Revision History ...................................................................................................................... 2082

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List of Figures
List of Figures
1-1. CC13x2 and CC26x2 Block Diagram.................................................................................... 75
1-2. CC13x2 and CC26x2 Supply System ................................................................................... 86
2-1. CPU Block Diagram........................................................................................................ 90
2-2. TPIU Block Diagram ....................................................................................................... 91
2-3. Arm®
Cortex®
-M4F Register Set.......................................................................................... 93
2-4. FPU Register Bank ....................................................................................................... 116
2-5. CTRL Register ............................................................................................................ 125
2-6. CYCCNT Register ........................................................................................................ 127
2-7. CPICNT Register ......................................................................................................... 128
2-8. EXCCNT Register ........................................................................................................ 129
2-9. SLEEPCNT Register ..................................................................................................... 130
2-10. LSUCNT Register......................................................................................................... 131
2-11. FOLDCNT Register....................................................................................................... 132
2-12. PCSR Register............................................................................................................ 133
2-13. COMP0 Register.......................................................................................................... 134
2-14. MASK0 Register .......................................................................................................... 135
2-15. FUNCTION0 Register .................................................................................................... 136
2-16. COMP1 Register.......................................................................................................... 138
2-17. MASK1 Register .......................................................................................................... 139
2-19. COMP2 Register.......................................................................................................... 143
2-20. MASK2 Register .......................................................................................................... 144
2-22. COMP3 Register.......................................................................................................... 147
2-23. MASK3 Register .......................................................................................................... 148
2-25. CTRL Register ............................................................................................................ 152
2-26. REMAP Register.......................................................................................................... 153
2-27. COMP0 Register.......................................................................................................... 154
2-28. COMP1 Register.......................................................................................................... 155
2-29. COMP2 Register.......................................................................................................... 156
2-30. COMP3 Register.......................................................................................................... 157
2-31. COMP4 Register.......................................................................................................... 158
2-32. COMP5 Register.......................................................................................................... 159
2-33. COMP6 Register.......................................................................................................... 160
2-34. COMP7 Register.......................................................................................................... 161
2-35. STIM0 Register ........................................................................................................... 164
2-36. STIM1 Register ........................................................................................................... 165
2-37. STIM2 Register ........................................................................................................... 166
2-38. STIM3 Register ........................................................................................................... 167
2-39. STIM4 Register ........................................................................................................... 168
2-40. STIM5 Register ........................................................................................................... 169
2-41. STIM6 Register ........................................................................................................... 170
2-42. STIM7 Register ........................................................................................................... 171
2-43. STIM8 Register ........................................................................................................... 172
2-44. STIM9 Register ........................................................................................................... 173
2-45. STIM10 Register .......................................................................................................... 174

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13
List of Figures
2-46. STIM11 Register .......................................................................................................... 175
2-47. STIM12 Register .......................................................................................................... 176
2-48. STIM13 Register .......................................................................................................... 177
2-49. STIM14 Register .......................................................................................................... 178
2-50. STIM15 Register .......................................................................................................... 179
2-51. STIM16 Register .......................................................................................................... 180
2-52. STIM17 Register .......................................................................................................... 181
2-53. STIM18 Register .......................................................................................................... 182
2-54. STIM19 Register .......................................................................................................... 183
2-55. STIM20 Register .......................................................................................................... 184
2-56. STIM21 Register .......................................................................................................... 185
2-57. STIM22 Register .......................................................................................................... 186
2-58. STIM23 Register .......................................................................................................... 187
2-59. STIM24 Register .......................................................................................................... 188
2-60. STIM25 Register .......................................................................................................... 189
2-61. STIM26 Register .......................................................................................................... 190
2-62. STIM27 Register .......................................................................................................... 191
2-63. STIM28 Register .......................................................................................................... 192
2-64. STIM29 Register .......................................................................................................... 193
2-65. STIM30 Register .......................................................................................................... 194
2-66. STIM31 Register .......................................................................................................... 195
2-67. TER Register .............................................................................................................. 196
2-68. TPR Register .............................................................................................................. 198
2-69. TCR Register.............................................................................................................. 199
2-70. LAR Register .............................................................................................................. 201
2-71. LSR Register .............................................................................................................. 202
2-72. ICTR Register ............................................................................................................. 206
2-73. ACTLR Register........................................................................................................... 207
2-74. STCSR Register .......................................................................................................... 208
2-75. STRVR Register .......................................................................................................... 209
2-76. STCVR Register .......................................................................................................... 210
2-77. STCR Register ............................................................................................................ 211
2-78. NVIC_ISER0 Register.................................................................................................... 212
2-79. NVIC_ISER1 Register.................................................................................................... 215
2-80. NVIC_ICER0 Register.................................................................................................... 216
2-81. NVIC_ICER1 Register.................................................................................................... 219
2-82. NVIC_ISPR0 Register.................................................................................................... 220
2-83. NVIC_ISPR1 Register.................................................................................................... 223
2-84. NVIC_ICPR0 Register.................................................................................................... 224
2-85. NVIC_ICPR1 Register.................................................................................................... 227
2-86. NVIC_IABR0 Register.................................................................................................... 228
2-87. NVIC_IABR1 Register.................................................................................................... 231
2-88. NVIC_IPR0 Register ..................................................................................................... 232

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List of Figures
2-98. CPUID Register ........................................................................................................... 242
2-99. ICSR Register ............................................................................................................. 243
2-100. VTOR Register............................................................................................................ 245
2-101. AIRCR Register ........................................................................................................... 246
2-102. SCR Register.............................................................................................................. 247
2-103. CCR Register.............................................................................................................. 248
2-104. SHPR1 Register .......................................................................................................... 250
2-105. SHPR2 Register .......................................................................................................... 251
2-106. SHPR3 Register .......................................................................................................... 252
2-107. SHCSR Register .......................................................................................................... 253
2-108. CFSR Register ............................................................................................................ 255
2-109. HFSR Register ............................................................................................................ 258
2-110. DFSR Register ............................................................................................................ 259
2-111. MMFAR Register.......................................................................................................... 260
2-112. BFAR Register ............................................................................................................ 261
2-113. AFSR Register ............................................................................................................ 262
2-114. ID_PFR0 Register ........................................................................................................ 263
2-115. ID_PFR1 Register ........................................................................................................ 264
2-116. ID_DFR0 Register ........................................................................................................ 265
2-117. ID_AFR0 Register ........................................................................................................ 266
2-118. ID_MMFR0 Register...................................................................................................... 267
2-119. ID_MMFR1 Register...................................................................................................... 268
2-120. ID_MMFR2 Register...................................................................................................... 269
2-121. ID_MMFR3 Register...................................................................................................... 270
2-122. ID_ISAR0 Register ....................................................................................................... 271
2-123. ID_ISAR1 Register ....................................................................................................... 272
2-124. ID_ISAR2 Register ....................................................................................................... 273
2-125. ID_ISAR3 Register ....................................................................................................... 274
2-126. ID_ISAR4 Register ....................................................................................................... 275
2-127. CPACR Register .......................................................................................................... 276
2-128. MPU_TYPE Register..................................................................................................... 277
2-129. MPU_CTRL Register..................................................................................................... 278
2-130. MPU_RNR Register ...................................................................................................... 279
2-131. MPU_RBAR Register .................................................................................................... 280
2-132. MPU_RASR Register .................................................................................................... 281
2-133. MPU_RBAR_A1 Register................................................................................................ 283
2-134. MPU_RASR_A1 Register................................................................................................ 284
2-139. DHCSR Register.......................................................................................................... 289
2-140. DCRSR Register.......................................................................................................... 292
2-141. DCRDR Register.......................................................................................................... 294
2-142. DEMCR Register.......................................................................................................... 295
2-143. STIR Register ............................................................................................................. 297

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15
List of Figures
2-144. FPCCR Register .......................................................................................................... 298
2-145. FPCAR Register .......................................................................................................... 300
2-146. FPDSCR Register ........................................................................................................ 301
2-147. MVFR0 Register .......................................................................................................... 302
2-148. MVFR1 Register .......................................................................................................... 303
2-149. SSPSR Register .......................................................................................................... 306
2-150. CSPSR Register .......................................................................................................... 307
2-151. ACPR Register............................................................................................................ 308
2-152. SPPR Register ............................................................................................................ 309
2-153. FFSR Register ............................................................................................................ 310
2-154. FFCR Register ............................................................................................................ 311
2-155. FSCR Register ............................................................................................................ 312
2-156. CLAIMMASK Register.................................................................................................... 313
2-157. CLAIMSET Register ...................................................................................................... 314
2-158. CLAIMTAG Register...................................................................................................... 315
2-159. CLAIMCLR Register...................................................................................................... 316
2-160. DEVID Register ........................................................................................................... 317
5-1. Vector Table............................................................................................................... 330
5-2. Exception Stack Frame .................................................................................................. 332
5-3. Event Fabric Concept .................................................................................................... 336
5-4. Event Fabric Overview (Simplified)..................................................................................... 337
5-5. WUC Subscriber in AON Event Fabric................................................................................. 338
5-6. MCUWUSEL Register.................................................................................................... 346
5-7. MCUWUSEL1 Register .................................................................................................. 351
5-8. EVTOMCUSEL Register................................................................................................. 356
5-9. RTCSEL Register......................................................................................................... 360
5-10. CPUIRQSEL0 Register .................................................................................................. 364
5-20. CPUIRQSEL10 Register................................................................................................. 374

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List of Figures
5-48. RFCSEL0 Register ....................................................................................................... 403
5-49. RFCSEL1 Register ....................................................................................................... 404
5-50. RFCSEL2 Register ....................................................................................................... 405
5-51. RFCSEL3 Register ....................................................................................................... 406
5-52. RFCSEL4 Register ....................................................................................................... 407
5-53. RFCSEL5 Register ....................................................................................................... 408
5-54. RFCSEL6 Register ....................................................................................................... 409
5-55. RFCSEL7 Register ....................................................................................................... 410
5-56. RFCSEL8 Register ....................................................................................................... 411
5-57. RFCSEL9 Register ....................................................................................................... 412
5-58. GPT0ACAPTSEL Register .............................................................................................. 415
5-59. GPT0BCAPTSEL Register .............................................................................................. 418
5-64. UDMACH1SSEL Register ............................................................................................... 433
5-65. UDMACH1BSEL Register ............................................................................................... 434

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17
List of Figures
5-82. UDMACH10SSEL Register.............................................................................................. 451
5-83. UDMACH10BSEL Register.............................................................................................. 452
5-105. AUXSEL0 Register ....................................................................................................... 482
5-106. CM3NMISEL0 Register .................................................................................................. 483
5-107. I2SSTMPSEL0 Register ................................................................................................. 484
5-108. FRZSEL0 Register........................................................................................................ 485
5-109. SWEV Register ........................................................................................................... 486
6-1. Top-Level Debug System ............................................................................................... 488
6-2. JTAG State Machine ..................................................................................................... 489
6-3. cJTAG Conceptual Diagram............................................................................................. 490
6-4. Data Shift Register........................................................................................................ 498
6-5. Instruction Register ....................................................................................................... 498
6-6. Bypass Register........................................................................................................... 498
6-7. Device Identification Register ........................................................................................... 498
6-8. User Code Register ...................................................................................................... 499
6-9. ICEPick Identification Register.......................................................................................... 499
6-10. Connect Register ......................................................................................................... 500
6-11. ROUTER DR Scan Chain ............................................................................................... 500
6-12. Profiler Register........................................................................................................... 507
6-13. Boundary Scan Cell ...................................................................................................... 509
7-1. Hierarchy of Power Saving Features................................................................................... 513
7-2. CC13x2 and CC26x2 Supply System.................................................................................. 515
7-3. Digital Power Partitioning in CC13x2 and CC26x2................................................................... 516
7-4. Clock Sources............................................................................................................. 517
7-5. System Clock Muxing .................................................................................................... 519
7-6. Clocks in MCU_VD ....................................................................................................... 521
7-7. CTL0 Register............................................................................................................. 528
7-8. CTL1 Register............................................................................................................. 530

CC13x2, CC26x2 SimpleLink™ Wireless MCU manual.pdf

CC13x2, CC26x2 SimpleLink™ Wireless MCU manual.pdf

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