Tech Overview

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A layman\'s overview of silicon technology, semiconductor manufacturing, and computer architecture.

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  • Tech Overview

    1. 1. Silicon Technology Overview for Non-Engineers Bill Gascoyne
    2. 2. Purpose <ul><li>Everyone should know where their paycheck comes from </li></ul><ul><ul><li>“All professions are conspiracies against the laity.” George Bernard Shaw (1856-1950) </li></ul></ul><ul><ul><li>Good for CFO to explain financials </li></ul></ul><ul><ul><li>Good for Engineering to explain tech </li></ul></ul><ul><li>Practice for trainer </li></ul><ul><ul><li>Know your assumptions </li></ul></ul><ul><li>It’s fun for me!! </li></ul><ul><ul><li>Thanks for indulging me </li></ul></ul>
    3. 3. Agenda <ul><li>Silicon, Electricity, & Transistors </li></ul><ul><li>Chips </li></ul><ul><li>EDA (Electronic Design Automation) Software </li></ul>
    4. 4. Silicon <ul><li>Silicon (Si) is a Mineral found in sand (SiO 2 ) </li></ul><ul><li>2nd most abundant element in Earth’s crust </li></ul><ul><li>“Silicone” is rubber </li></ul><ul><li>Manufacturer purchases silicon wafers </li></ul><ul><li>Wafers sliced from ingots </li></ul><ul><li>Ingots grown by wafer manufacturer </li></ul>Molten Silicon Heating Coils Silicon crystal structure
    5. 5. Gates Unfortunately, the word “gate” is used to mean several different things. Logic “gate” 4 transistors (1 million gates) “ Gate” terminal on a transistor (45n gate) D Q G “ Gate” on a latch (Engineers only)
    6. 6. “Analog” vs. “Digital” Analog is continuous & interpolated, “real world”; Subject to interpretation, interference. Digital is numeric & discreet, information only; Hard & fast, on or off, works or doesn’t work. Phonograph is analog; the groove is shaped like the sound. CD is digital; numbers represent the sound.
    7. 7. More Analog vs. Digital Analog (Bipolar) transistor acts like a valve; allows so many electrons to flow at a time. Digital (CMOS) transistor is all the way off or on, more like a switch. “ ON” or “OFF” is less information than “How many electrons”, so digital needs more transistors for the same amount of data, but each transistor can be less precise and smaller. Analog (“Linear Region”) Digital (If smoothly turning the faucet one way made the flow increase and decrease in fits and starts, control would be non-linear.)
    8. 8. Current and Voltage <ul><li>If Electricity were Water, then: </li></ul><ul><ul><li>Voltage would be Pressure </li></ul></ul><ul><ul><li>Current would be Volume </li></ul></ul><ul><ul><li>Volume and Pressure are Independent! </li></ul></ul>Low voltage, High current High voltage, Low current Low Low High High Current Eye dropper Low Calculator Squirt gun High TV Tube Bucket Low Stereo Speakers Firehose High Oven Water Voltage Item
    9. 9. Electricity Current flows this way Electrons flow this way Electricity is labeled “backwards,” sort of…. Electrons are like the tiles, current is like the empty space. Which actually moves?
    10. 10. Basic Units <ul><li>Length (meter) (m) </li></ul><ul><li>Time (second) (s) </li></ul><ul><li>Mass (Kilogram) (Kg) </li></ul><ul><li>Charge (Coulomb) (C) </li></ul><ul><ul><li>Force (Newton) (N) accelerate 1Kg(1m/s)/s </li></ul></ul><ul><ul><li>Pressure (Pascal) (Pa) 1N / 1m 2 </li></ul></ul><ul><ul><li>Energy/Heat (Joule) (J) 1Pa/1m 3 (Nm) </li></ul></ul><ul><ul><li>Power (Watt) (W) J/s (or VA) </li></ul></ul><ul><ul><li>Current (Ampere) (A) C/s </li></ul></ul><ul><ul><li>Electrical Force (Volts) (V) W/A or J/C </li></ul></ul><ul><ul><li>Elec. Resistance (Ohms) ( Ω ) V/A (Ohm’s law: V=A Ω ) </li></ul></ul><ul><ul><li>Elec. Capacitance (Farads) (F) As/V so (F)(1/s) = 1/ Ω </li></ul></ul><ul><ul><li>Elec. Inductance (Henrys) (H) Vs/A so (H)(1/s) = Ω </li></ul></ul>
    11. 11. Engineering Notation <ul><li>Each Latin number prefix = 1000X smaller </li></ul><ul><ul><li>milli = 10 -3 , micro = 10 -6 , nano = 10 -9 , pico = 10 -12 </li></ul></ul><ul><ul><li>Small letters (m, µ , n, p) </li></ul></ul><ul><li>Each Greek number prefix = 1000X larger </li></ul><ul><ul><li>Kilo = 10 3 , Mega = 10 6 , Giga = 10 9 , Tera = 10 12 </li></ul></ul><ul><ul><li>Capital letters (K, M, G, T) </li></ul></ul><ul><li>Meter is to millimeter as millimeter is to micrometer </li></ul>
    12. 12. Dopants Electron shell’s “magic stability #” is 8. Tetrahedron shape “feels like” “sharing” 1 ea. w/ 4 neighbors, “feels” stable. (Everyone’s content, no work gets done) N N N + N + N + N + + N N N + N + N + N + + Silicon N N N + N + N + N + + Boron (Positive dopant) N N N + N + N + N + + N N N + N + N + N + + Phosphorus (Negative dopant)
    13. 13. Diode <ul><li>Adjacent N and P areas form a “depletion region” where they meet </li></ul><ul><ul><li>Opposite charges “deplete” carriers from either side, potential created </li></ul></ul><ul><li>“Majority carriers” are exchanged when current flows </li></ul><ul><li>One N and one P form a diode (current flows only one way) </li></ul>N P + - + - + - + - + - + - Depletion Region
    14. 14. Bipolar Transistor Operation <ul><li>Formed by NPN or PNP diffusions with the middle (base) region very thin </li></ul><ul><li>Base-Emitter is forward biased, remains at .7V </li></ul><ul><li>Thin base region allows little current through the base lead </li></ul><ul><li>Base-collector is forward-biased, but thin base allows most carriers from emitter through base to collector </li></ul><ul><li>Small base current multiplies collector-emitter current </li></ul>Emitter Collector Base Emitter Collector Base N P N P N P
    15. 15. Bipolar Cross-section <ul><li>When fabricated, collector and emitter are not symmetrical </li></ul><ul><li>Operation enhanced by small emitter, lightly-doped N collector region </li></ul>P N- N+ N+ Collector Emitter Base
    16. 16. CMOS Transistor Operation <ul><li>We can also reverse the situation to create an N channel transistor </li></ul><ul><li>Negative charge on gate concentrates “holes” (+ charges) in channel (hence, P channel) </li></ul>N+ N+ P- P+ P+ N- 90n
    17. 17. P Channel vs. N Channel n+ n+ p+ p+ P- well N- well N channel symbol P channel symbol n+ = heavily doped negative (P, As) N- = lightly doped negative p+ = heavily doped positive (B) P- = lightly doped positive Wafer Source Gate Drain Oxide
    18. 18. Computer Logic Input Up = 1 0 Input Down = 0 1 Logic Symbol Schematic <ul><li>The simplest piece of computer (or “Boolean”) logic is the inverter </li></ul><ul><ul><li>Input “1” makes Output “0” and vice-versa. </li></ul></ul>A (Input) A (Input) Z (Output) Z (Output) off on on off off on on off off on on off off on on off
    19. 19. More Computer Logic <ul><li>Adding two more transistors to the inverter results in a NAND (Not AND) gate. </li></ul>0 1 1 1 1 0 1 0 1 1 0 0 Z B A A Z B A B Z “ bubble” always indicates “Not” A & B = !Z “ AND” shape 1 off off on on 0 1
    20. 20. AND vs. OR A and B and C A or B or C A Z C B C A B Z A Z B C C A B Z A B C A B C
    21. 21. Chips
    22. 22. An Illustration of Chip Scale Imagine that a wire on the chip is the size of a road. And roads are shoulder- to-shoulder for 7 levels. Then a transistor is the size of a car, and the chip covers most of Western Europe…
    23. 23. Moore’s Law <ul><li>Gordon Moore, co-founder of Intel, pointed out in a 1965 paper that the number of transistors on a chip had doubled roughly every two years, and he predicted that this would continue </li></ul><ul><ul><li>He was right; this had held true for almost fifty years </li></ul></ul><ul><li>The result has been an economic boon </li></ul><ul><li>An unfortunate consequence of Moore’s Law is that the cost of creating each new generation (a.k.a. “node”) of technology has increased almost as fast </li></ul><ul><li>We are rapidly approaching the point where Moore’s Law must end </li></ul><ul><ul><li>You can’t make a transistor smaller than an atom </li></ul></ul>
    24. 24. Shrinking Transistors <ul><li>If the transistors of the Intel 4004 (10 µ ) were the size of a Humvee, a 45n transistor would be the size of a sesame seed </li></ul>
    25. 25. More about scale <ul><li>A micrometer (formerly known as a micron) is one millionth of a meter. </li></ul><ul><li>A piece of human hair is about 100 micrometers thick. </li></ul><ul><li>The speed of light is about one foot per nanosecond (billionth of a second). </li></ul><ul><li>There are as many nanoseconds in a second as there have been seconds since 1977. </li></ul><ul><ul><li>31.7 years </li></ul></ul>
    26. 26. Die per Wafer *Source: SEMI Max. Die size Max. Die/Wafer* 12” (300mm ) 8” (200mm ) 6” (150mm ) 5” (125mm ) 4” (100mm ) 1cm 24 2cm 57 2cm 148 2cm 1.5cm
    27. 27. 3-D Chip Structure <ul><li>Several layers in the transistor </li></ul><ul><li>Two more layers for each wire level </li></ul><ul><ul><li>One for wires, one for vias between wire levels </li></ul></ul>Transistor Silicon substrate 1 st level wire 2 nd level wire 3 rd level wire 4 th level wire 5 th level wire
    28. 28. Photolithography: What’s in a Word? Writing in Stone with Light Photo litho graphy
    29. 29. Each Layer is Drawn on a Mask Ultraviolet Light Source 4:1 reduction lens The wafer is coated with a light-sensitive resin called photoresist . It is moved by a machine called a stepper . The glass mask (actually called a reticle ) is four times the size of the die.
    30. 30. Photolithography, Etch, Dope, Sputter Wafer (on edge) Mask Photo- resist Etch Dope Sputter
    31. 31. Optical Proximity Correction (OPC) <ul><li>In the late 80’s, it was thought that X-rays would be needed to create smaller features </li></ul><ul><ul><li>It is not possible to sharply focus an image smaller than the wavelength of the light used (Currently 193nm EUV) </li></ul></ul><ul><li>More powerful computers based on <1 µ process made it possible to simulate optical distortions </li></ul><ul><li>Working the problem backwards led to distorted masks that focus the desired image </li></ul>Mask Image
    32. 32. Chip Packages PQFP TQFP PGA BGA Flip Chip DIP
    33. 33. Where’s the chip in the package? Die Cavity Bond Fingers PGA w/ lid removed
    34. 34. Printed Circuit Boards Surface-Mount Through-Hole
    35. 35. Software EDA Tools
    36. 36. What does EDA do? <ul><li>The Electronic Design Automation industry exists primarily to answer one question: </li></ul><ul><ul><li>“What pattern must be drawn on each mask in order to manufacture a chip that behaves according to the customer’s specification?” </li></ul></ul><ul><ul><ul><li>Secondary questions: How to test chips after they’re made? How to fit chip into package? How to put wires on PC boards to connect the chips together? </li></ul></ul></ul>
    37. 37. Electronic Design Automation (EDA) <ul><li>There are three basic tasks to perform </li></ul><ul><li>Describe the idea (Build the Model) </li></ul><ul><ul><li>Logic Design (Synthesis) </li></ul></ul><ul><li>Evaluate the idea (Test the Model) </li></ul><ul><ul><li>Simulate and Analyze (Predicted Chip Behavior) </li></ul></ul><ul><li>Transfer Design Information to Manufacturing (Realize the Model) </li></ul><ul><ul><li>Physical Design and Testing </li></ul></ul>
    38. 38. Levels of Abstraction <ul><li>EDA Tools use approximations of data from more exact tools/measurements </li></ul><ul><ul><li>Like Babushka dolls </li></ul></ul><ul><li>As chips get more complex, job gets harder, another (bigger) doll is added </li></ul><ul><ul><li>Measurements/simulations of silicon diffusions (10 0 T’s) </li></ul></ul><ul><ul><li>SPICE transistor models (analog waveforms) (10 2 T’s) </li></ul></ul><ul><ul><li>Gate level simulations (0/1 w/ rise/fall delays) (10 5 T’s) </li></ul></ul><ul><ul><li>RTL (Register Transfer Level) (clock cycles) (10 8 T’s) </li></ul></ul><ul><ul><li>C-Code (abstract algorithms) </li></ul></ul><ul><li>At each step, results less precise </li></ul>Precision ≠ Accuracy
    39. 39. Logical Design Tools (Synthesis)
    40. 40. Hardware Description Languages <ul><li>Purpose: Make hardware design like writing software </li></ul><ul><li>Two main HDLs in the industry </li></ul><ul><ul><li>Verilog </li></ul></ul><ul><ul><ul><li>Developed privately, placed into public domain </li></ul></ul></ul><ul><ul><ul><li>Terse, “Loosely typed” </li></ul></ul></ul><ul><ul><ul><li>Easy to use, but allows users enough rope to hang themselves </li></ul></ul></ul><ul><ul><ul><li>Most common </li></ul></ul></ul><ul><ul><li>VHDL </li></ul></ul><ul><ul><ul><li>Developed by US DOD committee (and looks it) </li></ul></ul></ul><ul><ul><ul><li>Verbose, “Strongly typed” </li></ul></ul></ul><ul><ul><ul><li>Harder to use, works well or not at all (not much “rope”) </li></ul></ul></ul><ul><ul><ul><li>Popular for library development, also common in military and Europe </li></ul></ul></ul>
    41. 41. Simulation & Analysis Tools
    42. 42. Many Different Questions, Many Different Tasks <ul><li>What will it do? </li></ul><ul><ul><li>Simulation </li></ul></ul><ul><li>How fast will it go? </li></ul><ul><ul><li>Delay prediction </li></ul></ul><ul><ul><li>Static Timing Analysis (STA) </li></ul></ul><ul><ul><li>Statistical Static Timing Analysis (SSTA) </li></ul></ul><ul><li>How different is it from the previous version? </li></ul><ul><ul><li>Formal Verification </li></ul></ul><ul><li>How will we test it? </li></ul><ul><ul><li>Design For Test (DFT) </li></ul></ul><ul><ul><li>Automatic Test Pattern Generation (ATPG) </li></ul></ul><ul><li>How well will it yield? </li></ul><ul><ul><li>Design For Manufacturability (DFM) </li></ul></ul><ul><ul><li>Design Rule Checks (DRC) </li></ul></ul>
    43. 43. Physical Design Tools
    44. 44. Physical Design Basics: Place & Route <ul><li>Place </li></ul><ul><ul><li>How best to fit everything together on the chip </li></ul></ul><ul><ul><li>“Jigsaw puzzle” (but w/ abstract picture – many solutions) </li></ul></ul><ul><li>Route </li></ul><ul><ul><li>How best to connect everything once it’s placed </li></ul></ul><ul><ul><li>“Traveling Salesman Problem” </li></ul></ul>
    45. 45. Companies <ul><li>Companies that make chips: </li></ul><ul><ul><li>Intel, AMD, National, TI, Toshiba, Fujitsu </li></ul></ul><ul><li>“ Fabless” companies: </li></ul><ul><ul><li>LSI, Nvidia, MIPS, ARM, ++++ </li></ul></ul><ul><li>Fab-only companies (fabs for the fabless): </li></ul><ul><ul><li>TSMC, Chartered, UMC </li></ul></ul><ul><li>FPGA companies (programmable chips; fabless): </li></ul><ul><ul><li>Xylinx, Altera, Actel, Atmel </li></ul></ul><ul><li>EDA (Software) companies: </li></ul><ul><ul><li>Synopsys, Cadence, Mentor Graphics, Cadence, ++++ </li></ul></ul><ul><li>Equipment companies: </li></ul><ul><ul><li>Applied Materials, Ultratech </li></ul></ul><ul><li>Tester & measurement companies: </li></ul><ul><ul><li>Credence, KLA Tencor, Teradyne, Agilent, Nanometrics </li></ul></ul>
    46. 46. Summary <ul><li>Chips made from Silicon </li></ul><ul><ul><li>Moore’s Law: electronics keep getting better/cheaper </li></ul></ul><ul><li>Mfg. setup (“tooling”) is very expensive </li></ul><ul><ul><li>Can’t afford to be wrong </li></ul></ul><ul><li>EDA ensures chip will work before it’s built </li></ul>
    47. 47. Thank you!

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