SlideShare a Scribd company logo
1 of 2
Question 1
For the circuit in figure 2, determine the output if the input are:

a. [A] = 01012 and [B] = 11012
b. [A] = 01112 and [B] = 11112
Question 2

(4 Marks)

(4 Marks)
Question 3
Design an asynchronous counter that will count in a sequence of 6, 5, 4, 3, 2, 1 and
repeat. Only J-K flip-flops that have two active low control inputs PRE and CLR are
allowed to be used. Briefly explain the operation of the design.
(20
Marks)

More Related Content

What's hot

Digital logic design DLD Logic gates
Digital logic design DLD Logic gatesDigital logic design DLD Logic gates
Digital logic design DLD Logic gatesSalman Khan
 
Digital Logic Circuits
Digital Logic CircuitsDigital Logic Circuits
Digital Logic Circuitssathish sak
 
BOOLEAN ALGEBRA AND LOGIC GATE
BOOLEAN ALGEBRA AND LOGIC GATE BOOLEAN ALGEBRA AND LOGIC GATE
BOOLEAN ALGEBRA AND LOGIC GATE Tamim Tanvir
 
Digital systems logicgates-booleanalgebra
Digital systems logicgates-booleanalgebraDigital systems logicgates-booleanalgebra
Digital systems logicgates-booleanalgebraelfeds916
 
Seminar on Digital Multiplier(Booth Multiplier) Using VHDL
Seminar on Digital Multiplier(Booth Multiplier) Using VHDLSeminar on Digital Multiplier(Booth Multiplier) Using VHDL
Seminar on Digital Multiplier(Booth Multiplier) Using VHDLNaseer LoneRider
 
Computer organization and architecture lab manual
Computer organization and architecture lab manual Computer organization and architecture lab manual
Computer organization and architecture lab manual Shankar Gangaju
 
Power Optimization using Reversible Gates for Booth’s Multiplier
Power Optimization using Reversible Gates for Booth’s MultiplierPower Optimization using Reversible Gates for Booth’s Multiplier
Power Optimization using Reversible Gates for Booth’s MultiplierIJMTST Journal
 
Devry ecet 105 week 3 i lab introduction to digital logic gates new
Devry ecet 105 week 3 i lab introduction to digital logic gates newDevry ecet 105 week 3 i lab introduction to digital logic gates new
Devry ecet 105 week 3 i lab introduction to digital logic gates newBartholomee
 
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unit
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic UnitDesign and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unit
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unitrahulmonikasharma
 
GSP 215 RANK Achievement Education--gsp215rank.com
GSP 215 RANK Achievement Education--gsp215rank.comGSP 215 RANK Achievement Education--gsp215rank.com
GSP 215 RANK Achievement Education--gsp215rank.comclaric169
 
GSP 215 RANK Become Exceptional--gsp215rank.com
GSP 215 RANK Become Exceptional--gsp215rank.comGSP 215 RANK Become Exceptional--gsp215rank.com
GSP 215 RANK Become Exceptional--gsp215rank.comclaric119
 
Computer Organization And Architecture lab manual
Computer Organization And Architecture lab manualComputer Organization And Architecture lab manual
Computer Organization And Architecture lab manualNitesh Dubey
 
Digital Electronics Question Bank
Digital Electronics Question BankDigital Electronics Question Bank
Digital Electronics Question BankMathankumar S
 

What's hot (20)

Digital Logic circuit
Digital Logic circuitDigital Logic circuit
Digital Logic circuit
 
Digital logic
Digital logicDigital logic
Digital logic
 
Digital logic design DLD Logic gates
Digital logic design DLD Logic gatesDigital logic design DLD Logic gates
Digital logic design DLD Logic gates
 
Digital Logic Circuits
Digital Logic CircuitsDigital Logic Circuits
Digital Logic Circuits
 
Digital logic
Digital logicDigital logic
Digital logic
 
BOOLEAN ALGEBRA AND LOGIC GATE
BOOLEAN ALGEBRA AND LOGIC GATE BOOLEAN ALGEBRA AND LOGIC GATE
BOOLEAN ALGEBRA AND LOGIC GATE
 
Digital systems logicgates-booleanalgebra
Digital systems logicgates-booleanalgebraDigital systems logicgates-booleanalgebra
Digital systems logicgates-booleanalgebra
 
Seminar on Digital Multiplier(Booth Multiplier) Using VHDL
Seminar on Digital Multiplier(Booth Multiplier) Using VHDLSeminar on Digital Multiplier(Booth Multiplier) Using VHDL
Seminar on Digital Multiplier(Booth Multiplier) Using VHDL
 
Digital logic circuit
Digital logic circuitDigital logic circuit
Digital logic circuit
 
Computer organization and architecture lab manual
Computer organization and architecture lab manual Computer organization and architecture lab manual
Computer organization and architecture lab manual
 
Power Optimization using Reversible Gates for Booth’s Multiplier
Power Optimization using Reversible Gates for Booth’s MultiplierPower Optimization using Reversible Gates for Booth’s Multiplier
Power Optimization using Reversible Gates for Booth’s Multiplier
 
Devry ecet 105 week 3 i lab introduction to digital logic gates new
Devry ecet 105 week 3 i lab introduction to digital logic gates newDevry ecet 105 week 3 i lab introduction to digital logic gates new
Devry ecet 105 week 3 i lab introduction to digital logic gates new
 
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unit
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic UnitDesign and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unit
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unit
 
Digital design chap 2
Digital design    chap 2Digital design    chap 2
Digital design chap 2
 
Doc 20180130-wa0006
Doc 20180130-wa0006Doc 20180130-wa0006
Doc 20180130-wa0006
 
GSP 215 RANK Achievement Education--gsp215rank.com
GSP 215 RANK Achievement Education--gsp215rank.comGSP 215 RANK Achievement Education--gsp215rank.com
GSP 215 RANK Achievement Education--gsp215rank.com
 
GSP 215 RANK Become Exceptional--gsp215rank.com
GSP 215 RANK Become Exceptional--gsp215rank.comGSP 215 RANK Become Exceptional--gsp215rank.com
GSP 215 RANK Become Exceptional--gsp215rank.com
 
Logic Fe Tcom
Logic Fe TcomLogic Fe Tcom
Logic Fe Tcom
 
Computer Organization And Architecture lab manual
Computer Organization And Architecture lab manualComputer Organization And Architecture lab manual
Computer Organization And Architecture lab manual
 
Digital Electronics Question Bank
Digital Electronics Question BankDigital Electronics Question Bank
Digital Electronics Question Bank
 

Viewers also liked

Viewers also liked (18)

παρουσίαση Merry christmas europe
παρουσίαση Merry christmas europeπαρουσίαση Merry christmas europe
παρουσίαση Merry christmas europe
 
One_Child_Transmedia_Storytelling1
One_Child_Transmedia_Storytelling1One_Child_Transmedia_Storytelling1
One_Child_Transmedia_Storytelling1
 
Advisory Board 09Jan2014
Advisory Board 09Jan2014Advisory Board 09Jan2014
Advisory Board 09Jan2014
 
Homefront wwii pt 2
Homefront wwii pt 2Homefront wwii pt 2
Homefront wwii pt 2
 
Rediseño Celusal
Rediseño CelusalRediseño Celusal
Rediseño Celusal
 
Lean Stack - Um jeito simples de iniciar com Lean Startup
Lean Stack - Um jeito simples de iniciar com Lean StartupLean Stack - Um jeito simples de iniciar com Lean Startup
Lean Stack - Um jeito simples de iniciar com Lean Startup
 
Homefront wwii pt 1
Homefront wwii pt 1Homefront wwii pt 1
Homefront wwii pt 1
 
Cisco intranet deep dive case study webinar presentation Jan 2016
Cisco intranet deep dive case study webinar presentation Jan 2016Cisco intranet deep dive case study webinar presentation Jan 2016
Cisco intranet deep dive case study webinar presentation Jan 2016
 
Chap1
Chap1Chap1
Chap1
 
Finanzas
FinanzasFinanzas
Finanzas
 
2011.11.02 proyecto cniam
2011.11.02 proyecto cniam2011.11.02 proyecto cniam
2011.11.02 proyecto cniam
 
Form pedidodistribuidor 2012
Form pedidodistribuidor 2012Form pedidodistribuidor 2012
Form pedidodistribuidor 2012
 
Ficha técnica projeto
Ficha técnica projetoFicha técnica projeto
Ficha técnica projeto
 
|S|.@.|S|.^.^
|S|.@.|S|.^.^|S|.@.|S|.^.^
|S|.@.|S|.^.^
 
Cfq7 exercicios3
Cfq7 exercicios3Cfq7 exercicios3
Cfq7 exercicios3
 
Relatório matilde
Relatório matildeRelatório matilde
Relatório matilde
 
Starbene Articolo EFT
Starbene Articolo EFTStarbene Articolo EFT
Starbene Articolo EFT
 
Treinamento para quem trabalha na área de ensino
Treinamento para quem trabalha na área de ensinoTreinamento para quem trabalha na área de ensino
Treinamento para quem trabalha na área de ensino
 

Digital en4

  • 1. Question 1 For the circuit in figure 2, determine the output if the input are: a. [A] = 01012 and [B] = 11012 b. [A] = 01112 and [B] = 11112 Question 2 (4 Marks) (4 Marks)
  • 2. Question 3 Design an asynchronous counter that will count in a sequence of 6, 5, 4, 3, 2, 1 and repeat. Only J-K flip-flops that have two active low control inputs PRE and CLR are allowed to be used. Briefly explain the operation of the design. (20 Marks)