1. Zhenglei, Gong (龚正磊)
fafnirken@outlook.com
13817043351
PROFESSIONAL EXPERIENCE
Intel Asia-Pacific Research & Development Ltd.
2014/12 – Now: Performance & Platform Integration Engineer
- The OS auto-installer for BKC(best known configuration)
Create the auto-installer for Red Hat & Suse. Modifiy the OS
patches, integrate the drivers and test tools into the OS install image.
Automatically and speed up the OS installation process reduce at
least 50% time effort.
Working closely with team, figure out the BKC build process and test
frame work.
- Benchmark performance tuning
In charge of the different benchmark tuning on Intel server platform
with different OS, including SPECCPU2006, SPECPower, Stream.
Trouble shooting the performance regression and dig out the
performance potential.
Collaborate with international team about the technical issue
2013/01 – Now: Performance Engineer
- Working with US PnP (Power & Performance) team, ramp up SH
PnP team capability, finish the Baytrail-T platform performance
transition and PR release routine measurement/regression issue
debugging.
- Working on the Baytrail-T RVP/FFRD 64bit Windows benchmark
measurement, tuning and issue analysis/debugging. Collaborating
with OR PnP team, fulfill the BYT 64bit PV.
- Responsible for Baytrail-CR customer reference design board
Android/Windows benchmark tuning and measurement, co-working
with different stack holder on issue debugging, fulfill it to PV on
schedule
- Coordinated with internal stakeholders and worldwide vendors on
the issue debugging and test cases development;
- Onsite factory NPI support.
2011/03 – 2012/12: Validation Engineer

2. - Responsible for test cases design and optimization on server
platform component functionality test, compatibility test and usage
mode test;
- Initiated and completed test methodology reformation
- Responsible for internal validation execution on HDD RVI, platform
performance test and OS certification(Windows, VMware, RHEL
and SLES);
- Led platform validation effort on 4 Thurley and 4 Romley server
products in sustaining phase;
- Coordinated with internal stakeholders and ODM counterparts on
validation resource allocation, test case planning, test progress
monitoring, test execution audit, test reporting and issue
investigation to achieve high quality and on schedule product
delivery;
- Led validation effort, including Platform Validation, BIOS/FW
Evaluation and tracker/defect management on 1 customization SKU
and achieved high customer satisfaction by quick response on
customer demand and flawless validation execution
- Succeed the component verification demand from factory/customer,
provided the reliable quality and cost-down the extra factory re-work
effort and abandonment charge.
Inventec , Shanghai RD Center, System Integration Test Department
2007/08 – 2010/12: SIT engineer
- Responsible for design verification and relevant issue debugging
on Server/Storage Systems;
- Responsible for test case design and optimization on functionality
test;
- Established a PXE based test environment to improve validation
efficiency;
- Executed compatibility test, stress test, design verification test and
OS certification on 5 Tylersburg base products.
Personal Particular:
Gender male
Date of Birth February 15, 1985
Education Background
2003/09 -- 2007/06： Bachelor of Electronic Engineering
Dong Hua University, Shanghai, China