Chapter7 circuits

Elec3017:
Electrical Engineering Design
Chapter 7: Circuits and Communication
A/Prof D. S. Taubman
September 1, 2008

1 Purpose of this Chapter
This chapter cannot possibly take the place of an electronics course, so it is
assumed that you already have the basics under your belt. You may already
have seen a number of the circuit ideas introduced in this chapter, but then you
might not have. Our goal is to be as practical as possible, pointing out some
of the configurations and concepts with which every electrical engineer should
have some familiarity.
Seeming as all the lecture notes for this course are being created for the first
time, it is not possible to provide a comprehensive written coverage here at the
present time. For this reason, many sections of these notes serve only to indicate
the circuit configurations which are discussed during lectures and provide you
with some brief pointers. If, for some reason, you are unable to attend lectures
(this is generally a mistake), you can use these pointers to conduct your own
research. A good general reference is [1].
Many electronics design projects end up involving some form of communica-
tion, in the presence of noise and interference. These projects tend to be done
badly, due to a lack of knowledge of the fundamental principles. In Section 5,
we attempt to bridge this knowledge gap, by providing a minimal treatment
of the concepts of matched filtering and receiver synchronization, with circuit
examples.

2 Voltage Sources
Topics covered are as follows:

• Regulated power supplies
• Establishing a voltage reference with zener diodes — remember to use a
ceramic capacitor to reduce high frequency noise.

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°Taubman, 2006 ELEC3017: Circuits and Communication Page 2

• Establishing a voltage reference using a forward biased diode — remember
temperature sensitivity (Ebers-Moll equation).
• A few words about temperature stabilized voltage reference IC’s.

3 Driving Circuits

• Driving solenoids and relays — remember fly-back diodes and snubber cir-
cuits.
• Driving LED’s and LED displays
• Driving digital transmission lines — remember R-C transient suppression
circuits.

4 Opamp Circuits

• Inverting, non-inverting, summing and differential amplifiers
• Peak detectors and recifier circuits
• Digitally controlled integrators — circuits and choosing suitable compo-
nents

5 Communications
Since the material in this section is more difficult than the others, we provide
some additional explanation of the theory here. We cannot afford to be con-
cerned with general communication theory, so we will focus primarily on the
problem of robustly detecting codes (i.e., signal patterns) and modulated bi-
nary data sequences in the presence of noise and interference. The methods
described here can be used with RF, IR or even audio physical communications
media.

Sidebar: The word “media” is plural. Its singular form is “medium.” Thus, an
IR link forms a single communications medium, whereas IR and RF are
two different communications media.
Totally unrelated sidebar: While we are on singular and plural forms of
technical English terms, here is one common error that grates most deeply
upon the ear: The word “criterion” is the singular of “criteria.” Please get
this around the right way!!!

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5.1 Mathematical Description of the Transmitted Signal
At a fundamental level, we are concerned with transmitted signals of the fol-
lowing form: X
x (t) = sk · g (t − kT ) (1)
k

Here, T is the symbol period, sk is the k th symbol value, and g (t) is known
as the shaping pulse. Equation (1) states the transmitted signal is formed by
concatenating scaled copies of the shaping pulse. During the first symbol period
(first T seconds), x (t) is equal to g (t) scaled by s0 . During the second symbol
period, x (t) is equal to g (t − T ) scaled by s1 — i.e., delay g (t) by T seconds, to
shift it into the second symbol period, and then multiply by s1 — and so on.
For simplicity, we restrict our attention here to the following scenarios:

Repeating code: In this case, sk = 1 for all k so that x (t) is a periodic
waveform, with period T , the first period of which is given by g (t). We
think of g (t) as some kind of code, which is used to indicate the presence
of a transmitter. The goal of the receiver, in this case, is to figure out
whether or not the code is being transmitted and hence to deduce whether
the transmitter is nearby. A typical application of this is the garage door
opener. Each garage door looks for a specific code g (t), whose presence
indicates that the door should be opened (or closed, if it is already open).
The code g (t) should have a high degree of uniqueness and other garage
door codes, or randomly generated codes, should have an extremely low
probability of being detected by the receiver. Other codes may be regarded
as sources of interference. The reason for repeating the code g (t) is to give
the receiver time to lock onto the pattern. It may require many repetitions
before the receiver can correctly detect the code in a robust manner — more
on this shortly.
On-off keying: In this case, sk ∈ {0, 1}, so that in each symbol interval, the
canonical shaping pulse g (t) is either present or absent. Presence or ab-
sence may be interpreted by the receiver as a binary digit, so that each
symbol period has the opportunity to signal a single bit.
Antipodal signalling: In this case, sk ∈ {−1, 1}, so that in each symbol inter-
val, either g (t) or −g (t) is transmitted. Again, this allows for the trans-
mission of a single binary digit in each symbol period. One important
advantage of antipodal signalling over on-off keying is that the receiver
need only decide whether the received signal looks more like g (t) or its
inverse within each symbol period — this decision is essentially indepen-
dent of the amount by which the signal may have been attenuated over
the transmission medium. For on-off keying, on the other hand, attenua-
tion in the transmission medium biases the detection process toward the
detection of a 0 (off). On the other hand, antipodal signalling presents
greater challenges for synchronization — particularly for the recovery of
the transmitter’s symbol clock at the receiver.

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5.2 Matched Filters for Optimal Reception
For the sake of this simple treatment, we will regard the signal recovered by
the receiver as a scaled copy of the transmitted waveform plus additive white
Gaussian noise. We write this as

y (t) = αx (t) + n (t) (2)
X
= αg (t − kT ) · sk + n (t)
k

An important property of truly white noise processes is that they have infinite
power. To see this, let ΓN (f ) be the power spectral density of the noise process,
as a function of frequency f . For a truly white noise process, ΓN (f ) = N0 /2
is constant1 , for all frequencies. Now the noise power in the time domain is
expressed by the variance of n (t). That is,
Z ∞
£ ¤
σ 2 = E n2 (t) =
N ΓN (f ) df = ∞!!
−∞

What this means is that instantaneously sampling a truly white noise waveform
n (t) at any given time instant t will produce sample values of infinite magnitude
with probability 1.
This might sound ridiculous at first. Of course, the noise cannot have infinite
power. However, its power spectrum is often well approximated as flat over all
frequencies of interest, i.e.
N0
ΓN (f ) =
2
The trick, then, is to filter the signal before sampling it, in order to avoid the
amplitude of the sampled noise process far exceeding that of the signal of inter-
est. Filtering the noise process limits the range of frequencies over which ΓN (f )
departs significantly from 0, which drastically reduces the value of σ 2 produced
N
by the above integral. This is a very real phenomenon. For communication
systems, we don’t just take samples of the received waveform and then process.
We should always include some kind of analog filter.
Fortunately, the best kind of analog filter depends on the shaping pulse g (t)
alone, and can often be implemented or approximated quite simply with the aid
of a switched opamp integrator. This best filter is called a matched filter, but
it is most easily understood and implemented if you don’t think of filtering at
˜
all. Instead, let h (t) be any scaled version of g (t); that is,
˜
h (t) = βg (t) (3)

Suppose that the receiver is perfectly synchronized with the transmitter. Then
the variable which best indicates what was transmitted in symbol period k —
1 We adopt here the usual convention of writing N /2 for the magnitude of the two-sided
0
power spectrum (having values for both positive and negative frequencies). This means that
the power passed by a band-pass filter with passband given by B0 ≤ |f | ≤ B1 is equal to
N0 · (B1 − B0 ).

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i.e., between time kT and (k + 1) T — is
Z T
rk = ˜
y (t + kT ) · h (t) dt (4)
0

Putting equation (2) into the above equation, we see that
Z T Z T
rk = sk · αβ g 2 (t) dt + β g (t) n (t) dt
0 0
= sk · αβEg + n0
k

Here, Eg denotes the total energy in the shaping pulse2
Z T
Eg = g 2 (t) dt
0

. It can be shown that the noise term, n0 is a zero mean Gaussian random
k
variable with variance
N0 2
σ2 0 =
N β Eg
2
p
Now, since the the standard deviation of n0 (i.e., σ N 0 ) varies as β Eg and the
k
magnitude of the transmitted signal component, sk · αβEg , varies as αβEgpit is
,
clear that the key to robust reception is to make αEg much larger than Eg .
There are three ways to do this:

1. Make α as large as possible — this corresponds to making the receiver more
eﬃcient, or bringing it closer to the transmitter, so that it receives a larger
portion of the transmitted signal power.
2. Make the amplitude of g (t) as large as possible — this corresponds to
increasing the transmitter power.
3. Make the duration of g (t) as large as possible — this corresponds to slowing
down the communication, integrating for a longer period at the receiver
before deciding what was transmitted.

Given that receiver eﬃciency and transmitter power are likely to be constrained
by technology and/or regulatory standards, the third mechanism is the only
thing that a designer has direct control over. In summary, the longer you inte-
grate at the receiver, the more robust your detection mechanism will be.
The above discussion may still seem rather abstract. To bring things sharply
into focus, let us consider how to implement the receiver model in equation
(4). Suppose, for simplicity, that g (t) is a square wave pattern, consisting of
alternating −1’s and 1’s, as shown in Figure 1. In this case, the matched receiver
2 We think of the energy in a signal as the integral of its squared amplitude. The origin

of this convention is that we think of the signal as a voltage waveform, applied across a 1Ω
resistor. Of course, we can replace the load resistor with R, and then the energy is just scaled
by 1/R, but this is of no fundamental importance.

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g (t )
+1

t

−1
0 T

Figure 1: Example shaping pulse.

y(t) S2

S1 rk
R2
C
R1 R1

S3

Figure 2: Matched ﬁltering receiver for square wave shaping pulses. The circuit
is an integrator, driven either by y (t) or −y (t), depending on the state of the
MOSFET switches (e.g. those provided by a CD4066 quad bilateral switch IC)
S1 and S2 . Switch S3 is used to dump charge at the start of each symbol period.
The output rk holds the correct value at the end of each symbol period.

can be implemented using the circuit shown in Figure 2. Here, switch S1 is
closed when g (t − kT ) is +ve, while switch S2 is closed when g (t − kT ) is −ve.
The factor β in equation (3) depends on the selection of parameters (resistors
and capacitor) in the opamp integrator. The switch S3 is closed very brieﬂy at
the start of each symbol period. It is important that the on resistance of this
switch is as small as possible, so that very little of the symbol integration period
need be wasted in dumping the capacitor’s charge in preparation for the next
period. To simplify things, you might design your shaping pulse g (t) to contain
an initial period in which g (t) = 0, during which capacitor charge dumping can
occur. The longer this initial period is, the easier it will be for a receiver to
fully dump the charge on the integrator’s capacitor, but this charge dumping
period will also reduce the value of Eg , which determines the communication
robustness. We can now consider the circuit shown in Figure 2 in light of the
three communication scenarios outlined at the beginning of this section.

Repeating code: In this case, our objective is simply to determine whether

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or not the transmitter is present. The output rk from the integrator at
the end of one symbol period, is given by
½
αβEg + n0 if transmitter present
k
rk =
n0
k if no transmitter
Evidently, both the presence and absence of a transmitter may produce
non-zero values for rk , so we must determine a threshold κ and check
whether or not rk > κ. The threshold should be some multiple of the
RMS noise amplitude, e.g., κ = 4σ N 0 or more. In order to make detection
more reliable, we should consider integrating for multiple symbol periods.
For example, we can always think of x (t) as being generated by symbols
with period 2T , each of which is of the form g (t) + g (t − T ) — i.e., two
copies of the g (t) shaping pulse. These double length symbols have twice
the energy, so the detection process will be more immune to noise; the
√
value of σ N 0 (and hence κ) increases by 2, but the signal received when
a transmitter is present increases by a factor of 2. By integrating for
a large number of symbol periods, we can reliably detect extremely weak
transmitted signals in the presence of a large amount of noise. On the other
hand, the eﬀect of non-idealities in our integrator will become accentuated
as we try to integrate for longer periods of time.
On-oﬀ keying: In this case, our objective is to determine whether or not the
symbol transmitted in each symbol period is a 0 or a 1. To do this,
we again compare the value of rk with a threshold κ at the end of each
symbol period. In this case, integrating for multiple symbol periods is
not an option for improved reliability at the receiver. Thus, to achieve
the desired level of robustness, we must carefully select the symbol period
length used by the transmitter.
Antipodal signalling: In this case, we again check the value of rk produced
by the integrator at the end of each symbol period. The possible values
are given by ½
αβEg + n0 k if sk = 1
rk =
−αβEg + n0 if sk = −1
k
Noting that the noise has zero-valued mean, so that n0 is as likely to
k
be positive as negative, the optimal detection strategy is to decide that
sk = 1 if rk > 0 and sk = −1 if rk < 0. One nice property of antipodal
signalling is that we don’t need to select a threshold at all (if you like, the
threshold is always 0). All we need is to detect the sign of the integrator
output at the end of each symbol period. Again, robustness to noise can
be increased by extending the duration (and hence energy) of each symbol
period.

5.3 Design of Shaping Pulses
The shaping pulse is a kind of code that the receiver is looking for. We have al-
ready said that long shaping pulses (i.e., long symbol periods) will give increased

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robustness to noise and interference. At the end of the previous sub-section, we
considered shaping pulses which alternate between +1 and −1. Smoother pat-
terns (typically windowed sinusoids) can be much more interesting from the
perspective of bandwidth preservation, but we will not consider them here due
to limited time, and the increased practical complications of matched filtering.
For your ELEC3117 project, strict bandwidth conservation is unlikely to be a
significant issue.
For practical reasons, you might not have the luxury of transmitting
both negative and positive levels. For example, if you are using an IR (in-
frared) system, you only have the opportunity to transmit positive levels of
light. As another example, you might well be using pre-existing RF modula-
tion/demodulation modules which give you access only to the amplitude of the
modulated RF signal. You can readily obtain 433MHz transmit/receive mod-
ules of this form from electronics hobby stores. In any event, the best way to
work in such an environment is to add a constant to the otherwise signed signal
x (t) so as to render it strictly positive. Thus, for example, if g (t) consists of
an alternating sequence of 1’s and −1’s, you have only to add 1 to x (t) to get
a signal which alternates between 0 and 2. It turns out that this need not have
any impact upon our optimal matched filtering receiver, so long as the matched
filter is insensitive to the addition of constant signal offsets. To arrange for this,
it is sufficient to ensure that the shaping pulse has a mean value of 0 (prior to
adding offsets), i.e.,
Z T
g (t) dt = 0
0

This simply means that g (t) spends as much time in the 1 state as it does in
˜
the −1 state. The matched filter h (t) will then also have have zero mean. Even
if you are not forced to signal only with positive amplitudes, it is always a good
idea to arrange for the shaping pulse to have zero mean, since then the receiver
will be insensitive to constant voltage offsets which might appear in your circuit
for any number of reasons — e.g., opamp input voltage offsets, background light
in an optical signalling scheme, etc.
The second consideration we mention here applies when you wish to dis-
tinguish between multiple different transmitters, as in the garage door opener
example. Suppose each transmitter has a separate shaping pulse (or code), gi (t),
where i is the index of the transmitter. It is important that the matched filter
for transmitter i is insensitive to the shaping pulse used by another transmitter
j 6= i. That is, we want
Z T
gi (t) gj (t) dt ≈ 0, whenever i 6= j.
0

More generally, we need to recognize that the various transmitters are not
likely to be synchronized with each other. This means that interference from
transmitter j may be any shifted copy of gj (t), as far as the matched filter for
transmitter i is concerned. Ideally, then, we would like the following property

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to hold:
Z T
gi (t) gj (t − τ ) dt ≈ 0, for all i 6= j and all τ ∈ (−T, T )
0

Equivalently, we want

gi (t) ∗ gj (−t) u 0, ∀i 6= j

One way to arrange for this is to make gi (t) and gj (t) oscillatory waveforms
with different frequencies. In the case where the transmitted signal is a repeating
code (as in the garage door opener), we know that the signal produced by any
two transmitters, i and j, are repeating patterns with different shaping pulses
gi (t) and gj (t). In this case, the objective of good code design is to make sure
that
Z T
gi (t) gj (t − τ mod T ) dt ≈ 0, for all i 6= j and all τ ∈ [0, T ]
0

The important difference here is that we are interested in the cyclically shifted
version of gj (t) — shifted by τ and then wrapped around in the symbol interval
[0, T ].
In general, these “orthogonality” conditions cannot be achieved exactly in
practice, but they can help you to understand the desirable properties for shap-
ing pulses. If the shaping pulses are long and are chosen randomly, you can
interpret codes from other transmitters as random noise. Again, the longer
your receiver can integrate for, the more robustly it will discriminate its own
transmitter’s signal from the other “noise” signals.

5.4 Clock Synchronization
In the preceding treatment, we have assumed that the receiver is perfectly syn-
chronized with the transmitter. That is, the receiver is assumed to know exactly
when each symbol period starts and finishes, so that it can correctly multiply
˜
the received signal by h (t) and integrate over the relevant period. In practice,
the receiver is not normally synchronized a priori, so that synchronization is an
extremely important element in the overall detection process. Synchronization
is a big topic, which we cannot fully cover here, so we will provide only sufficient
information to get you going.
Let us assume that both the transmitter and the receiver use stable crys-
tal oscillators whose frequencies are very close to each other — e.g., to several
parts-per-million. This means that the initially unknown delay between the
transmitter’s clock and the receiver’s clock changes only very slowly. Just how
slow you can make this (or need to make this) will depend on the details of
your design. The most obvious receiver synchronization strategy is a kind of
trial-and-error approach. To understand this, consider the case of the endlessly
repeating code (as in the garage door opener example), and suppose we use the
matched receiver shown in Figure 2. The output of the receiver rk , is maximized

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when the transmitter and receiver use exactly the same symbol periods. Since
the switches in the receiver are operated by a digital logic circuit, all that is re-
quired is a sequential state machine that progressively adjusts the window over
which integration occurs, hunting for the window which maximizes rk . That is,
the receiver forms Z T
rτ k = ˜
x (t + kT + τ k ) h (t) dt,
k
0
incrementing the delay τ k , in each successive symbol period k, until it has tried
value of τ k which span the interval [0, T ), at which point it determines the
τ
value of τ k which yielded the largest value of rk k . If all we are doing is trying
to determine whether or not a transmitter is present, we simply compare this
τ
maximum value of rk k with the detection threshold κ, discussed above3 . We
need, of course, to decide on a step size

∆τ = τ k+1 − τ k .

This is simply the amount of extra delay we add at the end of one integration
period (of duration T ) before commencing the next integration period. The
number of periods that we will need to consider is equal to T /∆τ , so it will
take us T 2 /∆τ seconds to find the best match. There is thus a clear trade-off
between the robustness achieved by integrating for long periods of time (large
T ) and the delay precision ∆τ which can be achieved within a given amount of
time.
The above simplistic hunting strategy can be improved in a number of ways,
if required. The classic approach is to perform an initial hunt for the delay τ ,
using a coarse step size ∆τ , and integrating for only a short period of time (e.g.,
only one symbol period, or even a fraction of a symbol period). This first stage,
τ
produces a number of promising candidates which yield largish values for rk k ,
after which a second stage considers just these few candidates, integrating for
longer, and making fine adjustments to τ k . To do this under digital control,
you would probably need to incorporate an A/D converter into your design,
together with an FPGA or micro-controller to manage the hunting algorithm.
This adds a level of complexity that you might not be prepared to consider
within the scope of your ELEC3117 project, but it is good to be aware that
such possibilities exist.
So far, we have considered only the case where the signal x (t) consists of
a repeating code. This conceptually allows us to hunt for a match, for as long
as we like, since every symbol period should be the same. If on-off keying is
used, you can use essentially the same strategy to hunt for an initial lock to
the transmitter’s symbol clock, bearing in mind that your initial estimate for
τ k might be corrupted by the fact that the optimal delay is tested (integrated)
during a symbol period when the transmitted symbol is 0. To avoid this, you
may hunt through multiple iterations of the sequence of possible delays and you
might design your transmit strategy to include a long period during which the
3 Equivalently, τ
we compare each rk k with κ and report that the transmitter exists when a
value is found which exceeds κ.

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symbol which is transmitted is constantly equal to sk = 1. Once the initial lock
has been obtained, the ongoing decoding process needs to be prepared to make
minor adjustments to the symbol clock, inserting or removing a clock cycle every
so often from the receiver timing sequence. One way to do this is to run multiple
matched filter circuits in parallel, each operating with a slightly different delay
(e.g., one with a delay slightly less than the current estimated value, and one
with a delay slightly larger than the current estimated value). The matched
filter which yields the largest value for rk indicates the best estimate of the
delay to be used during the next symbol decoding period. If the symbol is
decoded as a 0, no adjustment is made, since there is no useful synchronization
information in x (t), otherwise, a 1 is decoded and the symbol clock delay is
adjusted as appropriate for the next symbol.
The above strategy can also be used for antipodal signalling, except that a
good lock to the symbol clock is indicated by the magnitude (i.e., the absolute
value) of rk , regardless of whether it is +ve or −ve. To ensure that the initial
hunt for a good symbol lock works correctly, it is a good idea to design your
shaping pulse g (t) such that it is not close to a shifted version of −g (t). Thus,
a periodic square wave pattern for g (t) would not be a good choice.

5.5 Modulation and Variations on the Theme
You are no doubt familiar with the concept of amplitude modulation, where
a periodic waveform (usually a sinusoid) is scaled by the information bearing
symbols. Modulation is in fact already covered by the description provided in
the preceding section. On the one hand, we can always define g (t) to be the
relevant oscillatory waveform, in which case sk provides the modulating ampli-
tude. More generally, we can construct our shaping pulses from the product
of a high frequency carrier waveform c (t), and a more slowly varying envelope
function ρ (t), i.e.,
g (t) = c (t) · ρ (t)
Here, ρ (t) has bounded support, of duration T seconds, whereas c (t) can be an
unbounded oscillatory carrier.
In principle, nothing stops us from applying the techniques described in the
preceding sections for optimal matched receiver design and clock recovery. In
practice, however, there is one problem. During clock recovery, it is important
that our receiver’s search precision ∆τ is significantly smaller than a single cycle
of the carrier, since otherwise the match may be very poor. However, there are
usually a very large number of cycles of the carrier in each symbol period. This
means that T /∆τ is very large — thousands, millions, even billions, depending
upon the context. In view of this difficulty, the clock recovery system is generally
decomposed into two phases: carrier clock recovery; and symbol clock recovery.
Once the carrier has been recovered, we can use a much coarser step size ∆τ to
synchronize the symbol clock, so long as the symbol period T is a multiple of

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the carrier period. To see this, note that equation (4) can be written
Z T
rk = ˜
y (t + kT ) · h (t) · dt
0
Z T
= y (t + kT ) · βc (t) ρ (t) · dt
0
Z T
= β [y (t + kT ) c (t + kT )] ·βρ (t) · dt
0 | {z }
d(t)

In the third line of the above equation, we have used the fact that c (t) =
c (t + kT ) for all integers k. Evidently, it is sufficient to demodulate the re-
ceived signal y (t) by multiplying it by the recovered carrier c (t), after which
the matched filter operates on the demodulated signal d (t), using the effective
shaping pulse, ρ (t). The step size ∆τ required to lock onto the symbol clock
need only be small in relation to the features in ρ (t), which is generally a much
lower bandwidth signal than g (t).
For carrier clock synchronization, there are a number of techniques which
can be employed. To ensure a unique result, it is best if the envelope component
of the shaping pulse has a non-zero mean value. For the sake of simplicity, we
will assume that Z T
ρ (t) · dt > 0 (5)
0

In the simplest case, ρ (t) ≥ 0, ∀t, but this is not strictly necessary. Equation
(5) is the condition required for a pilot tone to exist, meaning that the received
signal y (t) contains some component of the original carrier waveform. To see
this, note that demodulating by the correct carrier leaves

d (t) = y (t) c (t)
= αx (t) c (t) + n (t) c (t)
X
= αc2 (t) sk ρ (t − kT ) + n (t) c (t) ,
k

which has a positive average value.
One way to lock onto the carrier, then, is to adjust the phase of the local
carrier at the receiver until a low-pass filtered version of the demodulated signal
d (t) becomes as large as possible. Indeed, this is one method that can be
used. A more common strategy, however, is to generate a quarter cycle delayed
version cq (t) of the ideal carrier waveform and arrange for y (t) cq (t) to have
an average value of 0. This is the basic idea behind the common phase locked
loop (PLL). Let us be more precise. Let c0 (t) be the carrier signal which
the receiver will use to demodulate y (t). Then we want the average value of
y (t) c0 (t) to be as positive as possible. Now consider the half cycle delayed
carrier, c0 (t − T /2). Assuming that the carrier has a 50% duty cycle, we have
c0 (t − T /2) = −c0 (t), so that y (t) c0 (t − T /2) should have an average value

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y(t) cq(t)>0

cq(t)<0 -cq(t)y(t)
R2
C
R1 R1
R3
c0(t) Freq. Voltage
Controlled δf
Divider
cq (t) (counter) Oscillator
(VCO)

crystal

Figure 3: Simple phase locked loop, using a 1’st order low-pass filter (formed
by R3 and C), an integrator circuit driven by positive and negative versions
of y (t), and a voltage controlled oscillator (VCO). The output of the VCO is
divided down to form the receiver’s carrier clock c0 (t) and a quarter sample
delayed version cq (t) = c0 (t − T /4).

which is as negative as possible. Between these positive and negative extremes,
we expect y (t) c0 (t − T /4) to have an average value of 0. If we find that the
average value of y (t) c0 (t − T /4) is positive, the receiver’s carrier clock c0 (t)
must be running ahead and needs to be delayed a little. Similarly, if the average
value of y (t) c0 (t − T /4) is negative, the receiver’s local version of the carrier
is running behind and needs to be advanced a little. This is achieved by the
simple PLL circuit shown schematically in Figure 3.
Before concluding this section, we note that there is no need to use the same
shaping pulse g (t) for each symbol sk . We can generalize equation (1) to
X
x (t) = gsk (t − kT )
k

where there is a distinct shaping pulse gsk (t) for each possible symbol value
sk . For binary signalling, we let sk take one of the values 0 or 1 and define
two shaping pulses g0 (t) and g1 (t). In the preceding treatment, each of these
shaping pulses was a scaled version of the single waveform g (t). However,
this is not necessary. A popular alternative is to use oscillatory waveforms (or
carriers) with two frequencies — this is called frequency modulation. These could
be sinusoidal carriers, square waves or anything else, but the signal generation
and matched filtering processes become particularly simple for square waves,
even if the bandwidth spread is not so good. If g0 (t) and g1 (t) are not scaled
versions of the same waveform, we will need two separate matched filters (i.e.,
two integrators) in the receiver, one for each scaling function. In each symbol

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period k, we form
Z T Z T
rk,0 = ˜
y (t + kT ) h0 (t) dt and rk,1 = ˜
y (t + kT ) h1 (t) dt
0 0

If rk,0 is larger than rk,1 we decode the symbol as sk = 0. Otherwise, we decide
˜
that sk = 1. This is an optimal detection rule so long as h0 (t) = βg0 (t) and
˜
h1 (t) = βg1 (t) involve the same scaling factor β. For maximum robustness, the
matched filter for rk,0 should not respond to g1 (t) and the matched filter for
rk,1 should not respond to g0 (t). This can be arranged by designing g0 (t) and
g1 (t) as orthogonal signals, i.e.,
Z T
g0 (t) g1 (t) dt = 0
0

Carrier and symbol clock synchronization can be carried out using essentially
the same techniques which we described above.

5.6 Digitally (or Software) Defined Radio
In the foregoing discussion, we have supposed that the inegration process re-
quired for matched filtering is carried out in the analog domain. An alternative
approach is to convert the incoming signal y (t) into a sampled digital signal

y [n] = y (t)|t=n/fs (6)

with sampling frequency fs , and then replace all inegration operations with
sums. Thus, for example, equation (4) becomes
T fs
X
rk = ˜
y [n + kT fs ] · h [n] .
n=0

This approach is fundamentally equivalent to analog integration, so long as the
following conditions are met:

1. The sampling process in equation (6) must not involve significant aliasing.
That is, prior to sampling the continuous received signal y (t), it must be
passed through a suitable anti-aliasing filter which strongly attentuates
components with frequencies above fs /2. The most important thing that
this does is to remove noise power. Without the anti-aliasing filter, noise
power is effectively amplified by sampling, which renders the receiver much
less robust to errors.
2. The A/D converter used during sampling needs sufficient numerical preci-
sion to cover the range of expected signal amplitudes, without adding too
much noise of its own (due to quantization). In some applications, this
might require quite a high precision A/D converter.

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Ideally, the sampling clock has the property that T fs is an integer, meaning
that there are a whole number of samples in each symbol period. One way to
arrange for this is to drive the sampling clock from a PLL which is locked to an
underlying carrier frequency, assuming that there is such a carrier and that the
symbol period is designed to be an integer multiple of the carrier period. This,
however, still relies on the presence of analog components for carrier synchro-
nization and demodulation. For an all-digital receiver, the situation is a bit more
complex. The simplest approach is to use a sampling clock frequency which is
so high that we can represent the symbol period (and any carrier period) as a
large integer multiple of the sampling clock in the receiver, adding or removing
a sample from this period from time to time so as to achieve synchronization.
Digital processing has a number of advantages over analog matched filter-
ing. One of these is that the system is easily reconfigurable to handle different
transmission schemes; this is particularly true if the system is implemented in
software, using a DSP or general purpose CPU. Another advantage is that the
digital processor does not introduce any errors of its own, after the initial quan-
tization and aliasing distortions produced by sampling. This means that the
digital integration process does not suffer from the problems of analog compo-
nents whose gains do not match precisely — e.g., the positive and negative inputs
to the integrator in Figure 2.
Perhaps the most significant advantage of digital processing is that multiple
matched receivers can be implemented simultaneously by fast hardware proces-
sors. This is particularly important for clock synchronization. In Section 5.4,
we suggested a hunting technique for synchronizing the receiver’s clock with
the transmitter. This hunting technique requires the matched receiver to be
applied many times in sequence, shifting the clock by ∆T each time, until the
best match is found. With only one analog matched filter, this can take a long
time, since each step in the hunting process requires T seconds and the number
of steps is T /∆T . To speed the process up, multiple analog matched filters can
be implemented, but this is costly and may suffer from mismatches amongst
the parallel analog circuits. A more cost effective solution is to run multiple
digital matched filters in parallel. One way to do this is to load 2T seconds of
the received signal y [n] into memory and then to evaluate
T fs
X ∙ ¶
r (i)
= ˜ [n] , for each i ∈ 0, T
y [n + i∆T fs ] · h ∩Z
n=0
∆T

searching for the value of i which maximizes r(i) .

6 Micro-Controllers
Micro-controllers are small microprocessors which are targeted at the design of
stand-alone electronic consumer products of moderate to low complexity. The
main distinctions between a micro-controller and a general purpose CPU are:

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1. Micro-controllers are principally designed to work with their own inter-
nal RAM and programmable ROM, rather than interfacing with external
memory chips.
2. Micro-controllers normally include additional embedded functions, such
as A/D and D/A converters, LCD display drivers and the like, so as to
reduce the number of external chips that will be required for a complete
solution.
3. The main external interfaces provided by micro-controllers consist of a
collection of I/O lines. These are generally software configurable to be
used as inputs or outputs, for either analog or digital purposes, so that a
small package can be used to serve a large number of different purposes.
4. The CPU inside most micro-controllers is fairly simple, with an 8-bit or
16-bit data path and only a small set of assembly language instructions.

The features described above serve to keep chip count and power consumption
to an absolute minimum, since these are usually important issues for electronic
products. A small number of micro-controllers allow you to attach external
memory chips, but by the time you go to this amount of effort, perhaps you
should be considering a real CPU.
Micro-controllers are available from various manufacturers. For your
ELEC3117 design project, we suggest that you use either the PIC micro-
controllers from “Microchip Technology Inc.” (www.microchip.com), or one of
the TMS430 micro-controllers from Texas Instruments Inc. The PIC micro-
controllers use an 8-bit data path, while the MS430 series are 16-bit micro-
controllers. As for sourcing components and development/programming kits,
we have the following recommendations:

• The Electronics Workshop keeps stock of several micro-controllers, which
they can sell to you for a good price. The Electronics Workshop also
has quite a few PIC programming kits, with development software, which
they can lend to you for a limited period of time, subject to a deposit
(fully refundable). These kits can be used to program the afore-mentioned
chips, plus a range of other ones. If you wish to purchase your own PIC
programmer, the staff in the Electronics Workshop are happy to help you
locate suppliers, or even to arrange the purchase. Prices tend to be a
bit less than $100. The PIC micro-controllers come in easy-to-use (and
easy-to-solder) DIP packages.
• The MSP430 micro-controllers are quite a bit more difficult to work with
than the PIC series, but they are more powerful. One difficulty is the
use of a low supply voltage (typically 3.3V). The other is the fact that
all packages are of the surface mount variety (as opposed to DIP), which
can be difficult to solder or otherwise connect into your circuit unless you
have finely honed skills. Nevertheless, one very interesting product is the
MSP430 eZ430-F2013 development tool. This tool is entirely packaged in

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a device the size of a USB thumb drive, which contains a MSP430F2013
component mounted on a convenient break-out board, to which you can
solder. This development tool costs around US$20. The local supplier
for these micro-controllers is “AVNET Electronics Marketing.” We are
still trying to arrange a special rate for purchasing these devices (and the
programming tool), but you might like to contact AVNET yourself.

7 Programmable Logic
Many designs call for some significant amount of digital logic, to interface com-
ponents, implement state machines or control complex timing and addressing
sequences. Constructing this logic from discrete TTL/CMOS logic devices is of-
ten either practically infeasible or overly expensive, in terms of both component
count and power consumption. CPLD’s (Complex Programmable Logic De-
vices) and FPGA’s (Field Programmable Gate Arrays) are designed to address
exactly these situations. Both types of devices contain internal arrays of pre-
defined logic elements and flip-flops, whose interconnects can be programmed
electronically. FPGA’s tend to be much more sophisticated than CPLD’s, pro-
viding many more flip-flops, more sophisticated logic elements (usually defined
by programmable lookup tables), and often quite a bit of on-chip RAM. In fact,
modern FPGA’s are so densely integrated that it is possible to program them to
implement entire general purpose CPU’s (potentially many interacting CPU’s
on the same chip), in addition to dedicated logic and arithmetic functions.
Fortunately, most of the complexity of programming CPLD’s and FPGA’s is
abstracted for you by sophisticated design tools, which do their best to make the
internal architecture of the device transparent. All design tools support some
form of schematic capture technique to describe the digital circuit you want to
implement. To facilitate this, libraries of standard digital logic components are
provided for you to place and connect on a schematic diagram. You can then
turn your own schematics into new library components to be incorporated into
more complex designs. Ultimately, everything is built up from gates and flip-
flops, including all the standard library components. Subsequent synthesis tools
then map the configuration onto the device’s internal resources and allow you
to assign component pins to logic lines in your digital circuit. As an alternative
to schematic capture, it is possible to use a hardware description language to
describe your digital circuit. The two most popular hardware description lan-
guages are VHDL and Verilog. These are often both supported by the relevant
manufacturer’s design tools.
If you would like to learn techniques such as these and use them in your
ELEC3117 design project, the Electronics Workshop has some tools which will
facilitate the process. For relatively simple designs, you can use the XC9572
Xilinx CPLD, which comes in a square 44-pin package. The Electronics Work-
shop has a number of programming tools which can be used to program the
XC9572 via a parallel port; once you are done, the chip can be removed and
mounted on a socket (the workshop has these as well) which is relatively easy

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to solder to, having widely spaced pins. Alternatively, the workshop has a num-
ber of “breakout” boards which allow you to mount an XC9572 and then wire
the pins to your own breadboard using screw-type terminals — these require
no soldering, although you need to be careful to keep your leads short. The
workshop also has a number of much larger demonstration boards they can lend
you, which can be used to program and subsequently deploy a Xilinx SPARTAN
FPGA, the XC2S200. You cannot remove these chips and use them separately in
your project, but you can interface your prototype to the demonstration board
through the edge connectors which are provided. The Electronics Workshop can
offer you some help with this if required.
In order to encourage you to learn and use CPLD’s (or FPGA’s) for your
project, a demonstration of the process will be given in lectures. A number of
the lab demonstrators may also be able to help you in this regard. Software
for programming the Xilinx components can be obtained from the Electronics
Workshop and installed on your PC under an open license. This software cor-
responds to version 4.1 of the Xilinx Foundation tools. The software install and
runs without incident on Windows 98 and Windows 2000 operating systems.
Unfortunately, the software is not fully compatible with Windows XP, for the
following two reasons:

1. After running the usual install script, you will find that your Windows
XP machine does not boot up again properly. You can overcome this
problem by powering down the machine and booting again, selecting the
“Last Good Version” option. You then need to go into the “System” area
of the control panel, select the “Advanced” tab and click “Environment
Variables,” doing the following:

• Create a new environment variable named “Xilinx” and set it to the
value “C:Xilinx” — assuming you installed the development tools in
that location.
• Edit the “path” environment variable, adding “C:Xilinxbinnt” to
the path list — entries in the path list are separated by semicolons
(i.e., the “;” character).

After you have done the above, you will need to reboot your system one
more time; otherwise, when you use the Xilinx tools they will continually
report that the “Xilinx” variable has not been set.
2. The software methods for accessing the parallel port under Windows XP
are fundamentally different to those offered by Windows 98 and Windows
2000. As a result, even after following the above steps, you will not actually
be able to program the Xilinx chips from Windows XP, although you can
do everything else and bring your files to the lab or workshop to program
the chip.

To avoid the problems described above, an alternate approach is to download
the latest Xilinx development tools from www.xilinx.com. There is a free version

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for web-based download. Unfortunately, though, the install executable is nearly
1GB in size.

References
[1] P. Horowitz and W. Hill, The Art of Electronics (2 ed ), Cambridge University
Press, 1989

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