MICROCONTROLLER COURSE TITLE

SHRI MADHWA VADIRAJA INSTITUTE OF
TECHNOLOGY AND MANAGEMENT
Microcontroller
18EC46
Venugopala Rao A S
Dept. of CSE
venugopalrao.cs@sode-edu.in

Introduction to the course
• Course Outcome:
• Explain the difference between Microprocessors & Microcontrollers, Architecture
of 8051
• Write 8051 Assembly level programs using 8051 instruction set.
• Write stack related assembly level programs using 8051 instruction set and I/O
Port Interfacing and Programming.
• Write 8051 Assembly language program to handle timers/counters, serial port and
interrupts.
• Interface various peripheral devices to 8051 using I/O ports and related its
programming.
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• Module-1 - 8051 Microcontroller:
• Microprocessor Vs Microcontroller, Embedded Systems, Embedded
Microcontrollers, 8051 Architecture- Registers, Pin diagram, I/O ports functions,
Internal Memory organization. External Memory (ROM & RAM) interfacing.
• Module -2 – 8051 Instruction Set:
• Addressing Modes, Data Transfer instructions, Arithmetic instructions, Logical
instructions, Branch instructions, Bit manipulation instructions. Simple Assembly
language program examples (without loops) to use these instructions.
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• Module-3 8051 Stack, I/O Port Interfacing and Programming:
• 8051 Stack, Stack and Subroutine instructions. Assembly language program
examples on subroutine and involving loops. Interfacing simple switch and LED to
I/O ports to switch on/off LED with respect to switch status.
• Module -4 – 8051 Timers and Serial Port:
• 8051 Timers and Counters – Operation and Assembly language programming to
generate a pulse using Mode-1 and a square wave using Mode- 2 on a port pin.
8051 Serial Communication- Basics of Serial Data Communication, RS- 232
standard, 9 pin RS232 signals, Simple Serial Port programming in Assembly and C
to transmit a message and to receive data serially.
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• Module -5 – 8051 Interrupts and Interfacing Applications:
• 8051 Interrupts. 8051 Assembly language programming to generate an external
interrupt using a switch, 8051 C programming to generate a square waveform on a
port pin using a Timer interrupt. Interfacing 8051 to ADC-0804, DAC, LCD and
Stepper motor and their 8051 Assembly language interfacing programming.
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• Textbooks
1. “The 8051 Microcontroller and Embedded Systems – using assembly and C”,
Muhammad Ali Mazidi and Janice Gillespie Mazidi and Rollin D. McKinlay;
PHI, 2006 / Pearson, 2006.
2. “The 8051 Microcontroller”, Kenneth J. Ayala, 3rd Edition, Thomson/Cengage
Learning.
• Reference Books
1. “The 8051 Microcontroller Based Embedded Systems”, Manish K Patel,
McGraw Hill, 2014, ISBN: 978-93-329-0125-4.
2. “Microcontrollers: Architecture, Programming, Interfacing and System Design”,
Raj Kamal, Pearson Education, 2005.
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Microprocessor vs Microcontroller
• What is micro processor?
• A microprocessor is a computer processor where the data processing logic and
control logic is included on a single integrated circuit.
• The microprocessor contains the arithmetic, logic, and control circuitry required
to perform the functions of a computer's central processing unit.
• The integrated circuit is capable of interpreting and executing program
instructions and performing arithmetic operations
• Examples:
• Intel 4004 – The First Microprocessor.
• Intel 8085, Intel 8086, Intel Pentium 4, Intel Core i7, AMD Athlon.
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• Microprocessors
• General-purpose microprocessors
• Must add RAM, ROM, I/O ports, and timers externally to make them functional
• Make the system bulkier and much more expensive
• Have the advantage of versatility on the amount of RAM, ROM, and I/O ports
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• What is microcontroller?
• Microcontroller contains all essential components of a microcomputer such as
CPU, RAM, ROM/EPROM, I/O lines etc.
• Some single chip microcontrollers contain devices to perform specific functions
such as DMA channels, A/D converter, serial port, pulse width modulation, etc.
• E.g.: Intel 8031/8051, PIC1x, and Motorola MC68HC11 families.
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• Microcontroller
• The fixed amount of on-chip ROM, RAM, and number of I/O ports makes them
ideal for many applications in which cost and space are critical
• In many applications, the space it takes, the power it consumes, and the price per
unit are much more critical considerations than the computing power
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Microprocessor v/s Microcontroller
Microprocessor Microcontroller
contains ALU, General purpose registers,
stack pointer, program counter, clock
timing circuit, interrupt circuit
contains the circuitry of microprocessor, and
in addition it has built in ROM, RAM, I/O
Devices, Timers/Counters etc.
It has many instructions to move data
between memory and CPU
It has few instructions to move data between
memory and CPU
Few bit handling instruction It has many bit handling instructions
Less number of pins are multifunctional More number of pins are multifunctional
Single memory map for data and code Separate memory map for data and code
Access time for memory and IO are more Less access time for built in memory and IO.
More flexible in the design point of view Less flexible since the additional circuits
which is residing inside the microcontroller is
fixed for a particular microcontroller
Large number of instructions with flexible
addressing modes
Limited number of instructions with few
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Microcontrollers for Embedded Systems
• Microcontrollers for Embedded Systems
• An embedded product uses a microprocessor (or microcontroller) to do one task
and one task only
• There is only one application software that is typically burned into ROM
• On the other hand, A PC, with the embedded system, can be used for any number
of applications
• It has RAM memory and an operating system that loads a variety of applications
into RAM and lets the CPU run them
• A PC contains or is connected to various embedded products
• Each one peripheral has a microcontroller inside it that performs only one task
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• Applications of embedded systems
• Home
• Appliances, intercom, telephones, security systems, garage door openers,
answering machines, TVs, cable TV tuner, VCR, camcorder, remote controls,
video games, cellular phones, musical instruments, sewing machines, lighting
control, camera, toys etc.
• Office
• Telephones, computers, security systems, fax machines, copier, laser printer,
colour printer, paging
• Automobile industry
• Trip computer, engine control, air bag, ABS, instrumentation, security system,
transmission control, entertainment, climate control, keyless entry
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• One of the most critical needs of an embedded system is to decrease power
consumption and space
• In high-performance embedded processors, the trend is to integrate more functions
on the CPU chip and let designer decide which features he/she wants to use
• In many cases using x86 PCs for the high-end embedded applications  saves
money and shortens development time
• A vast library of software already written
• Windows is a widely used and well understood platform
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• Criteria for Choosing a Microcontroller
• Meeting the computing needs of the task at hand efficiently and cost effectively
• Speed
• Packaging
• Power consumption
• The amount of RAM and ROM on chip
• The number of I/O pins and the timer on chip
• How easy to upgrade to higher performance or lower power consumption versions
• Cost per unit
• Availability of software development tools, such as compilers, assemblers, and
debuggers
• Wide availability and reliable sources of the microcontroller
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• The 8051 family has the largest number of diversified suppliers
• Intel (original), Atmel, Philips/Signetics, AMD, Infineon (formerly Siemens),
Matra, Dallas Semiconductor/Maxim
• Intel introduced 8051, referred as MCS-51, in 1981
• The 8051 is an 8-bit processor
• The CPU can work on only 8 bits of data at a time
• The 8051 had
• 128 bytes of RAM
• 4K bytes of on-chip ROM
• Two timers
• One serial port
• Four I/O ports, each 8 bits wide
• 6 interrupt sources
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Overview of 8051 family
• There are two other members in 8051 family of Microcontroller.
• They are 8052 and 8031.
• 8052 has all standard features of 8051 with an extra 128 bytes of RAM and an
extra timer. i.e. a total of 256 bytes of RAM and 3 timers.
• It also has 8K bytes of on chip program instead of 4K bytes.
• 8031 Microcontroller is often referred as a ROM less 8051 since it has 0K bytes
of on chip ROM.
• To use this chip we must add external ROM to it.
• Two ports will be lost in the process of adding external ROM.
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Overview of 8051 family
• Comparison of 8051 family
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8051 Architecture
• Functional Diagram:
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8051 Architecture
• CPU(Central Processing Unit)
• Main part of the microcontroller that actually does all the processing works.
• It has control circuit and ALU to perform logical and mathematical operations.
• A user can not access the processor or CPU of the microcontroller.
• The CPU is internally connected or interfaced with the memory units such as
ROM and RAM.
• CPU works according to the instruction or programs stored in the ROM.
• Oscillator and Timers
• Pulse signal generator circuit which provides the pulse signal to the CPU to
complete its operation and to work with cycles per unit time.
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8051 Architecture
• It is an on-chip crystal oscillator mounted outside of the CPU.
• The crystal frequency of this oscillator is 12 MHz.
• Memory Units
• Has a ROM of 4kb and RAM of 128bytes
• The ROM is used for the preloaded or stored program and according to this
program, the CPU works.
• CPU can read or fetch data from the ROM but it can not write or store any data
to the ROM.
• RAM is used to store data temporarily during the operation or program execution.
CPU can store data into the RAM.
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8051 Architecture
• Interrupts
• The interrupt is the subroutine call that interrupts the main ongoing program
execution in the CPU and tells to execute another important task or program.
• We can say the interrupts help for the emergency operations.
• There are mainly five interrupt sources in the microcontroller 8051,
• TF0 - it is the Timer 0 overflow interrupt
• TF1 - it is the Timer 2 overflow interrupt
• INT0 - it is an external hardware interrupt
• INT1 - it also an external hardware interrupt
• R1/T1 - it is the serial communication interrupt
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8051 Architecture
• Input/Output Ports
• There are four parallel 8-bit ports such as P0, P1, P2, and P3.
• These ports are bidirectional and used to carry both address and data.
• Bus
• The system bus connects all the circuits or components(memory, timers, ports) to
the CPU.
• The system bus consists of an 8-bit data bus and a 16-bit address bus.
• The address bus helps to carry the memory addresses where the data is stored
whereas the data bus helps to carry the actual data.
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8051 Architecture
• Salient features of 8051 microcontroller:
• Eight bit CPU
• On chip clock oscillator
• 4Kbytes of internal program memory (code memory) [ROM]
• 128 bytes of internal data memory [RAM]
• 64 Kbytes of external program memory address space.
• 64 Kbytes of external data memory address space.
• 32 bit directional I/O lines
• can be used as four 8 bit ports or 32 individually addressable I/O lines
• Two 16 Bit Timer/Counter :T0, T1
• Full Duplex serial data receiver/transmitter
• Four Register banks with 8 registers in each bank
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8051 Architecture
• Sixteen bit Program counter (PC) and a data pointer (DPTR)
• 8 Bit Program Status Word (PSW)
• 8 Bit Stack Pointer
• Five vector interrupt structure (RESET not considered as an interrupt.)
• 8051 CPU consists of 8 bit ALU with associated registers like accumulator ‘A’, B
register, PSW, SP, 16 bit program counter, stack pointer.
• ALU can perform arithmetic and logic functions on 8 bit variables.
• 8051 has 128 bytes of internal RAM which is divided into
• Working registers [00 – 1F]
• Bit addressable memory area [20 – 2F]
• General purpose memory area (Scratch pad memory) [30-7F]
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8051 Architecture
• Pin Diagram:
• Pins 1 to 8 − These pins are known
as Port 1.
• This port doesn’t serve any other
functions.
• It is internally pulled up, bi-
directional I/O port.
• Pin 9 − It is a RESET pin, which is
used to reset the microcontroller to
its initial values.
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8051 Architecture
• Pins 10 to 17: Known as Port 3.
• This port serves some functions like interrupts, timer input, control signals, serial
communication signals RxD and TxD, etc.
• Pins 18 & 19 − These pins are used for interfacing an external crystal to get the
system clock.
• Pin 20 − This pin provides the power supply to the circuit.
• Pins 21 to 28 − These pins are known as Port 2.
• It serves as I/O port. Higher order address bus signals are also multiplexed using
this port.
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8051 Architecture
• Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to
read a signal from the external program memory.
• Pin 30 − This is EA pin which stands for External Access input. It is used to
enable/disable the external memory interfacing.
• Pin 31 − This is ALE pin which stands for Address Latch Enable. It is used to
demultiplex the address-data signal of port.
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8051 Architecture
• Pins 32 to 39 − These pins are known as Port 0.
• It serves as I/O port.
• Lower order address and data bus signals are multiplexed using this port.
• Pin 40 − This pin is used to provide power supply to the circuit.
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8051 Architecture
• Block Diagram
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8051 Architecture
• Block Diagram
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8051 Architecture
• Block Diagram
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8051 Architecture
• Salient features of 8051 microcontroller:
• Eight bit CPU
• On chip clock oscillator
• 4 Kbytes of internal program memory (code memory) [ROM]
• 128 bytes of internal data memory [RAM]
• 64 Kbytes of external program memory address space.
• 64 Kbytes of external data memory address space.
• 32 bit directional I/O lines
• can be used as four 8 bit ports or 32 individually addressable I/O lines
• Two 16 Bit Timer/Counter :T0, T1
• Full Duplex serial data receiver/transmitter
• Four Register banks with 8 registers in each bank
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8051 Architecture
• Sixteen bit Program counter (PC) and a data pointer (DPTR)
• 8 Bit Program Status Word (PSW)
• 8 Bit Stack Pointer
• Five vector interrupt structure (RESET not considered as an interrupt.)
• 8051 CPU consists of 8 bit ALU with associated registers like accumulator ‘A’, B
register, PSW, SP, 16 bit program counter, stack pointer.
• ALU can perform arithmetic and logic functions on 8 bit variables.
• 8051 has 128 bytes of internal RAM which is divided into
• Working registers [00 – 1F]
• Bit addressable memory area [20 – 2F]
• General purpose memory area (Scratch pad memory) [30-7F]
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8051 Architecture
• 8051 has 4 K Bytes of internal ROM. (Address space - 0000 to 0FFFh).
• If the program size is more than 4 K Bytes, 8051 will fetch the code automatically
from external memory.
• Accumulator is an 8 bit register widely used for all arithmetic and logical
operations.
• Accumulator is also used to transfer data between external memory.
• B register is used along with Accumulator for multiplication and division.
• A and B registers together is also called MATH registers.
• PSW (Program Status Word) – An 8 bit register which contains the arithmetic
status of ALU and the bank select bits of register banks.
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8051 Architecture
• The heart of the 8051 is the circuitry that generates the clock pulses by which
all internal operations are synchronized.
• Pins XTALI and XTAL2 are provided for connecting a resonant network to form
an oscillator.
• The 8051 requires an external oscillator circuit.
• The oscillator circuit runs around 12MHz.
• The crystal generates 12M pulses in one second.
• The pulse is used to synchronize the system operation in a controlled pace.
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8051 Architecture
• Typically, a quartz crystal and capacitors are employed, as shown in Figure.
• A machine cycle is minimum amount time a simplest machine instruction must
take.
• An 8051 machine cycle consists of 12 crystal pulses (ticks).
• Instruction with a memory operand needs multiple memory accesses (machine
cycles).
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8051 Architecture
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8051 Architecture
• Programming Model:
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8051 Architecture
• Closer view:
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8051 Architecture
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8051 Architecture
• The programming model of the 8051 shows the 8051 as collection of 8- and 16-bit
registers and 8-bit memory locations.
• These registers and memory locations can be made to operate using the software
instructions.
• Most of the registers have a specific function such as A or THO or PC.
• Others, which are generally indistinguishable from each other, are grouped in a
larger block, such as internal ROM or RAM memory.
• Each register, (except program counter), has an internal 1-byte address assigned to
it.
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8051 Architecture
• Some registers (marked with an asterisk*) are both byte and bit addressable.
• That is, the entire byte of data at such register addresses may be read or altered, or
individual bits may be read or altered.
• Software instructions are generally able to specify a register by its address, its
symbolic name, or both.
• W.k.t. many of the pins are used for more than one function.
• Programming instructions or physical pin connections determine the use of any
multifunction pins.
• E.g.: P3.0 may be used as a general-purpose 1/O pin, or as an input (RXD) to
SBUF, the serial data receiver register.
• The designer decides which of these two functions is to be used and designs the
hardware and software affecting that pin accordingly
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8051 Architecture
• Internal RAM organization
• Working Registers
• Register Banks: 00H to 1FH. ( 32 Bytes)
• The 8051 uses 8 general-purpose registers R0 through R7.
• There are four such register banks.
• Selection of register bank can be done through RS1,RS0 bits of
PSW.
• On reset, the default Register Bank 0 will be selected.
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8051 Architecture
• Bit Addressable RAM: 20h to 2Fh . (16 Bytes)
• The 8051 supports a special feature which allows access
to bit variables.
• This is where individual memory bits in Internal RAM
can be set or cleared.
• In all there are 128 bits numbered 00h to 7Fh.
• Being bit variables any one variable can have a value 0 or
1.
• A bit variable can be set with a command such as SETB
and cleared with a command such as CLR.
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8051 Architecture
• Example
• SETB 25h ; sets the bit 25h (becomes 1)
• CLR 25h ; clears bit 25h (becomes 0)
• bit 25h is actually bit 5 of Internal RAM location 24h.
• The Bit Addressable area of the RAM is just 16 bytes
of Internal RAM located between 20h and 2Fh.
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8051 Architecture
• General Purpose RAM: 30h to 7Fh. (80 Bytes)
• Even if 80 bytes of Internal RAM memory are available for general-purpose data
storage, user should take care while using the memory location from 00 -2Fh since
these locations are also the default register space, stack space, and bit addressable
space.
• It is a good practice to use general purpose memory from 30 – 7Fh.
• The general purpose RAM can be accessed using direct or indirect addressing
modes.
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8051 Architecture
• Storage Registers in 8051
• We will discuss the following types of storage registers here −
• Accumulator
• R register
• B register
• Data Pointer (DPTR)
• Program Counter (PC)
• Stack Pointer (SP)
• Accumulator
• The accumulator, register A, is used for all arithmetic and logic operations.
• If the accumulator is not present, then every result of each calculation (addition,
multiplication, shift, etc.) is to be stored into the main memory.
• Access to main memory is slower than access to a register like the accumulator
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8051 Architecture
• The "B" Register
• The "B" register is very similar to the Accumulator in the sense that it may hold an
8-bit (1-byte) value.
• The "B" register is used only by two 8051 instructions: MUL AB and DIV AB.
• To quickly and easily multiply or divide A by another number, we may store the
other number in "B" and make use of these two instructions.
• Apart from using MUL and DIV instructions, the "B" register is often used as yet
another temporary storage register, much like a ninth R register
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8051 Architecture
• The "R" Registers
• The "R" registers are a set of eight registers, namely, R0, R1 to R7.
• These registers function as auxiliary or temporary storage registers in many
operations.
• Consider an example of the sum of 10 and 20. Store a variable 10 in an
accumulator and another variable 20 in, say, register R4.
• To process the addition operation, execute the following command −ADD A,R4
• After executing this instruction, the accumulator will contain the value 30.
• Thus "R" registers are very important auxiliary or helper registers.
• The "R" registers are meant for temporarily storage of values
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8051 Architecture
• The Data Pointer
• The Data Pointer (DPTR) is the 8051’s only user-accessible
• DPTR is meant for pointing to data.
• It is used by the 8051 to access external memory using the address indicated by
DPTR.
• The DPTR register is made up of two 8-bit registers, named DPH and DPL.
• These are used to furnish memory addresses for internal and external code
access and external data access.
• The DPTR is under the control of program instructions and can be specified by its
16-bit name, DPTR, or by each individual byte name, DPH and DPL.
• DPTR does not have a single internal address; DPH and DPL are each assigned an
address.
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8051 Architecture
• The Program Counter
• The Program Counter (PC) is a 2-byte address which tells the 8051 where the next
instruction to execute can be found in the memory.
• PC starts at 0000h when the 8051 initializes and is incremented every time after an
instruction is executed.
• PC is not always incremented by 1.
• Some instructions may require 2 or 3 bytes; in such cases, the PC will be
incremented by 2 or 3.
• Branch, jump, and interrupt operations load the Program Counter with an address
other than the next sequential location.
• The PC is the only register that does not have an internal address
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8051 Architecture
• The Stack and the Stack Pointer
• The stack refers to an area of internal RAM that is used in conjunction with
certain opcodes to store and retrieve data quickly.
• The 8-bit Stack Pointer (SP) register is used by the 8051 to hold an internal RAM
address that is called the top of the stack.
• The address held in the SP register is the location in internal RAM where the last
byte of data was stored by a stack operation.
• When data is to be placed on the stack, the SP increments before storing data on
the stack so that the stack grows up as data is stored.
• As data is retrieved from the stack, the byte is read from the stack, and then the SP
decrements to point to the next available byte of stored data.
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8051 Architecture
• Operation of the stack and the SP is shown in Figure below
• The SP is set to 07h when the 8051 is reset and can be changed to any internal
RAM address by the programmer, using a data move command
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8051 Architecture
• The stack is limited in height to the size of the internal RAM.
• The stack has the potential (if the programmer is not careful to limit its growth) to
overwrite valuable data in the register banks, bit-addressable RAM, and scratch-
pad RAM areas.
• The programmer is responsible for making sure the stack does not grow beyond
predefined bounds
• The stack is normally placed high in internal RAM, by an appropriate choice of
the number placed in the SP register, to avoid conflict with the register, bit, and
scratch-pad internal RAM areas.
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8051 Architecture
• ROM Space in 8051
• Some family members of 8051 have 4K bytes of on-chip ROM (e.g. 8751,
AT8951); some have 8K ROM like AT89C52, and there are some family members
with 32K bytes and 64K bytes of on-chip ROM such as Dallas Semiconductor.
• The point to remember is that no member of the 8051 family can access more than
64K bytes of opcode since the program counter in 8051 is a 16-bit register (0000
to FFFF address).
• The first location of the program ROM inside the 8051 has the address of 0000H,
whereas the last location can be different depending on the size of the ROM on the
chip.
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8051 Architecture
• 8051 Flag Bits and PSW Register
• Flags are 1-bit registers provided to store the results of certain program
instructions.
• Other instructions can test the condition of the flags and make decisions based on
the flag states.
• To use the flags conveniently, they are grouped inside the program status word
(PSW) and the power control (PCON) registers.
• The 8051 has four math flags that respond to the outcomes of math operations
and three general-purpose user flags that can be set to 1 or cleared to 0 by the
programmer as desired.
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8051 Architecture
• The math flags include Carry (C), Auxiliary Carry (AC), Overflow (OV), and
Parity (P).
• User flags are named F0, GF0, and GF1; they are general-purpose flags that may
be used by the programmer to record some event in the program.
• Note that all of the flags can be set and cleared by the programmer at will.
• The math flags, however, are also affected by math operations
• The program status word is shown in Figure below:
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CY CA F0 RS1 RS0 OV - P

8051 Architecture
• Bit Symbol Function
• 7 CY Carry flag; used in arithmetic, jump, rotate, and Boolean instructions
• 6 AC Auxiliary Carry flag: used for BCD arithmetic
• 5 F0 User flag 0
• 4 RS1 Register bank select bit 1
• 3 RS0 Register bank select bit 0
• 2 OV Overflow flag; used in arithmetic instructions
• 1 - Reserved for future use
• 0 P Parity flag: shows parity of register A: 1 = Odd Parity
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8051 Architecture
• Special Function Registers
• The 8051 operations that do not use the internal 128-byte RAM are done by a
group of specific internal registers, which are called a Special-Function registers
• These may be addressed using addresses from 80h to FFh.
• Some SFRs (marked with an asterisk*) are also bit addressable, as is the case for
the bit area of RAM.
• This feature allows the programmer to change only what needs to be altered,
leaving the remaining bits in that SFR unchanged.
• Note that all of the addresses from 80h to FFh are used for SFRs,
• Attempting to use an address that is not defined, or empty, results in unpredictable results
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8051 Architecture
• The SFR addresses are shown in the upper right corner of each block.
• The SFR names and equivalent internal RAM addresses are given in Table
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8051 Architecture
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8051 Architecture
• SFRs are named in certain opcodes by their functional names, such as A or THO,
and are referenced by other opcodes by their addresses (E.g.: 0E0h or 8Ch)
• The address used in the program must start with a number; thus address E0h for
the A SFR begins with 0.
• If this convention is missed, result will be an assembler error when the program is
assembled.
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8051 Architecture
• Internal ROM
• The 8051 is organized so that data memory and program code memory can be
in two different physical memory entities.
• Each has the same address ranges.
• We have already discussed the structure of the internal RAM
• A corresponding block of internal program code, contained in an internal ROM,
occupies code address space 0000h to 0FFFh.
• The PC is ordinarily used to address program code bytes from addresses 0000h to
FFFFh.
• Program addresses higher than 0FFFh, which exceed the internal ROM capacity,
will cause the 8051 to automatically fetch code bytes from external program
memory.
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8051 Architecture
• Code bytes can also be fetched exclusively from an external memory, addresses
0000h to FFFFh, by connecting the external access pin (EA pin 31) to ground.
• The PC does not care where the code is
• The circuit designer decides whether the code is found totally in internal ROM,
totally in external ROM, or in a combination of internal and external ROM.
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8051 Architecture
• Input /Output Pins, Ports, and Circuits
• Major feature of a microcontroller is the flexibility built into the input/ output
(I/O) circuits that connect the 8051 to the outside world.
• W.k.t. microprocessor designs must add additional chips to interface with external
circuitry
• This ability is built into the microcontroller.
• To be commercially viable, the 8051 had to incorporate as many functions as were
technically and economically feasible.
• The main constraint that limits numerous functions is the number of pins available
to the 8051 circuit designers.
• The DIP has 40 pins, and the success of the design in the marketplace was
determined by the flexibility built into the use of these pins.
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8051 Architecture
• For this reason, 24 of the pins may each be used for one of two entirely different
functions, yielding a total pin configuration of 64.
• The function a pin performs at any given instant depends,
• on what is physically connected to and, then,
• on what software commands are used to "program" the pin.
• Both of these factors are under the complete control of the 8051 programmer and
circuit designer.
• With this pin flexibility, the 8051 may be applied simply as a single component
with 1/0 only, or it may be expanded to include additional memory, parallel ports,
and serial data communication by using the alternate pin assignments.
• An alternate pin function can be achieved using the port pin circuitry shown in the
figure
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8051 Architecture
• Port 0
• Pin configuration
• Port 1
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8051 Architecture
• Port 2
• Port 3
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8051 Architecture
• Ports can be accessed directly by instructions during program execution
• I/O ports are memory mapped, they are treated as memory locations
• All ports are bit addressable
• Each PIN consists of a D latch, I/P buffer and O/P driver
• SFRs for each port is made of 8-latches
• Accessed by SFRs address or name of that port
• The four 8-bit I/O ports P0, P1, P2 and P3 each uses 8 pins
• All the ports upon RESET are configured as output, ready to be used as output
ports
• When the first 0 is written to a port, it becomes an output
• To reconfigure it as an input, a 1 must be sent to the port
• To use any of these ports as an input port, it must be programmed
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8051 Architecture
• Memory Address Decoding
• The CPU provides the address of the data desired, but it is the job of the decoding
circuitry to locate the selected memory block
• Memory chips have one or more pins called CS (chip select), which must be
activated for the memory’s contents to be accessed.
• Sometimes the chip select is also referred to as chip enable (CE)
• In connecting a memory chip to the CPU, the following points need to be noted
• The data bus of the CPU is connected directly to the data pins of the memory chip
• Control signals RD (read) and WR (memory write) from the CPU are connected to
the OE (output enable) and WE (write enable) pins of the memory chip
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8051 Architecture
• In the case of the address buses, while the lower bits of the address from the CPU
go directly to the memory chip address pins, the upper ones are used to activate the
CS pin of the memory chip.
• Normally memories are divided into blocks and the output of the decoder selects a
given memory block
• Using simple logic gates
• Using the 74LS138
• Using programmable logics
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8051 Architecture
• Simple Logic Gate Address Decoder
• The simplest way of decoding circuitry is the use of NAND or other gates.
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8051 Architecture
• Using 74LS138 3-8 Decoder
• Most widely used address decoders
• The 3 inputs A, B, and C generate 8 active-low outputs Y0 – Y7
• Each Y output is connected to CS of a memory chip, allowing control of 8
memory blocks by a single 74LS138
• In the 74LS138, A, B, and C inputs select which output is activated,
• There are three additional inputs, G2A, G2B, and G1
• G2A and G2B are both active low, and G1 is active high
• If any one of the inputs G1, G2A, or G2B is not connected to an address signal,
they must be activated permanently either by VCC or ground, depending on the
activation level
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8051 Architecture
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8051 Architecture
• 74LS138 as Decoder
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8051 Architecture
• Looking at the above figure, find the address range for the Y4 line
• The address range for Y4 is calculated as follows.
• A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
• 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
• 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
• A15 must be 0 for the decoder to be activated.
• Y4 will be selected when A14 A13 A12 = 100 (4 in binary).
• The remaining A11-A0 will be 0 for the lowest address and 1 for the highest
address.
• Thus the range for Y4 is 4000H to 4FFFH
• Similarly try for Y7 and Y2
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8051 Architecture
• External ROM (program memory) Interfacing
• Port 0 is used as multiplexed data & address lines.
• It gives lower order (A7-A0) 8 bit address in initial cycle & used as data bus in the
subsequent cycles.
• 8 bit address is latched using external latch & ALE signal from 8051
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8051 Architecture
• Port 2 provides higher order (A15-A8) 8 bit address.
• PSEN' is used to activate the output enable signal of external ROM/EPROM.
• External RAM (data memory) Interfacing
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8051 Architecture
• Port 0 is used as multiplexed data & address lines.
• Address lines are decoded using external latch & ALE signal from 8051 to provide
lower order (A7-A0) address lines.
• Port 2 gives higher order address lines.
• RD' & WR' signals from 8051 selects the memory read & memory write
operations respectively.
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8051 Architecture
• E.g.: Design a controller system using 8051.Interface the external RAM of size
16k x 8.
• Given, Memory size: 16k  2n=16k (n address lines), n=14 needed (A0 to A13)
• Let us connect A14 and A15 to CS pin of external RAM through OR gate.
• When A14 and A15 both are low (logic ‘0’), external data memory (RAM) is
selected.
• Address Decoding (Memory Map) for 16k x 8 RAM
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8051 Architecture
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8051 Architecture
• Design and draw the interfacing diagram to interface 8051 to the external ROM of
size 4k x 8.
• Memory size: 4k => 2n=212=4k, thus we require 12 address lines, (A0 to A11)
• Remaining lines A12, A13, A14, A15 & PSEN` are connected though OR gate to
CS & RD of external ROM.
• When A12 to A15 are low (logic ‘0’), only then external ROM is selected.
• Address Decoding (Memory Map) for 4k x 8 RAM
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8051 Architecture
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8051 Architecture
• How to interfacing of 16KByte of RAM and 32KByte of EPROM to 8051
• Number of address lines required for 16 Kbyte memory ?
• 14 lines
• Number of address lines required for 32Kbytes of memory ?
• 15 lines
• The interfacing of 16KByte of RAM and 32KByte of EPROM to 8051 is shown in
the following figure
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8051 Architecture
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8051 Architecture
• The lower order address and data bus are multiplexed.
• De-multiplexing is done by the latch.
• Initially the address will appear in the bus and this is latched at the output of latch
using ALE signal.
• The output of the latch is directly connected to the lower byte address lines of the
memory.
• Later data will be available in this bus.
• Still the latch output is address itself.
• The higher byte of address bus is directly connected to the memory.
• The number of lines connected depends on the memory size.
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8051 Architecture
• The RD` and WR` (both active low) signals are connected to RAM for reading
and writing the data.
• PSEN` (Program Store Enable) of microcontroller is connected to the OE` output
enable of the ROM to read the data from the memory.
• EA` (active low) pin is always grounded if we use only external memory.
• Otherwise, once the program size exceeds internal memory the microcontroller
will automatically switch to external memory.
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8051 Architecture
• Connecting External Memory: (Example from the text book)
• Interfacing an 8031 with EPROM of 16K and 8K of static RAM
• Address lines needed
• 16K ROM – 14 lines
• 8K RAM – 12 lines
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8051 Architecture
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8051 Architecture
• Pin details continued…
• P3.2 and P3.3 (INT0′, INT1′ ): 12th and 13th pins
• These are for External Hardware Interrupt 0 and Interrupt 1 respectively.
• When this interrupt is activated(i.e. when it is low), 8051 gets interrupted in
whatever it is doing and jumps to the vector value of the interrupt (0003H for
INT0 and 0013H for INT1) and starts performing Interrupt Service Routine (ISR)
from that vector location.
• P3.4 and P3.5 (T0 and T1): 14th and 15th pins
• These are for Timer 0 and Timer 1 external input.
• They can be connected with 16 bit timer/counter.
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8051 Architecture
• Pin 29 (PSEN) –Program Store Enable.
• It is output, active-low pin, used to read external memory.
• In 8031 based system where external ROM holds the program code, this pin is
connected to the OE pin of the ROM.
• Pin 30 (ALE/ PROG) – Address Latch Enable.
• It is input, active-high pin.
• This pin is used to distinguish between memory chips when multiple memory
chips are used.
• It is also used to de-multiplex the multiplexed address and data signals available at
port 0.
• During flash programming i.e. Programming of EPROM, this pin acts as program
pulse input (PROG)
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8051 Architecture
• Pin 31 (EA/ VPP) –External Access
• Input pin used to enable/disable external memory interfacing.
• In 8051, EA is connected to VCC as it comes with on-chip ROM to store programs.
• For other family members such as 8031 and 8032 in which there is no on-chip
ROM, the EA pin is connected to the GND.
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