SPICE MODEL of uPC4071C in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.

1. Device Modeling Report
COMPONENTS: OPERATIONAL AMPLIFIER
PART NUMBER: uPC4071C
MANUFACTURER: NEC ELECTRONICS
REMARK TYPE: (OPAMP)
Bee Technologies Inc.
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

2. Spice Model
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

3. Output Voltage Swing
Simulation result
20V
0V
-20V
-500mV -250mV 0V 250mV 500mV
V(Vout)
V_V1
Evaluation circuit
U1
OF FSET NU LL NC
Ii - V+ Vo ut 10 k
+
In OU T
Rl oa d
V- OF FSET NU LL V+
V1 UP C40 71 C
0V dc V- 15 Vd c
-15 Vdc
0
Comparison table
Output Voltage Swing Measurement Simulation %Error
+Vout(V) 13.500 13.499 -0.007
-Vout(V) -13.500 -13.499 -0.007
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

4. Input Offset Voltage
Simulation result
20V
0V
-20V
-5mV 0V 5mV 10mV
V(Vout)
V_Vin
Evaluation circuit
U1
OF FSET NU LL NC
Ii - V+ Vo ut
2k
+
In OU T
Rl oa d
V- OF FSET NU LL
UP C40 71 C
VO FF = 0 V-
VA MPL = 0 V+
Vi FREQ = 0
AC = 0 -15 Vdc
DC = 0 15 Vd c
VO FF = 0
VA MPL = 0
Vi n FREQ = 0
AC = 0
DC = 0
0
Comparison table
Measurement Simulation %Error
Vos(mV)
3.000 2.992 -0.260
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

5. Slew Rate
Simulation result
20V
0V
-20V
0s 50us 100us 150us 200us
V(Vout)
Time
Evaluation circuit
U1
OF FSET NU LL NC
Ii - V+ Vo ut
+
In OU T
V- OF FSET NU LL
Vi
UP C40 71 C
V1 = -1 3.5 Vi n
VO FF = 0 V2 = 13.5 V+
VA MPL = 0 TD = 0 .1m
FREQ = 0 TR = 1 0n V-
AC = 0 TF = 10n 15 Vd c
DC = 0 PW = 1 m -15 Vdc
PE R = 2m
0
Comparison table
Slew Measurement Simulation %Error
Rate(v/us) 13.000 12.820 -1.385
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

6. Input current Ib, Ibos
Simulation result
-20pA
-25pA
-30pA
-35pA
-40pA
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms
I(Vi) I(Vin)
Time
Evaluation circuit
U1
OF FSET NU LL NC
Ii - V+ Vo ut
+
In OU T
Vi n V- OF FSET NU LL
VO FF = 0
UP C40 71 C
VA MPL = 0
FREQ = 0 V-
Vi AC = 0 V+
VO FF = 0 DC = 0 -15 Vdc
VA MPL = 0
FREQ = 0 15 Vd c
AC = 0 V1
DC = 0
2.9 92m
0
Comparison table
Measurement Simulation %Error
Ib(pA) 30.000 30.065 0.217
Ibos(pA) 5.000 5.094 1.880
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

7. Open Loop Voltage Gain vs. Frequency , Av-dc, f-0dB
Simulation result
120
80
40
0
1.0Hz 100Hz 10KHz 1.0MHz 100MHz
DB(V(Vout)/V(Vin:+))
Frequency
Evaluation circuit
U1
OF FSET NU LL NC
Ii - V+ Vo ut RL
+
In OU T
2k
V- OF FSET NU LL
Vi UP C40 71 C
VO FF = 0
VA MPL = 0 Vi n V+
FREQ = 0 VO FF = 0 V-
AC = 0 VA MPL = 0
DC = 0 FREQ = 0 15 Vd c
AC = 1 m -15 Vdc
DC = 2 .992 m
0
Comparison table
Measurement Simulation %Error
f-0dB(MHz) 3.000 3.020 0.667
Av-dc(dB) 106.000 107.750 1.651
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

8. Common-Mode Rejection Voltage gain
Simulation result
10V
0V
-10V
0s 1.0s 2.0s 3.0s 4.0s
V(Vout)
Time
Evaluation circuit
U1
OF FSET NU LL NC
Ii - V+ Vo ut
+
In OU T
V1
-2.99 2m V- OF FSET NU LL
UP C40 71 C
V+
V-
15 Vd c
V
VO FF = 0 -15 Vdc
VA MPL = 0 .5
FREQ = 1
AC = 0
DC = 0
0
Common Mode Reject Ratio=20*LOG(244061.9068/9.968) = 87.7778 dB
CMRR Measurement Simulation %Error
(dB) 86.000 87.777 2.066
All Rights Reserved Copyright (c) Bee Technologies Inc. 2008