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1. HIGH SPEED HYBRID LOGIC FULL ADDER USING HIGH
PERFORMANCE 10T XOR-XNOR CELL
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2. Contents:
• ABSTRACT
• INTRODUCTION
• EXISTING METHOD
• PROPOSED METHOD DIAGRAM
• TRUTH TABLE
• APPARATUS
• ADVANTAGES
• APPLICATIONS

3. Abstract:
• Hybrid logic style is widely used to implement full adder (FA)
circuits.
• It performance of hybrid FA in terms of delay, power, and driving
capability is largely dependent on the performance of XOR–XNOR
circuit.
• The high speed low power 10T XOR-XNOR is proposed ,which
provides full swing output.
• The performance of the proposed circuit is measured by using
CMOS technology.
• The proposed circuit reduces the power delay product (PDP) at least
by 7.5%.

4. Introduction:
ADDER:
 Addition is the basic arithmetic operation
 Adder is a key element for VLSI systems like
• ALU’s
• Microprocessors
• Parity checkers
FULL ADDER:
 Combing of two half adders is known as full adder.
 Which adds three inputs at a time and produces two outputs Like
sum and carry.

5. • To realize a full adder circuit, several static CMOS logic styles have
been presented .
• These logic styles can be broadly classified into two categories:
classical design style and hybrid design style.
 CLASSICAL DESIGN:
In this style the FA is designed in a single module using CMOS
transistors.
 HYBRID DESIGN:
In hybrid design style, FA structure is divided into three modules

6. Hybrid Model:

7. Existing Method:

8. Proposed Method:

9. Circuit Diagram:

10. Full Adder Truth Table:

11. Apparatus:
• CADENCE 45GPDK TECHNOLOGY
• CADENCE VIRTUOSO
• PMOS :L=45nm W=180nm
• NMOS L=45nm W=90nm
• VDC=1.8V For biasing propose

12. Advantages:
 Number of transistors reduced.
 Delay and power consumption reduced.
 Speed increased.
 Complexity of the circuit is reduced.

13. Applications:
• Multipliers
• ALU
• DSP

14. THANKYOU