This article discuss various ARM instruction sets including ARM, Thumb, Thumb-2 and latest nomenclature T32, A32, A64.  It also discuss various execution states and logic used.

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ARM
Instruction Set Classification

2. ARM Instruction Set
●
Memory vs speed. Caused further addition of Thumb to original 32-bit ARM instruction
●
introduction of Thumb instruction in ARMv4T ISA based ARM7T family core ARM7TDMI . Thumb for better
code density, less power consumption due to 16-bit system bus
●
Thumb-2 was introduced in ARMv6T2 ISA based ARM11 family core ARM1156T2-S .
–
Thumb-2 has both 16 and 32-bit encoded instructions. Helps for better code density and
performance
●
ARMv8A
–
A32 is alias of ARM instruction
–
T32 is alias of Thumb instruction
●
when both a 16-bit encoding and a 32-bit encoding are available, the 16-bit encoding is
selected, to optimize code density.
A64 for accessing 64 bit registers and memory pointers
●
Execution States
–
ARM
–
Thumb
–
AARCH32 was introduced in ARMv8A ISA based Cortex-A family core Cortex-A32
●
Supports A32 and T32 instruction sets
–
AARCH64 was introduced in ARMv8A ISA based Cortex-A family core Cortex-A35
●
Supports A64 instruction set

3. ARM ISA Simplified
●
ARMv7M or ARMv7R based devices are based on Thumb,Thumb-2
●
Need to divide whole ARM family based on Pre and post ARMv8A
●
As per latest naming convention
ISA ARMv7A or older ARMv8A-32 ARMv8-A-64
Instruction
Encoding
A32 ,T32
(old ARM,Thumb2)
A32,T32 A64
Instruction
size(Bits)
Fixed 32 ,16/32 bit Fixed 32 , 16/32 bit Fixed 32 bit
Execution State ARM, Thumb AARCH32 AARCH64
Status Register xPSR[T] SPSR_EL1[M[4]]=1
SPSR_EL1[T]=1 for
T32
SPSR_EL1[M[4]
]=0
T=0 ARM
=1 Thumb
SPSR_EL1[T]=0 for
A32

4. ARMv8A
A picture is worth a thousand words

5. Thumb Instruction 16/32-bit Mechanism
●
How devices with only Thumb State differentiate between 16 and
32-bit encoding ?

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