in this ppt i gave the information of phase lag design by using rout locus. and i gave solved example.

1. Control System Engineering (2150909)
Active Learning Assignment
on
Phase lag design using Rout Locus
Prepared By:
Patel RajalKumar H.
(160123109013)
Guided By :
Prof. Naveen Sharma
Electrical Department
Batch-B3

2. Contents
• Lag Comparator with rout locus
• Example

3. Lag compensators: design with root locus
 The goal of lag compensators, when you’re designing them
with root locus:
 Reduce the steady state error significantly
 With a marginal impact on (the relevant part of) the root locus
 While maintaining the freedom to adjust your position on that
root locus!
 Let’s show this graphically:
 Let’s say we have a system 𝑃𝑃 𝑃𝑃 with the
following root locus:
 The orange poles indicate the desired
dominant pole locations (which we’ll call 𝑃
and 𝑃), and as you can see they are on the
root locus, for a gain value we’ll call 𝑃𝑃

6. • It is quite readily visible from the following root locus plot
that the condition for a small impact on (a region of) the root
locus by a lag compensator is that its pole and zero lie much
closer to each other than to that region:
• The effect of this pole and zero
on the angle at 𝑞𝑞 is only the
angle between the dotted and the
dashed red line.
• The effect of this pole and zero
on the magnitude at 𝑞 is only
the ratio between the length of
the dashed and the dotted red

9. Example

11. • The closed loop pole and zero locations of KP(𝑠) and 𝑠P(𝑠) 𝑠(s) are shown
here below:
• As you can see there is hardly any distinction (that’s why they weren’t plotted
on the same graph, because they almost entirely overlap).
• The reason is that the factor 50 we use in determining 𝑠𝑠is very large; this
gives very small pole-zero values; this also means the steady-state value is very
slowly approached, so sometimes you’ll want a smaller factor than 50 and as
you can see in this example, there is quite some margin left.