This document describes an Ethernet sniffer project implemented on an FPGA board without software. The sniffer is able to monitor its own subnet and output messages containing the destination and source MAC addresses, length, and data when it detects an Ethernet broadcast message from another device. It uses a dual port RAM, AXI interface, and state machines to transfer data between the PHY, MII to RMII core, Ethernet MAC, and UART for output.
2. Project definition
• Network Ethernet sniffer based on FPGA
board Nexys 4.
• The device has the ability to monitor the
network, to gain information about the
network and the devices by dynamically
changing the Mac address. The project is
implemented HW VHDL language without
software.
3. Basic configurations and PR
• The UE should be able to monitor own sub
network.
• Once reception Ethernet broadcast message
from another device, UE should recognize
start of frame and notifies the user by output
message.
• Output message should consist of destination
and source MAC, length of message and data.
6. IP MII to RMII v2.0
The core accept the 16 signal MII interface and provides a six or seven signal
interface to a RMII compliant PHY. Additionally, a fixed 50 MHz reference clock
synchronizes the MII to RMII core with both interfaces.
8. AXI Ethernet Lite MAC v3.0
Parameterized AXI4 slave interface based on the AXI4 or AXI4-Lite specification
for transmit and receive data dual port memory access. Include independent
internal 2KByte TX and RX dual port memory for holding data for one packet.
9. Advanced Extensible Interface 4 Lite
(AXI4-Lite)
Read procedure
The most widespread AMBA interface. Connectivity up to 100's of Masters and
Slaves in complex SoC's