This document presents the design of an integrated synthesizer enclosed in a 16-pin QFN package for the DVB-H standard. The synthesizer includes a voltage-controlled oscillator, dividers, phase frequency detector, and charge pump. Measurements and post-layout simulations are shown for the individual blocks and entire synthesizer. The simulations account for the influence of bond wires, pads, solder dots, and packaging, showing results both before and after packaging. The total phase noise is -107 dBc/Hz at 100 kHz offset, suitable for the DVB-H standard.

1. A Packaged Integrated Synthesizer for DVB-H
D. Ramos-Valido1, R. Pulido1, Sunil L. Khemchandani1, E. Ortega-García1,
A. Juanicorena2 and J. del Pino1.
1 Institute for Applied Microelectronics, Departamento de Ingeniería Electrónica y Automática, Universidad de Las Palmas de Gran Canaria, Spain.
2 CEIT and Tecnun (University of Navarra), Electronics and Communications dept, Spain.
Published in
XXVI Design of Circuits and Integrated Systems Conference.
Albufeira, Portugal, 2011.
Abstract
This paper presents a BiCMOS integrated synthesizer enclosed in a 16-pin QFN package for DVB-H standard. A
detailed description of the synthesizer, including the VCO, the dividers, the phase frequency detector and the
charge pump is carried out. Measurement of individual blocks and post layouts simulations of the entire
synthesizer are shown. The influence of the bond-wires, ESD pads, solder dots and package in the synthesizer
response is studied, showing simulations before and after the package. The total phase noise and the contribution
of the VCO phase noise in the synthesizer is shown, obtaining a total phase noise of -107 dBc/Hz at 100 kHz offset,
suitable for DVB-H standard.
Circuits Design
Measurements & Simulations
Figure 1 Synthesizer for DVB-H.
Figure 11 Synthesizer in a QFN16 package.
0
(a) (b)
Figure 2 (a) Phase frequency detector and Figure 3 Passive three-pole
Figure 9 Inphase and quadrature output
loop filter. Figure 8 Fast divider output spectrum.
(b) charge pump simplified schematic. signals for the fast divider.
Figure 4 VCO simplified schematic. Figure 7 CML fast divider and shifter.
Figure 12 Synthesizer transient response. Figure 14 Synthesizer phase noise
response.
Conclusions
This paper shows the design procedure of an integrated (a)
synthesizer in a 16-pin QFN package for DVB-H standard.
The synthesizer includes VCO, 0-90º phase shifter, fast
dividers, PFD, charge pump, loop filter and programmable
dividers. A description of each element is done, including (b)
the design and measure of a single core fully integrated Figure 12 Synthesizer transient response. Figure 16 VTUNE voltage post-layout
VCO with on chip tank. Bond-wires, ESD pads, solder dots simulatioins without (a) and with (b)
package effect.
and package were taken into account in the synthesizer
response, showing simulations after and before the
packaging. Simulations have been done to test the
synthesizer behavior, showing the VCO phase noise Acknowledgement
contribution to the synthesizer. The blocks are implemented This work is partially supported by the Spanish Ministry of Science and
in an AMS 0.35 µm BiCMOS process and the power supply Innovation (TEC2008-06881-C03-01) and the Spanish Ministry of Industry,
is 3.3 V. Tourism and Trade (TSI-020400-2010-55).
INSTITUTO UNIVERSITARIO DE MICROELECTRÓNICA APLICADA (IUMA)
UNIVERSIDAD DE LAS PALMAS DE GRAN CANARIA (ULPGC)