Unit_I.pptx

UNIT- I
INTRODUCTION TO PIC
MICROCONTROLLERS
MZCET/EEE/EE6008/1 1

1.1 Introduction to PIC Microcontroller
1.2 PIC 16C6x and PIC16C7x Architecture
1.3 PIC16cxx–-Pipelining
1.4 Program Memory considerations
1.5 Register File Structure
1.6 Instruction Set
1.7 Addressing modes
1.8 Simple Operations.

Introduction
1.1

PIC -Peripheral Interface Controller
Brain child of Microchip Technology, USA .
single chip micro-controllers
Industrial automation and embedded applications
Low cost
Wide availability
Large user base
Extensive collection of application notes
Availability of low cost or free development tool
Serial programming capability
1.1
Introduction

1.1
Introduction
Classification of PIC microcontroller
Low-end architectures Mid-range devices
• 12-bit wide
instructions with
basic I/O functions.
• Upgradation of low-end
architectures with more
number of peripherals,
more number of registers.
• An enhancement of Analog
to Digital converter
capability

1.1
Introduction
Classification of PIC microcontroller
Low-end architectures Mid-range devices
• 12C5XX
• 16C5X
• 16C505
• 16C6X
• 16C7X
• 16F87X
• limited program
memory
• Applicable only in
simple interface
functions.
• More data/program
memory
• Applicable in Medium range
projects.

Princeton Architecture
1.1
Introduction

1.1
Harvard Architecture
Introduction

• PIC16C61 • PIC16C64A
• PIC16C62 • PIC16CR64
• PIC16C62A • PIC16C65
• PIC16CR62 • PIC16C65A
• PIC16C63 • PIC16CR65
• PIC16CR63 • PIC16C66
• PIC16C64 • PIC16C67
1.2
Series of PIC16C6X

High performance RISC CPU
Only 35 single word instructions to learn
All single cycle instructions except for program
branches which are two-cycle
Operating speed:
DC - 20 MHz clock input DC - 200 ns instruction cycle
Interrupt capability
Eight level deep hardware stack
1.2
Core features of PIC16C6X

Direct, indirect, and relative addressing modes
Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up Timer
(OST)
Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Programmable code-protection
Power saving SLEEP mode
Selectable oscillator options
1.2
Core features of PIC16C6X

Timer0: 8-bit timer/counter with 8-bit prescaler
Timer1: 16-bit timer/counter with prescaler, can be
incremented during sleep via external crystal/clock
Timer2: 8-bit timer/counter with 8-bit period register,
prescaler and postscaler
Capture/Compare/PWM (CCP) module(s)
1.2
Peripheral features of PIC16C6X

Capture is 16-bit, max resolution is 12.5 ns, Compare is
16-bit, max resolution is 200 ns, PWM max resolution is
10-bit.
Synchronous Serial Port (SSP) with SPI and I2C
Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
Parallel Slave Port (PSP) 8-bits wide, with external RD,
WR and CS controls
Brown-out detection circuitry for Brown-out Reset
(BOR)
1.2
Peripheral features of PIC16C6X

1.2
Pin Diagram of PIC16C6X

Pin Name Pin Type Description
OSC1/CLKIN I Oscillator crystal input/external clock source input.
OSC2/CLKOUT
O
Oscillator crystal output. Connects to crystal or
resonator in crystal oscillator mode.
In RC mode, the pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the
instruction cycle rate.
MCLR/VPP I/P Master clear reset input or programming voltage
input. This pin is an active low reset to the device.
RA0
RA1
RA2
RA3
RA4/T0CKI
I/O
I/O
I/O
I/O
I/O
PORTA is a bi-directional I/O port.
RA4 can also be the clock input to the Timer0 timer
/counter.
Output is open drain type.
1.2
Pin out Description of PIC16C61

RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PORTB is a bi-directional I/O port.
PORTB can be software programmed for internal
weak pull-up on all inputs.
RB0 can also be the external interrupt pin.
Interrupt on change pin.
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
VSS P Ground reference for logic and I/O pins.
VDD P Positive supply for logic and I/O pins.
1.2
Pinout Description of PIC16C61

1.2
PIC16C62

1.2

1.2
PIC16C63
PIC16CR63
PIC16C66

OSC2/CLKOUT
O
RA0
RA1
RA2
RA3
RA4/T0CKI
RA5/SS
I/O
I/O
I/O
I/O
I/O
RA4 can also be the clock input to the Timer0
timer/counter. Output is open drain type.
RA5 can also be the slave select for the synchronous
serial port.
1.2
MZCET/EEE/EE6008/1
20
Pinout Description of
PIC16C62/62A/R62/63/R63/66

1.2
MZCET/EEE/EE6008/1
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PIC16C62/62A/R62/63/R63/66
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

1.2
MZCET/EEE/EE6008/1
22
PIC16C62/62A/R62/63/R63/66
Pin Name Pin
Type
Description
RC0/T1OSO(1)/T1CKI
I/O PORTC is a bi-directional I/O port.
RC0 can also be the Timer1 oscillator output(1) or
Timer1 clock input.
RC1/T1OSI(1)/CCP2(2) I/O RC1 can also be the Timer1 oscillator input(1) or
Capture2 input/Compare2 output/PWM2
output(2).
RC2/CCP1 I/O RC2 can also be the Capture1 input/Compare1
output/PWM1 output.
RC3/SCK/SCL I/O RC3 can also be the synchronous serial clock
input/output for both SPI and I2C modes
RC4/SDI/SDA I/O RC4 can also be the SPI Data In (SPI mode) or data
I/O (I2C mode).
RC5/SDO I/O RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK(2) I/O RC6 can also be the USART Asynchronous
Transmit(2) or Synchronous Clock(2).
RC7/RX/DT(2) I/O RC7 can also be the USART Asynchronous
Receive(2) or Synchronous Data(2).

1.2

1.2
PIC16C65A
PIC16CR65
PIC16C67

OSC2/CLKOUT
O
RA0
RA1
RA2
RA3
RA4/T0CKI
RA5/SS
I/O
I/O
I/O
I/O
I/O
serial port.
1.2
MZCET/EEE/EE6008/1
26
PIC16C64/64A/65/65A/67

1.2
MZCET/EEE/EE6008/1
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RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PIC16C64/64A/65/65A/67

1.2
MZCET/EEE/EE6008/1
28
Pin Name Pin
Type
Description
RC0/T1OSO(1)/T1CKI
Timer1 clock input.
output(2).
output/
PWM1 output.
I/O (I2C mode).
PIC16C64/64A/65/65A/67

1.2
MZCET/EEE/EE6008/1
29
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PORTD can be a bi-directional I/O port or parallel slave port
for interfacing to a microprocessor bus.
RE0/RD
RE1/WR
RE2/CS
I/O
I/O
I/O
PORTE is a bi-directional I/O port.
RE0 can also be read control for the parallel slave port.
RE1 can also be write control for the parallel slave port.
RE2 can also be select control for the parallel slave port.
NC - These pins are not internally connected. These pins should
be left unconnected.
PIC16C64/64A/65/65A/67

PIC16C6X Device varieties
1.2
C, as in PIC16C64- EPROM type memory and
operate over the standard
voltage range
LC, as in PIC16LC64 EPROM type memory and
operate over an extended
voltage range
CR, as in PIC16CR64 ROM program memory and
operate over the standard
voltage range
LCR, as in
PIC16LCR64
ROM program memory and
operate over an extended
voltage range

• The UV erasable version, offered in CERDIP package is optimal
for prototype development and pilot programs.
• This version can be erased and reprogrammed to any of the
oscillator modes.
• Flexibility for frequent code updates and small volume
applications.
• Packaged in plastic packages, permit the user to program
them once.
• In addition to the program memory, the configuration bits
must also be programmed.
1.2
PIC16C6X Device varieties
UV Erasable Devices
One-Time-Programmable (OTP) Devices

• Available for users who choose not to program a medium to
high quantity of units
• whose code patterns have stabilized.
• Identical to the OTP devices but with all EPROM locations and
configuration options already programmed by the factory.
1.2
PIC16C6X DEVICE VARIETIES
Quick-Turnaround-Production (QTP) Devices
• Masked ROM versions of several of the highest volume parts
• Low cost option for high volume, mature products.
Read Only Memory (ROM) Devices

• A unique programming service where a few user-defined
locations in each device are programmed with different serial
numbers.
• The serial numbers may be random, pseudo-random, or
sequential.
• Serial programming allows each device to have a unique number
which can serve as an entry-code, password, or ID number.
• ROM devices do not allow serialization information in the
program memory space.
• The user may have this information programmed in the data
memory space.
1.2
PIC16C6X DEVICE VARIETIES
Serialized Quick-Turnaround Production
(SQTPSM) Devices

Architecture of
PIC16C61
1.2

PIC16C62/62A/R62/64/64A/R64 BLOCK DIAGRAM
1.2
35
MZCET/EEE/EE6008/1

PIC16C62/62A/R62/64/64A/R64
BLOCK DIAGRAM
1.2
1: Higher order bits are from the STATUS register.
2: PORTD, PORTE and the Parallel Slave Port are not available on
the PIC16C62/62A/R62.
3: Brown-out Reset is not available on the PIC16C62/64.
4: Pin functions T1OSI and T1OSO are swapped on the
PIC16C62/64.

PIC16C63/R63/65/65A/R65 BLOCK DIAGRAM
1.2
37
MZCET/EEE/EE6008/1

PIC16C63/R63/65/65A/R65 BLOCK DIAGRAM
1.2
2: PORTD, PORTE and the Parallel Slave Port are not available
on the PIC16C63/R63.
3: Brown-out Reset is not available on the PIC16C65.

PIC16C66/67 BLOCK DIAGRAM
1.2
39
MZCET/EEE/EE6008/1

PIC16C66/67 BLOCK DIAGRAM
1.2
40
2: PORTD, PORTE and the Parallel Slave Port are
not available on the PIC16C66.
MZCET/EEE/EE6008/1

Architectural overview
• RISC microprocessors.
• Harvard architecture, in which, program and data are
accessed from separate memories using separate buses.
• This improves bandwidth over traditional von Neumann
architecture.
• Separating program and data busses further allows
instructions to be sized differently than 8-bit wide data
words.
• Instruction opcodes are 14-bits wide making it possible to
have all single word instructions.
• A 14-bit wide program memory access bus fetches a 14-
bit instruction in a single cycle.
• All instructions execute in a single cycle (200 ns @ 20
MHz) except for program branches.
1.2

• The PIC16CXX device contains an 8-bit ALU and working
register (W).
1.2
• It performs arithmetic and Boolean functions between data
in the working register and any register file.
• The ALU is 8-bits wide and capable of addition, subtraction,
shift, and logical operations.
• Arithmetic operations are two's complement in nature.
• Depending upon the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and Zero
(Z) bits in the STATUS register.
• Bits C and DC operate as a borrow and digit borrow out bit,
respectively, in subtraction.
Arithmetic and logic unit

• The W register is an 8-bit working register used for ALU
operations.
• It is not an addressable register.
• In two-operand instructions, typically one operand is the
working register (W register), the other operand is a file
register or an immediate constant.
• In single operand instructions, the operand is either the W
register or a file register.
1.2
Working register (W register)

1.2
Comparison of 16C6X series
PIC16C61 PIC16C62A PIC16CR62 PIC16C63 PIC16CR63
Clock Maximum
Frequency
of
Operation
(MHz)
20 20 20 20 20
Memory EPROM
Program
Memory
(x14 words)
1K 2K - 4K -
ROM
Program
Memory
(x14 words)
- - 2K - 4K
Data
Memory
(bytes)
36 128 128 192 192

1.2
PIC16C64A PIC16C65A PIC16C66 PIC16C67
Clock Maximum
Frequency
of Operation
(MHz)
20 20 20 20
Memory EPROM
Program
Memory
(x14 words)
2K 4K 8K 8K
ROM
Program
Memory
(x14 words)
- - - -
Data Memory
(bytes)
128 192 368 368

1.2
Peripheral
s
Timer
Module(s)
TMR0 TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Co
mpare/
PWM
Module(s)
- 1 1 2 2
Serial
Port(s)
(SPI/I2C,
USART)
- SPI/I2C SPI/I2C SPI/I2C
USART
SPI/I2C
USART
Parallel
Slave Port
- - - - -

1.2
Peripherals Timer
Module(s)
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Com
pare/
PWM
Module(s)
1 2 2 2
Serial Port(s)
(SPI/I2C,
USART)
SPI/I2C SPI/I2C
USART
SPI/I2C
USART
SPI/I2C
USART
Parallel Slave
Port
Yes Yes Yes Yes

1.2
Features Interrupt
Sources
3 7 7 10 10
I/O Pins 13 22 22 22 22
Voltage
Range
(Volts)
3.0-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
In-Circuit
Serial
Programmin
g
Yes Yes Yes Yes Yes
Brown-out
Reset
- Yes Yes Yes Yes
Packages 18-pin
DIP, SO
28-pin SDIP,
SOIC, SSOP
28-pin SDIP,
SOIC, SSOP
28-pin
SDIP,
SOIC
28-pin
SDIP,
SOIC

1.2
Features Interrupt
Sources
8 11 10 11
I/O Pins 33 33 22 33
Voltage Range
(Volts)
2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
In-Circuit
Serial
Programming
Yes Yes Yes Yes
Brown-out
Reset
Yes Yes Yes Yes
Packages 40-pin DIP;
44-pin
PLCC,
MQFP,
TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
28-pin SDIP,
SOIC, SSOP
40-pin DIP;
44-pin
PLCC,
MQFP, TQFP

PIC16C7X
PIC 16C7X
series
1.2
PIC16C72
PIC16C73
PIC16C73A
PIC16C74
PIC16C74A
PIC16C76
PIC16C77

High-performance RISC CPU
Only 35 single word instructions to learn
All single cycle instructions except for program branches which
are two cycle
Operating speed: DC - 20 MHz clock input DC - 200 ns instruction
cycle
Up to 8K x 14 words of Program Memory, up to 368 x 8 bytes of
Data Memory (RAM)
Interrupt capability
Eight level deep hardware stack
Direct, indirect, and relative addressing modes
1.2
PIC16C7X Core Features:

Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
Watchdog Timer (WDT) with its own on-chip RC oscillator for
reliable operation
Programmable code-protection
Power saving SLEEP mode
Selectable oscillator options
Low-power, high-speed CMOS EPROM technology
Fully static design
1.2
PIC16C7X Core Features:

1.2
PIC16C7X Peripheral Features:
Timer0: 8-bit timer/counter with 8-bit prescaler
Timer1: 16-bit timer/counter with prescaler, can be
incremented during sleep via external crystal/clock
Timer2: 8-bit timer/counter with 8-bit period register,
prescaler and postscaler
Capture, Compare, PWM module(s)
Capture is 16-bit, max. resolution is 12.5 ns
Compare is 16-bit, max. resolution is 200 ns
PWM max. resolution is 10-bit

8-bit multichannel analog-to-digital converter
Synchronous Serial Port (SSP) with SPI
Universal Synchronous Asynchronous Receiver Transmitter
(USART/SCI)
Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and
CS controls
Brown-out detection circuitry
1.2
PIC16C7X Peripheral Features:

1.2
PIC16C72

1.2
PIC16C73
PIC16C76

1.2
PIC16C74
PIC16C77

OSC2/CLKOUT
O
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/Vref
RA4/T0CKI
RA5/SS/AN4
I/O
I/O
I/O
I/O
I/O
Can also be analog input 0
serial port. Or analog input 4
1.2
MZCET/EEE/EE6008/1
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Pin out Description of PIC16C72/73/76

1.2
MZCET/EEE/EE6008/1
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RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

1.2
MZCET/EEE/EE6008/1
60
Pin Name Pin
Type
Description
RC0/T1OSO(1)/T1CKI
Timer1 clock input.
output(2).
output/
PWM1 output.
I/O (I2C mode).

1.2
MZCET/EEE/EE6008/1
61
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PORTD can be a bi-directional I/O port or parallel slave port
for interfacing to a microprocessor bus.
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
I/O
I/O
I/O
PORTE is a bi-directional I/O port.
RE0 can also be read control for the parallel slave port OR
analog Input 5
RE1 can also be write control for the parallel slave port. Or
Analog input 6
RE2 can also be select control for the parallel slave port or
Analog input7
NC - These pins are not internally connected. These pins should
be left unconnected.
Pinout Description of PIC16C74/77
(additional apart from 72/73/76)

PIC16C72 BLOCK DIAGRAM
1.2

PIC16C73/73A/76
BLOCK DIAGRAM
1.2

Device Program
Memory
Data Memory
(RAM)
PIC16C73 4K x 14 192 x 8
PIC16C73A 4K x 14 192 x 8
PIC16C76 8K x 14 368 x 8
PIC16C73/73A/76 BLOCK DIAGRAM
1.2
Note

PIC16C74/74A/77
BLOCK DIAGRAM
1.2

Device Program
Memory
Data Memory
(RAM)
PIC16C74 4K x 14 192 x 8
PIC16C74A 4K x 14 192 x 8
PIC16C77 8K x 14 368 x 8
PIC16C74/74A/77 BLOCK DIAGRAM
1.2
Note

RISC microprocessors.
Harvard architecture
Improves bandwidth over traditional von Neumann
architecture
Separating program and data buses allows instructions to be
sized differently than the 8-bit wide data word.
Instruction opcodes are 14-bits wide
A 14-bit wide program memory access bus fetches a 14-bit
instruction in a single cycle.
1.2

A twostage pipeline overlaps fetch and execution of instructions
All instructions (35) execute in a single cycle (200 ns @ 20 MHz)
except for program branches.
Directly or indirectly address its register files or data memory.
All special function registers, including the program counter, are
mapped in the data memory.
Orthogonal (symmetrical) instruction set.
Lack of ‘special optimal situations’ make efficient programming
1.2

CPU Registers
• Working Register (W)
• Status – Register
• FSR – File Select Register
• INDF
• PCLATH
• Program Counter
• PCL
• Eight Level Stack
1.2

1.2
PIC16C72 PIC16C73 PIC16C74 PIC16C76 PIC16C77
Clock Maximum
Frequency
of
Operation
(MHz)
20 20 20 20 20
Memory EPROM
Program
Memory
(x14 words)
2K 4K 4K 8K 8K
Data
Memory
(bytes)
128 192 192 368 368

1.2
Peripheral
s
Timer
Module(s)
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Co
mpare/
PWM
Module(s)
1 2 2 2 2
Serial
Port(s)
(SPI/I2C,
USART)
SPI/I2C SPI/I2C
USART
SPI/I2C
USART
SPI/I2C
USART
SPI/I2C
USART
Parallel
Slave Port
- - Yes - Yes
A/D
Converter
Channels
5 5 8 5 8

1.2
Features Interrupt
Sources
8 11 12 11 12
I/O Pins 22 22 33 22 33
Voltage
Range
(Volts)
2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
In-Circuit
Serial
Programmin
g
Yes Yes Yes Yes Yes
Brown-out
Reset
- Yes Yes Yes Yes
Packages 28-pin
SDIP,
SOIC,
SSOP
28-pin SDIP,
SOIC, SSOP
40-pin SDIP,
PLCC, MQFP,
TQFP
28-pin
SDIP,
SOIC
40-pin
SDIP,
PLCC,
MQFP,
TQFP

1.3
Pipelining

Pipelining
1.3

Pipelining
• Internal division of oscillator clock input as Q1, Q2, Q3, and
Q4.
• PC is incremented every Q1
• Instruction is fetched from the program memory
• Latched into the instruction register in Q4.
• Decoding and execution in next Q1 through Q4.
1.3
Clocking Scheme/Instruction Cycle

1.3
Pipelining
Fetch of nth
instruction
from
address n
Fetch of (n+1)th
instruction from
address n+1
(goto New
address
Instruction)
Fetch of (n+2)th
instruction from
address n+2
Fetch instruction
from new address
Execution
of nth
instruction
Change
program
counter to
new address
Ignore the (n+2)th
instruction
Cycle
Cycle Cycle Cycle

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3, and
Q4).
The instruction fetch and execute are pipelined
Fetch takes one instruction cycle
Decode and execute takes another instruction cycle.
Due to the pipelining, each instruction effectively executes in one
cycle.
1.3
Pipelining

• A fetch cycle begins with the program counter (PC)
incrementing in Q1.
• In the execution cycle, the fetched instruction is latched into
the “Instruction Register (IR)” in cycle Q1.
• This instruction is then decoded and executed during the Q2,
Q3, and Q4 cycles.
• Data memory is read during Q2 (operand read) and written
during Q4 (destination write).
1.3
Pipelining
Two cycle instruction(Branch)

All instructions are single cycle, except for any program branches. These
take two cycles since the fetch instruction is “flushed” from the pipeline
while the new instruction is being fetched and then executed.
1.3
Pipelining (Example)
Fetch1
Fetch 2
Fetch3
Fetch4
Fetch SUB-1
Execute1
Execute2
Execute3
Flush
Execute SUB-1
CY1 CY2 CY3 CY4 CY5 CY6
loop Address Instruction
1 MOVLW 55h
2 MOVWF PORTB
3 CALL SUB-1
4 BSF PORTA, BIT3
SUB-1 5 ADDW

Memory organisation
It has three memory blocks.
• Program memory
• Data memory
• Stack
1.4

1.4
Program memory Considerations
Hex address
000
Program memory
.
.
.
.
.
.
.
3E7
7FF
2K
Addresses
(11 bit range)
X X 0 1 1 1 1 1 0 0 1 1 1
Ignored Bits
3 E 7
Program counter (13 bit)
11
12 0
How to access 2K Program memory
10

1.4
Hex address
000
Program memory
.
.
.
.
.
.
.
BA5
FFF
4K
Addresses
(12 bit range)
X 1 0 1 1 1 0 1 0 0 1 0 1
Ignored Bit
B A 5
11
12 0
How to access 4K Program memory

• Each PIC 16CXX family either consists of 2K or 4K addresses of
program memory
• A program memory of 2K needs only an 11 bit program counter
to access any address.
• A program memory of 4K needs only an 12 bit program counter
to access any address.
• 13 bit program counter allowing extension of PROM into 8K
program memory without changing the CPU structure.
• For the 4K and 2K parts the upper bits are similarly ingored
during fetches from program memory.
1.4

Structure of Mainline program
Mainline
Call Initial ; Initialize everything
Mainloop
Call Task1 ; Deal with Task1
Call Task2 ; Deal with Task2,
.
.
.
.
Call Looptime ;Force looptime to a fixed value
goto mainloop ;Repeat
1.4

Program Memory Map
1.4
MZCET/EEE/EE6008/1
85
Hex address 0 00 Program memory
.
FFF
Goto main line
Goto Intservice
001
003
002
004
Tables
Mainline
program and
its subroutines
Interrupt
service routine
and its
subroutines
005
End of Tables
Mainline
IntService
End of code

• Two addresses are treated in a special way by the CPU.
• After reset state, its program counter is at zero.
• Content of address H’000’1 being goto Mainline
instruction.
• when an interrupt occurs, second special address
H’004’, is loaded into the PC.
• A goto Intservice instruction can be assigned to this
address
• Cause the CPU to jump to the beginning of the
interrupt service routine.
1.4

• If task 1 is supposed to toggle an LED indicator lamp
every half second, then it need only increment a scale of
50 counter once per call of Task1.
• Then LED will be toggled once for each complete cycle
of this counter.
• The mainline program begins execution when PIC
comes out of resent.
• It continues running until one of the PIC’s interrupt
sources request service.
• At that point, the execution of mainline code is
temporarily suspended.
1.4

• CPU begins the execution of the interrupt service
routine by automaticaaly loading the program
counter with H’004’.
• At the completion of interrupt service routine,
CPU returns to where it left off in the Mainline
program.
• Program writing is somewhat simplified if all the
program code for the tables, the mainline
program and its subroutines, interrupt service
routine and its subroutines take up less than 2K
words of instruction.
1.4

1.4
Hex address
000
Program memory
.
.
.
.
.
.
.
7FF
FFF
4K
Addresses
(12 bit range)
11
12 0
How 11 bit call instruction is executed
800
2K
Addresses
(11 bit range)
X X
0
3
4
PC LATH
PC LATH,3 = 0
PC LATH,3 = 1
0

• It is a result of having a one word subroutine call
instruction.
• Bits of 10….0 of the call instruction are loaded into the
program counter.
• At the same time, bits 4 and 3 of a special register called
PCLATH ( program counter Latch) are loaded into bits 12
and 11 of the program counter.
1.4

• As long as the program memory is less than 2048 words,
bits 4 and 3 of PCLATH can be left initialized to H’00’,.
• 11 address bits in the call instruction will identify the
starting address of any subroutine located upto address
F’7FF’.
• Programs larger than this, it is necessary to ensure that bit
3 of PCLATH is set or cleared appropriately each time a
subroutine is called.
• The Goto instruction which also has an 11 bit address field
requires an same treatment.
1.4

Data memory
Register File consists of two components.
• General purpose register file ( RAM).
• Special purpose register file (similar to SFR in
8051).
1.5
Data Memory is also known as Register File.

MZCET/EEE/EE6008/1
93
Register File Structure
1.5
Special Purpose
Registers
(32 bytes)
RAM
(96 bytes)
00
1F
7F
20
Bank 0
(128 bytes)
Special Purpose
Registers
(32 bytes)
RAM
(32 bytes)
Extra RAM
(64 bytes)
In
PIC16C63
PIC16C65A
PIC16C73A
PIC16C74A
80
9F
FF
A0
Bank 1
(128 bytes)

Typical SFRs
STATUS Status word + flags
OPTION Timer options
PCLATH
PCL
Components of program
counter (PC)
FSR
File Select for indirect data
addressing
INTCON, PIR1, PIE1,
PIR2, PIE2
Components of interrupt
handling
PORTA, TRISA, … Access to parallel ports
TMR0, OPTION,
INTCON, …
Timer0
TXREG, TXSTA,
RCREG, RCSTA, …
Access to serial port
ADRESH, ADRESL,
ADCON0, …
Access to A/D converter
EEADRH, EEDATA, …
Access to EEPROM and
Flash memory
GPR
General Purpose Registers
User program data
SFR
Special Function Registers
Reserved for
Control / configuration
Peripheral access
Indirect addressing
Program counter
Core SFRs
Appear in every bank at
same file address
1.5

The register file can be accessed either
directly, or indirectly, through the File Select
Register (FSR)
1.5
95
MZCET/EEE/EE6008/1

STATUS REGISTER (ADDRESS 03h, 83h)
bit 7 IRP(1): Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh) ; 0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1(1):RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh) ;
10 = Bank 2 (100h - 17Fh) ;
01 = Bank 1 (80h - FFh) ;
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
1.5
SPECIAL FUNCTION REGISTERS

STATUS REGISTER (ADDRESS 03h, 83h)
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction ;
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/ borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)
(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C(2): Carry/ borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
1.5

• The special purpose register file consists of
input/output ports and control registers.
• Addressing from 00H to FFH requires 8 bits of address.
• Instructions that use direct addressing modes in PIC to
address these register files use 7 bits of instruction
only.
• Register bank select (RP0) bit in the STATUS register is
used to select one of the register bank
1.5
Special Purpose Registers

INDF
Core SFR accessible at file address 00h in all banks
Virtual pointer — not physical register
Tracks contents of FSR
Simplifies pointer arithmetic
Example
In register file,
[05] = 10h
[06] = 0Ah
Load FSR ← 05
[INDF] = 10h
FSR++
[INDF] = 0Ah
;
;
;
;
FSR points to file address 05
INDF points to file address 05
increment FSR ⇒ FSR = 06
INDF points to file address 06
INDF Register
1.5
In register file,
[05] = 10h
[06] = 0Ah
Load FSR ← 05
[INDF] = 10h
FSR++
[INDF] = 0Ah

The OPTION_REG register is a readable and writable
register, which contains various control bits to configure the
TMR0/WDT prescaler, the external INT Interrupt, TMR0 and the
weak pull-ups on PORTB.
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
1.5
OPTION Register (ADDRESS 81h)

bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
1.5

bit 2-0 PS2:PS0:
Prescaler Rate Select bits
1.5
Bit value TMR0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1:16 1:8
100 1:32 1:16
101 1:64 1:32
110 1:128 1:64
111 1:256 1:128

bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts ;
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts;
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt;
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt;
0 = Disables the RB0/INT external interrupt
1.5
INTCON Register (ADDRESS 0Bh, 8Bh)

bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt;
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state(1)
0 = None of the RB7:RB4 pins have changed state
1.5
INTCON Register (ADDRESS 0Bh, 8Bh)

PIE1 Register (ADDRESS 8Ch)
bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt;
0 = Disables the PSP read/write interrupt
bit 6 ADIE(2): A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt;
0 = Disables the A/D interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt;
0 = Disables the USART receive interrupt
1.5

PIE1 Register (ADDRESS 8Ch)
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt;
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt;
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt;
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt;
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt;
0 = Disables the TMR1 overflow interrupt
1.5

1.5
bit 7-2: Unimplemented: Read as '0'
bit 1: POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred
(must be set in software after a Power-on Reset occurs)
bit 0: BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred
(must be set in software after a Brown-out Reset occurs)
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as
‘0’
- n = Value at POR reset
q = value depends on conditions
PCON REGISTER (ADDRESS 8Eh)

PC low (PCL) = PC<7:0>
Accessible by instruction reads/writes
PC high (PCH) = PC<12:8>
Not directly accessible to instructions
PC latch high (PCLATH)
Core SFR accessible at file address 0Ah in all banks
PCH = PC<12:8> = PCLATH<4:0>
PCLATH<7:5> not implemented
PC 0
1
2
3
4
5
6
7
8
9
10
11
12
offset
page
PCL
PCH
PCLATH
0
1
2
3
4
1.5
CPU Registers
Program Counter

• The program counter (PC) is 13-bits
wide.
• The low byte comes from the PCL
register, which is a readable and
writable register.
• The upper bits (PC<12:8>) are not
readable, but are indirectly writable
through the PCLATH register.
• On any RESET, the upper bits of the
PC will be cleared
• The upper one how the PC is
loaded on a write to PCL
(PCLATH<4:0> → PCH).
• The lower one how the PC is loaded
during a CALL or GOTO instruction
(PCLATH<4:3> → PCH).
1.5
CPU Registers
PCL and PCLATH

instruction
…
instruction
…
instruction
…
instruction
instruction
instruction
instruction
instruction
…
instruction
instruction
instruction
1…1 1…11
…
1…1 0…00
…
0…1 1…11
…
0…1 0…11
0…1 0…10
0…1 0…01
0…1 0…00
0…0 1…11
…
0…0 0…11
0…0 0…10
0…0 0…01
Page 2
Page 1
Page 0
instruction
Memory
Location
0…0 0…00
page offset
Address
k bits
offset
n – k bits
page
Instruction address
n bit location address
Location = instruction
≤ 2n instructions
Instruction width
12 / 14 / 16 bits
Page
Partition of instruction
memory space
2k instructions / page
k bit offset
n bit address
Instruction Memory Space
All 8‐bit MCUs
1.5

Mid-Range instruction memory
14-bit instruction word
n = 13
213 = 8192 instruction words
k = 11
Page = 211 = 2048 = 800h words
Program counter (PC)
PC<12:11> = page number ⇒ 4 pages
PC<10:0> = offset
Reserved addresses
Address 0h
Reset vector — pointer to reset routine
Address 4h
Interrupt vector — pointer to interrupt service routine
2 bits
page
13 bit PC
11 bits
offset
0
10
11
12
1.5
Instruction Memory Space
All 8‐bit MCUs

Stack
8 level FILO buffer
Holds 13 bit instruction addresses on CALL/RETURN
Function entry
CALL instruction
STACK ← PC<12:0>
PCL ← literal<10:0> from instruction
PCH<12:11> ← PCLATH<4:3>
Function exit
RETURN instruction
PC<12:0> ← STACK
PCLATH not updated
May be different from PCH after RETURN
0
1
2
3
4
5
6
7
8
9
10
literal
PC 0
1
2
3
4
5
6
7
8
9
10
11
12
PCLATH
0
1
2
3
4
STACK
CALL
RETURN
1.5
Call / Return

Instruction Format
1.6
CALL / GOTO
k = 11 bit literal (immediate)
General literal
k = 8 bit literal (immediate)
Bit oriented
b = bit position in register
f = 7 bit file address
Byte oriented
d = 0 ⇒ destination = W
d = 1 ⇒ destination = f
f = 7 bit file address
0
11 10
13
k
opcode
0
8 7
13
k
opcode
0
7 6
10 9
13
f
b
opcode
0
8 6
7
13
f
d
opcode

Instruction Set
1.6
Mnemonic Operands Description Cycles Status bits
affected
bcf f,b Clear bit b of register f,
Where bit b = 0 to 7
1
bsf f,b set bit b of register f,
Where bit b = 0 to 7
1
Single bit Manipulation

Instruction Set
1.6
affected
clrw Clear W 1 Z
clrf f Clear f 1 Z
movlw k Move literal value to W 1
movwf f Move the value of W to f 1
movf f,F(W) Move the value of f to F
or W
1 Z
swapf f,F(W) Swap nibbles of f, putting
result into F or W
1
Clear/move

Instruction Set
1.6
affected
incf f,F(W) Increment f, putting result
into F or W
1 Z
decf f,F(W) Decrement f, putting
result into F or W
1 Z
comf f,F(W) Complement f, putting
result into F or W
1 Z
Increment/Decrement/complement

Instruction Set
1.6
affected
addlw k Add literal value into W 1 C, DC, Z
addwf f,F(W) Add W with f, Putting
result into F or W
1 C, DC, Z
sublw k Subtract W from literal
value, putting result in W
1 C, DC, Z
subwf f,F(W) Subtract W from f, putting
result in F or W
1 C, DC, Z
Addition/Subtraction

Instruction Set
1.6
affected
andlw k AND literal value into W 1 Z
andwf f,F(W) AND W with f, Putting result
into F or W
1 Z
iorlw k Inclusive OR literal value
into W
1 Z
iorwf f,F(W) Inclusive OR W with f,
Putting result into F or W
1 Z
xorlw k Exclusive OR literal value
into W
1 Z
xorwf f,F(W) Exclusive OR with f, Putting
result into F or W
1 Z
Multiple bit manipulation

Instruction Set
1.6
affected
rlf f,F(W) Copy f into F or W;
Rotate F or W left through
the carry bit
1 C
rrf f,F(W) Copy f into F or W;
Rotate F or W right
through the carry bit
1 C
Rotate

Instruction Set
1.6
affected
btfsc f,b Test bit b of register f,
where bit b = 0 to 7;
Skip if clear.
1 (2)
btfss f,b Test bit b of register f,
where bit b = 0 to 7;
Skip if set.
1 (2)
decfsz f,F(W) Decrement f, putting
result into F or W;
Skip if zero.
1 (2)
incfsz f,F(W) increment f, putting result
into F or W;
Skip if zero.
1 (2)
Conditional Branch

Instruction Set
1.6
affected
goto Label Go to labeled instruction 2
call label Call labeled instruction 2
return Return from subroutine 2
retlw k Return from subroutine,
putting literal value in W
2
retfie Return from interrupt
service routine;
Re enable interrupts
2
unconditional Branch

Instruction Set
1.6
affected
clrwdt Clear watch dog timer 1 NOT_T0,
NOT_PD
sleep Go to in standby mode 1 NOT_T0,
NOT_PD
nop No operation 1
Miscellaneous

1.7
MZCET/EEE/EE6008/1
123
Addressing Modes
Direct Addressing
7 6 5 4 3 2 1 0
X X X X X X
STATUS Register
RP1 RP0 6 5 4 3 2 1 0
Instruction
00
7F
80
FF
Bank0 Bank1
0 0
Bank
Address
Content

Notation
REG<b> Bit b in register REG
REG<a:b> Bits a to b in register REG
A.B
Concatenation of A and B
(A bits followed by B bits)
Addressing Modes
Direct addressing
Program specifies data address
Bank selection
STATUS bits RP1 and RP0
On reset
RP1 = RP0 = 0 ⇒ bank 0 selected
Bank switching
Write to STATUS<6:5>
File Address
Literal field in instruction
0
7 bits from instruction
file address
5 4 3 2 1
6
RP1 RP0
bank
8 7
1.7

1.7
MZCET/EEE/EE6008/1
125
Addressing Modes
Indirect Addressing
7 6 5 4 3 2 1 0
X X X X X X X
STATUS Register
IRP1 7 6 5 4 3 2 1 0 FSR
00
7F
80
FF
Bank0 Bank1
0
Bank
Address
INDF
1

Indirect addressing
Program writes to Special Function Registers (SFRs)
Address formed from SFRs
Instructions can increment/decrement SFR values
Similar to pointer arithmetic
File Select Register (FSR)
Core SFR accessible at file address 08h in all banks
File Address
FSR<6:0>
Bank
IRP.FSR<7>
STATUS bit IRP (Indirect Register Pointer)
On small devices
1 or 2 banks = 128 or 256 bytes of data memory
8 bit FSR address covers 2 banks
IRP not implemented (read 0 / write = NOP)
8 bits of FSR
IRP
bank
0
1
file address
4 3 2
5
6
7
8
1.7
Addressing Modes

; ** IF DEVICE HAS BANK1 **
Sample Program
RAM Initialization
1.8
CLRF STATUS ; STATUS ← 0
MOVLW 0x20 ; W ← 1st address in GPR bank 0
MOVWF FSR ; Indirect address register ← W
Bank0_LP
CLRF INDF0 ; address in GPR ← 0
INCF FSR ; FSR++ (next GPR address)
BTFSS FSR, 7 ; skip if (FSR<7> == 1) ⇒ FSR = 80h
GOTO Bank0_LP ; continue
MOVLW 0x80 ; W ← 1st address in GPR bank 1
MOVWF FSR ; Indirect address register ← W
Bank1_LP
CLRF INDF0 ; address in GPR ← 0
INCF FSR ; FSR++ (next GPR address)
BTFSS STATUS, C ; skip if (STATUS<0> == 1) ⇒ FSR = 00h
GOTO Bank1_LP ; continue
In register file,
[05] = 10h
[06] = 0Ah
Load FSR ← 05
[INDF] = 10h
FSR++
[INDF] = 0Ah

; W ← Prog10<15:8>
; operator HIGH reads bits <15:8>
of pointer
movwf PCLATH
goto Prog10
; PCLATH ← W
; PC<10:0> ← Prog10<7:0>
; PC<12:11> ← PCLATH<4:3>
Prog10:
;
; Prog10 labels some address in program memory
;
Prog:
movlw HIGH Prog10
Sample Program
Branch to address in new page
1.8

Prog20:
;
; Prog20 labels some address in program memory
;
Sample Program
Computed goto
1.8
movlw HIGH Prog20 ; W ← Prog20<15:8>
movwf PCLATH ; PCLATH ← W
movlw LOW Prog20 ; W ← Prog20<7:0>
movwf PCL ; PCL ← Prog20<7:0>
; PCH ← PCLATH<4:0>

btfss f,b ; skip one instruction if
; bit b in register f = 1
goto Action2
Action1:
; instructions for Action1
goto Action3
Action2:
Action3:
Sample Programs
if‐else branch
1.8
F<b> =1?
Action 2
Action 1
Action 3
Yes No

; W ← times
; COUNTER ← W (times)
; COUNTER--
; COUNTER = 0 ⇒ skip next
instruction
; next iteration
movlw times
movwf COUNTER
Loop:
;
; loop instructions
;
decfsz COUNTER, f
goto Loop
End:
;
;
Sample Programs
Static loop
1.8

movlw HIGH Table
movwf PCLATH
movf INDEX, W
call Table
;
Table:
addwf PCL, f
; Function call returns data at Table.INDEX
; W ← Table<15:8>
; PCLATH ← W
; W ← INDEX
; Call to subroutine table
; PCL ← PCL + W = PCL + INDEX
; computed goto
; return with W ← 'A'
retlw 'A'
retlw 'B'
retlw 'C'
retlw 'D'
retlw 'E'
Sample Programs
Data table in instruction memory
1..8

Class Test-1
1. Explain the architecture of PIC16CXX Series.
(15)
2. Explain the classification of instruction set.
(15)
3. Explain the Pipelining Process.(8)
4. Write any four features of PIC 16CXX series.
(2)
5. Write the function of BOR register.(2)

Unit_I.pptx

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Unit_I.pptx