DWS VS. SPICE COMPARISONS FROM NGSPICE USERS FORUM DISCUSSION " SPICE- DWS INTEGRATION"

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DWS VS. SPICE COMPARISONS FROM NGSPICE
USERS FORUM DISCUSSION " SPICE- DWS
INTEGRATION"
RESEARCH · DECEMBER 2015
DOI: 10.13140/RG.2.1.1388.2960
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Piero Belforte
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1 Piero Belforte Marcel Hendrix December 2015
DWS VS. SPICE COMPARISONS FROM NGSPICE USERS
FORUM DISCUSSION " SPICE- DWS INTEGRATION"
The original discussion is available here:
https://sourceforge.net/p/ngspice/discussion/133842/thread/8f20bc1b/
Forum: ngspice-users
Creator: marcel hendrix
Created: 2015-10-09
Updated: 2015-11-26
Comparative simulation tests among DWS and Spice versions including Ngspice, Ltspice and Microcap11 are presented
for several circuits not including Transmission Lines that are dealt with in a previous forum discussion available at :
https://sourceforge.net/p/ngspice/discussion/133842/thread/363a66f8/
Start is here:
https://sourceforge.net/p/ngspice/discussion/133842/thread/363a66f8/#6b59/bde8/fdee/156c/c818
Marcel, attached here the DWS result at 20ps tstep
IL goes to 0 at 56.82us, different with respect your result (about 43us).
V(1) should be a simple 5 volt amplitude sine. It appears to be severely flattened on the positive side. The
amplitude of the inductor current is about +62mA. All other mismatches could come from that. Why the
distortion?
This a classical circuit showing chaotic behavior. I already studied it with DWS since the '80s.
It is not chaotic (only 2nd order). I created it to show what happens when the diode does not turn
off exactly at the right moment. It is even better visible with an ideal diode (Roff, Ron only).
The second item it tests is the quality of TRAP method (current NGSPICE fails this test). The amplitude of
the oscillation should be constant for about 11us after the current zero crossing.
(NGSPICE runtime: 60 ms)
-marcel
Last edit: marcel hendrix 2015-10-09
inductor_D.png
inductor_D_detail.png

inductor_D_reference.png

marcel hendrix
2015-10-09
I just discovered that the phase of sin source is NOT supported by DWS syntax, so the circuits are
different. Can you try using a phase equal to 0?
That works. I see that your plots are now much better matching.
Two questions:
1. does the current cross 0 at 78.6886us (I see you use a STEP of 20ps)?
2. How long did the SWAN simulation take (SPICE: 49ms)?
-marcel
o
Piero Belforte
2015-10-09
Marcel as you can see in the interacive plot, the current crosses 33.5uA at 78.68us and -59uA at
78.69966us for both DWS (TSTEP=20PS) and ngspice (TMAX=100PS)
https://plot.ly/~piero.belforte/5789.embed
DWS elapsed time at TSTEP=20PS is 8.3sec ...should be compared to ngspice at TMAX<=100PS.
At TSTEP=2NS DWS elapsed time is about 100ms with results apparently still good. I used 20PS to get a
REFERENCE result.
Attached a zoomed view pinpointing the DWS/NGS small phase shift of current oscillations after cut-off.
Last edit: Piero Belforte 2015-10-09
MARCEL_VLDIODE_NO_PHASE_SHIFT_DWS_20PS_VS_NGS25_100PS (2).jpg
X

MARCEL_VLDIODE_NO_PHASE_SHIFT_DWS_20PS_VS_NGS25_100PS (3).jpg
X

Piero Belforte
2015-10-09
I ran SpicySWAN between 78.6 and 78.7 us both in DWS at 1PS and NGSPICE25 AT 50ps (its limit before
time-out) to get an accurate first zero crossing of the inductor current.
I got the following values.
DWS 1PS: 78.68624 us (residual I=90pA) should be the "EXACT VALUE" because of 1PS TSTEP (about 80
MEGASAMPLES calculated in few seconds online)
NGSPICE 50PS: 78.68863 uS (residual I=-136pA)
Difference 2.39ns (NGS delay)
Relative error: -0.003%


marcel hendrix
2015-10-09
DWS 1PS: 78.68624 us (residual I=90pA) should be the "EXACT VALUE"
because of 1PS TSTEP (about 80 MEGASAMPLES calculated in few seconds onnline)
I calculated the zero crossings for a range of temperatures: for 1 degree change the zerocrossing shifts
55ns already :-)
-marcel
The data ...
----------------------------------
Index temps zcs
----------------------------------
0 2.000000e+001 7.906211e-005
1 2.100000e+001 7.900726e-005
2 2.200000e+001 7.895289e-005
3 2.300000e+001 7.889901e-005
4 2.400000e+001 7.884561e-005
5 2.500000e+001 7.879269e-005
6 2.600000e+001 7.874022e-005
7 2.700000e+001 7.868817e-005
The circuit file ...
*** L_diode ***
V1 N001 0 dc=0 SIN(0 5 10K)
L2 N001 N002 1mH ic=0
D1 N002 0 1N914 temp=27

.model 1N914 D(Is=2.52n N=1.752 Rs=.568 Cjo=4p M=.4 tt=20n )
.param t_end=120us
.tran 0 {t_end} 0u 0.5u uic
.options method=trap XMU=0 reltol=1e-6
* Inductor - diode oscillation
*.inc ngspice.inc
.control
listing e
let zcs = unitvec(8)
let temps = unitvec(8)
let ix = 0
foreach mt 20 21 22 23 24 25 26 27
altermod @D1[tnom] = $mt
run
meas tran zcross WHEN I(L2)=0
let temps[ix] = $mt
let zcs[ix] = zcross
let ix = ix + 1
end
print col temps zcs > tempdata
quit
.endc
.end


Piero Belforte
2015-10-09
The ngspice 27 C value 78.68817us is close to DWS 1PS (default temp=27C) value 78.68624 us
At 20 C you get 79.06211us while DWS 1PS (temp= 20 C) gets 78.84608us
Using SpicySWAN in Spice mode (ngspice5) with TEMP=20C TMAX=50PS I get 78.84843us still close to
DWS 1PS but different with respect your value.
DWS 1PS deltaT (20C-27C) is about 160ns about 3X your ngspice value (NO TMAX).
This difference between your and my ngspice values is due probably to my TMAX=50ps while you didn't
set TMAX.


marcel hendrix
2015-10-09
Hi Piero,

Good catch! However, I was changing TNOM
(temperature at which parameters were measured), not TEMP. TNOM is not on the device line like
TEMP, that's why I used ALTERMOD.
Here I change TEMP (temperature local to the 1N914, not global to the circuit). Note that I now use the
ALTER command.
-marcel
---------------------------------
Index temps zcs
---------------------------------
0 2.000000e+001 7.855656e-005
1 2.100000e+001 7.857529e-005
2 2.200000e+001 7.859405e-005
3 2.300000e+001 7.861282e-005
4 2.400000e+001 7.863162e-005
5 2.500000e+001 7.865046e-005
6 2.600000e+001 7.866932e-005
7 2.700000e+001 7.868817e-005
::html
*** L_diode ***
V1 N001 0 dc=0 SIN(0 5 10K)
L2 N001 N002 1mH ic=0
D1 N002 0 1N914 temp=20
.model 1N914 D(Is=2.52n N=1.752 Rs=.568 Cjo=4p M=.4 tt=20n )
.param t_end=120us
.tran 0 {t_end} 0u 0.5u uic
.options method=trap XMU=0 reltol=1e-6
* Inductor - diode oscillation
.control
listing e
let zcs = unitvec(8)
let temps = unitvec(8)
let ix = 0
foreach mt 20 21 22 23 24 25 26 27
alter D1 temp = $mt
run
meas tran zcross WHEN I(L2)=0
let temps[ix] = $mt
let zcs[ix] = zcross
let ix = ix + 1
end
print col temps zcs > tempdata
quit
.endc
.end



Piero Belforte
2015-10-10
Yes, I changed TEMP not TNOM (not supported by DWS). Anyway the DELTA T of zero current crossing
is much higher (160ns) between TEMP=20C and TEMP=27C using both DWS 1PS and NGS 50PS than the
value you got (only 13ns about). I suppose that this is due to TMAX setting that you didn't use.
https://www.ischematics.com/webspicy/report.py?RCODE=25761182757633016350a#.VhfU4cCLTDc
https://www.ischematics.com/webspicy/report.py?RCODE=81163587120203124655as#newwin
I also tried with LTSPICE. Here the values:
TEMP=27C TMAX=10PS ALT.SOLV. 78.68743us
TEMP=20C TMAX=10PS ALT.SOLV. 78.55592us
While at 27C the value is very close to DWS_1PS and NGS_50PS at 20C the LTS_10PS is completely
different with respect all values obtained so far.
LTS_10PS elapsed time is about 91sec (4 CPUs)
DWS_10PS elapsed time is about 13sec.(1 CPU)
DWS SPEEDUP/CPU= 28X
Here the related plot:
MARCEL_VLDIODE_SPICE.cir
X
MARCEL_VLDIODE_SPICE_report.pdf
X
MARCEL_VLDIODE_report.pdf
X


Piero Belforte
2015-10-10
Tried with MC11 too. FIXED STEP=10PS
TEMP=27C 78.689us
TEMP=20C 78.558us
MC11_10PS elapsed time (1CPU)= 124 sec DWS SPEEDUP=10X
Values close to LTSPICE but different with respect DWS_1PS and NGSPICE_50PS
The MAJOR DIFFERENCES ARE AT TEMP=20C
DWS_1PS=78.84608us NGS_50P=78.84843us (about 2ns relative difference)
LTS_10PS=78.55592us MC11_10PS=78.558us (about 2ns relative difference)
The difference between the two groups is 290ns ! While at 20C the time increases for both DWS and
NGSPICE it decreases for both LTSPICE and MC11.
This looks very strange and should be investigated.
I ran ngpsice on Spicy SWAN with no TMAX at TEMP 20C (global) and I got 78.899us that even more
different even with respect your value (even if you uses local temp, but the only temp dependent
component is the diode, so this should not make any difference).
NOW I UNDERSTAND THE CAUSE OF THE DIFFERENCE; I took the SECOND crossing for DWS and
NGSPICE!
https://www.ischematics.com/webspicy/report.py?RCODE=47146158141411544452a#.VhjV4sCLTDc
Here the corrected values:

NGS_50PS=78.55703us
DWS_1PS=78.5548us
MARCEL_VLDIODE_SP_20C_report.pdf
X


marcel hendrix
2015-10-09
( edited: fixed bug in NGSPICE-KLU and new plot )
I tried to do an AC analysis of the TEST_ZYTL61 circuit.
That is extremely quick with NGSPICE-KLU, although one must be careful not to have any resistances <
0.1mOhm or it will produce wrong results.
The phase is of course linear with the frequency, but only
up to 7.8GHz: (25905e deg->rad) / (7.787GHz freq->omega) = 9.240829ns).
There are two nasty resonances at 3.3 and 6.6 GHz.
The gain falls off by about 3.6dB. (This could be by design as this is supposed to be rg58 coax).
-marcel
67_AC.png
o
o
Piero Belforte
2015-10-09
The resonances should not exist.
Here you will find a 100Mhz-20Ghz frequency response (log log scale) of the ZYTL model where ngspice
ac analysis (1-cell) is compared to DWS Virtual VNA (VVNA) 10-cell response. At 3Ghz the attenuation
looks higher than your result ( 1.56465dB vs 1dB) coming from my ngspice ac and DWS VVNA
simulation.
Here the attenuation is shown in db/m.

RG58_VVNA_VS_AC.jpg
X

marcel hendrix
2015-10-10
Hi Piero,
NOW I UNDERSTAND THE CAUSE OF THE DIFFERENCE; I took the SECOND crossing for DWS and NGSPICE!
That can happen.
Please complete the next table when you have corrected the error with the zero crossing.
Absolute values
TEMP MC11 LTspice_10ps NGSPICE_50ps NGSPICE_mhx DWS
20 78.558us 78.55592us 78.84843us 78.55656us 78.84608us
27 78.689us 78.68743us ? 78.68817us 78.68624us
Error relative to NGSPICE_mhx
TEMP MC11 LTspice_10ps NGSPICE_50ps NGSPICE_mhx DWS
20 -1.8e-3 8.1e-4 -3.7e-1 0 -3.7e-1
27 -1.1e-3 9.4e-4 ? 0 2.5e-3
-marcel
o
o
Piero Belforte
2015-10-10
OK, the table is attached
At 20C DWS_1P and MC11_10P are both anticipated of about 1.8ns.
At 27C only MC11_10P is anticipated of about 1ns . LTSPICE_10P is delayed of about 1ns.
Here the effect of TSTEP on DWS result:
TEMP 20C
DWS_1P=78.5548us DWS_100P=78.5548us DWS_1N=78.555us
Not so significant between 1Ps and 100PS.
MARCEL_VLDIODE_TEMP_CMP.txt
X

MARCEL_VLDIODE_TEMP_CMP.jpg
X


Piero Belforte
2015-10-10
Here a similar RLDIODE circuit with Chaotic behavior (DWS vs NGSPICE).
Zooming the plot it interestng to see how dws and ngpsice slowly get different...
here the chaotic orbits at startup:
RLDIODE_2013_FB.jpg
X
RLDIODE_DWS_VS_NGSPICE_1NS_20C.xls
X
RLDIODE_2013_TEMP_2=C_DWS_1NS_VS_NGS_INS.jpg
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RLDIODE_2013_TEMP_2=C_DWS_1NS_VS_NGS_INS (2).jpg
X

RLDIODE_report.pdf
X
o
o
marcel hendrix
2015-10-10
Here a similar RLDIODE circuit with Chaotic behavior
(DWS vs NGSPICE).
( Assuming that the diode is ideal, Vfwd=0.8V, Ron=1m, Roff=1G )
The circuit as such is not chaotic but in combination with an inaccurate simulator it becomes a system
that is. Note that I(diode) goes negative, which of course is not possible. I(diode) can only be negative
when SPICE does not find the zero-crossing of the diode current exactly.
In your example the chaos will die down when you decrease TSTEP more and more (<1ps?)
Standard SPICE has variable-step solvers that in principle can eliminate this problem (without becoming
slow), however, standard SPICE assumes 2nd order derivatives exist (polynomial approx. possible) and
therefore cannot handle discontinuities that are common in switched circuits (the only thing that
helps is setting STEPMAX to a low value).
The sketched behavior is why I have made an NGSPICE library dedicated to power-electronics + digital
control. Without its accurate event detection all sorts of unrealistic limit cycles in PWM and current
mode circuits would be possible.
LTspice is also aware of these special discontinuities and is even better at fixing them (at least for now).
-marcel
L_D4.png


Piero Belforte
2015-10-10
Ok, I'll try with the ideal diode too.
It would be interesting also to test DWS with power electronics circuits too (digital control and
switches)...


Piero Belforte
2015-10-10

Ok, I'll try with the ideal diode too.
It would be interesting also to test DWS with power electronics circuits too (digital control and
switches)...Here an example I developed one year ago.
CHAOS_BUCK_CONVERTER.jpg
X


Piero Belforte
2015-10-10
Here the RLDIODE CIRCUIT with ideal PWL diode as you proposed.
No chaos with DWS at any tstep (1PS TO 50NS), despite at 50ns the inductor modeled as LINK TL has a
time delay of 50ns! The same will happen with the STUB MODEL for the inductor (TRAP METHOD).
DWS has no problem with PWL resistors (except topological issue if you connect them directly solved by
the addition of a unit TL) because no iteration is needed
https://www.ischematics.com/webspicy/report.py?RCODE=32252721678506182322as#newwin (attach
ed)
Anyway I found chaotic circuits with pwl diodes.
RLDIODE_IDEAL_report.pdf
X


marcel hendrix
2015-10-10
Here the RLDIODE CIRCUIT with ideal PWL diode as you proposed. No chaos with DWS at any tstep
(1PS TO 50NS), despite at 50ns the inductor modeled as LINK TL has a time delay of 50ns!
This undermines my understanding of DWS :-(The STEP time is always the same, so if the physical system being
modelled forces the diode current through zero inbetween sample points, then at the next sample instant it
is not possible to calculate the value of this current, nor of any other voltage andcurrent. It would be clearly wrong
to simply set the diode current to 0 when it has become negative (without adjusting all other state variables). Are
the voltages and current the same for all tsteps {1p .. 50n}?
One way to fix this is to accurately detect that i(diode) becomes zero, andthen compute the network
recursively with the state at this tzero, forward to the next fixed tstep. Only the valuesat tstep are
stored, those at tzero are deleted (I think this is the way ACSL and Simulink do it). However, this
scheme would not be very fast, as in between tzero and tstep another or the same diode might turn on
or off, as very HF oscillations may result.
-marcel



Piero Belforte
2015-10-10
Marcel,
the response is apparently unaffected by tstep with the exception of oscillations that arise at current
cut off at largest tstep due to the integration method of the inductor. I don't see any reason why this is
not the true response.


Piero Belforte
2015-10-10
DWS simply mimics the real behavior of the circuit. T he pwl diode doesn't require any iteration to
calculate the reflected wave from the incident one. At picosecond time steps the evolution of this
circuit is very slow so no sudden event should arise between two subsequent samples. The only
approximation is due to inductor model, but at 1 PICOSECOND TIME STEP the propagation delay is
equivalent to.02 mm length, very small for a 10mh inductor....that theoretically hs no delay at all.

marcel hendrix
2015-10-10
The only approximation is due to inductor model, but at 1 PICOSECOND TIME STEP the propagation
delay is equivalent to.02 mm length, very small for a 10mh inductor....that theoretically hs no delay at
all.
That's an eye-opener.The inductors for PE have at least 5m wire on them, which roughly means 17ns
delay for the current wrt the voltage. Such delays are easily measurable with nowadays equipment.
-marcel


Piero Belforte
2015-10-11
True,
it would be very interesting to take into account that real behavior in the inductor model... this is the
reason why this circuit is a theoretical abstraction, very useful to test simulator's algorithm but without
correspondence with an actual implementation.



Piero Belforte
2015-10-12
Marcel,
here the simulation result adding a 17ns 100ohm TL to model the inductor more realistically:
Here the result adding an additional 10PF capacitor to diode model.
RLDIODE_IDEAL_TL_report.pdf
X
RLDIODE_IDEAL_TL_C_report.pdf
X


Piero Belforte
2015-10-16
I tried the original circuit (RLDIODE_IDEAL) comparing the LINK and STUB MODEL OF INDUCTOR. While
the diode current is the same for the two models, the diode voltage is different and the diode voltage
seems to be chaotic.
The chaotic behavior is present for TSTEP<=1PS .
RL_DIODE_IDEAL_CMP_1PS.jpg
X
RL_DIODE_IDEAL_CMP_1PS(2).jpg
X

RLDIODE_IDEAL_CMP_report.pdf
X
o

Piero Belforte
2015-10-16
Here a detail of first zero crossing of current at 100fs and 50fs TSTEP. Using the LINK model shows persistent
oscillations (visible only with this time scale) at 100fs disappearing at 50fs TSTEP. The stub model (TRAP
method) is always oscillations free. The current goes to 0 for both models but no negative values appear at
whatever TSTEP used.
RLDIODE_IDEAL_CMP_DETAIL_ZERO_CROSSING.jpg
X
o

Piero Belforte
2015-10-10
Here my discovery of 4 years ago, I called it WINDING CHAOS.
I simulated it up to 50sec! On this long time frame it shows a very strange changing behavior (see collage)
WINDING_CHAOS_2014.jpg
X
o


marcel hendrix
2015-10-10
I don't see any reason why this is not the true response.
The behavior of the circuit in the real world does not depend on whether we simulate it with 1ps or with
50ns.
At picosecond time steps the evolution of this circuit is very slow so no surprise should arise between two
subsequent samples.
That is true, but at 50ns steps and with digital control
it certainly will.
It is a very interesting idea that if we could afford 1ps or 1ns fixed steps, simulators would be vastly
simplified.
I have been playing with the idea of implementing devices with FPGAs and then hook these up like in the real
world. It might be possible with a high-end graphical card already today, or with a bit-coin miners' box.
o
Piero Belforte
2015-10-12
Yes, I agree. Real-time wave digital processors are already used for real time emulation of musical
instruments and vacuum tube amplifiers.
http://dafx09.como.polimi.it/proceedings/papers/paper_16.pdf
https://www.spsc.tugraz.at/sites/default/files/tube_amp_modeling.pdf
http://dafx10.iem.at/proceedings/papers/MacakSchimmel_DAFx10_P12.pdf
https://ccrma.stanford.edu/~dtyeh/papers/wdftutorial.pdf


Piero Belforte
2015-10-14
Interesting STARTUP ORBITS in circuit RLDIODE_IDEAL_TL_C (0-1ms) . Should be compared to ngspice result.
RLDIODE_IDEAL_TL_C.jpg
X

RLDIODE_IDEAL_TL_C_2.jpg
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RLDIODE_IDEAL_TL_C_report_2.pdf
X
o

marcel hendrix
2015-10-16
I'll look at the remaining questions (start of thread). KLU also needs a look.
Evidently SPICE cannot solve networks with many transmission lines with different lengths or
terminations (I need to look at KLU, though), but DWS can.
Are there circuits that DWS can not solve by itself, either because of accuracy
or because of runtime issues, and that SPICE also cannot solve, but for complementary
reasons? If such circuits cannot be shown to exist, than I'd prefer to let the issue
rest.
-marcel
o
o
Piero Belforte
2015-10-16
I think that the union of Spice and DWS is the best way to simulate all kind of circuits. This can be done
simply choosing the best tool for each application as happens in Spicy SWAN or by integrating the two
approaches in a single tool.
In case of two separate tools (Spice and DWS) there is a set of circuits that can be dealt with efficiently by
both simulators (small-medium size lumped networks). In this case using both is the best way to check the
correctness of the result (I have also examples of this situation).
The experience on actual cases shows that even in case of lumped circuits DWS can get more accurate
results than Spice thanks to its speed. In case of large size lumped circuits (no TL inside) our recent
experiments (see TL thread, ZY networks) have demonstrated that DWS can simulate them correctly while
ngspice cannot give a practical result and LTSPICE gives a uncorrect results with long simulation times.



Piero Belforte
2015-10-18
Back to RL_DIODE_IDEAL, surprise! The DWS behavior is not chaotic but unusual (see attachement).0-20
millisec window 100KS plotted TSTEP=10PS and 20PS.
After the startup that seems a chaotic behavior, VDIODE peaks shows a pseudo-periodic behavior. The stub
model has a pseudo frequency that is twice the link model. Similar effect is due to TSTEP. Doubling TSTEP the
pseudo-frequency doubles.
The envelope of VDIODE using LINK OR SUB L models is the same (see attachment).
RLDIODE_IDEAL_20MS.jpg
X
RLDIODE_IDEAL_20MS (2).jpg
X
RL_DIODE_CMP.jpg
X
o

Piero Belforte
2015-10-19
Example of small size RLC circuit: CAUER PASSBAND FILTER STEP RESPONSE (from another discussion)
Ngspice_1PS /DWS_1PS comparison
Match is good, at 20.04ns VOUT_NGS=63.7182uV VOUT_DWS=63.6239uV DELTA=85.3nV
Here 10 filters in cascade:

Match seems stll good.
DWS tested from TSTEP=100ps down to TSTEP=1fs. Accuracy starts to be good (apparently) from TSTEP=1ps
down.
CAUER_FILTER.jpg
X
CAUER_FILT_DWS_NGS_1PS_CMP.xlsx
X
CAUER_FILTER_report.pdf
X
CAUER_FILTER_10_report.pdf
X
o

marcel hendrix
2015-10-19
Hi Piero,
There are two axes for comparison: simulation speed and accuracy of the result.
To compare DWS and SPICE we should choose an accuracy (say 0.1%) and then set up the simulators for
maximum speed, but with accuracy same or better than requested. The problem is how to judge the validity
of the returned results.
Three possibilities:
1) The results (DWS/SPICE) are equal within the wanted accuracy: done.
2) They differ: a golden reference is needed. This means that only circuits can be compared for which a
golden reference exists.
3) Results differ: set BOTH simulators for a 2x better accuracy at the same time points ('linearize' in SPICE,
least squares for all points) and redo the simulation. If they now agree to within the originally stated
accuracy, compare the simulation times for the increased accuracy run. If the difference becomes worse,
abandon this circuit (or try with a 10x LOWER initial accuracy).
I suggest we need 3) as we avoid the 'golden reference' and it is easy to implement.
Trying to find out exactly how accurate a simulation is will not be useful, as different results do not (with
certainty) tell us which of the tested simulators in wrong.
Therefore a SPICE netlist of the test circuit and the results in tabular form (preferably at fixed time step), are
not sufficient: you must state the target accuracy (0.1%) and simulation time on the host PC (we need a
standard benchmark on all hosts -- I suggest SuperPI 1.9, see attached).
-marcel

superpi.png
o
Piero Belforte
2015-10-19
Marcel,
your proposal is good, we can try the method 3 to check if it works.
About golden reference I can say that DWS gives information of the error by reducing TSTEP and comparing
the results at different TSTEP. For Spice this is more complicated due the complexity of possible options.
From previous experience, running SPICE and DWS with TMAX (Spice)=TSTEP (DWS) can be an acceptable
rule to compare simulation times (if there are not major issues like those seen for LTSPICE simulating large
ZY networks).
Attached an example of a simple circuit (50MHz LC free oscillator)where the GOLDEN reference exists.
Tried SuperPI on my PC but i didn't get results (NOT CALCULATED warning, I don't know why, my OS is
Windows 7 64 bit).
LC_OSC_ERR_PEAK.jpg
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
Piero Belforte
2015-10-19
Here an example of DWS auto error evaluation related to the previous CAUER FILTER:
The integration method error decreases to 1.8e-10 peak decreasing TSTEP down to 10fs. At TSTEP=1fs it
increases (2e-9 peak) due to numerical rounding errors.
From TSTEP=10PS DOWN to 100FS the error decrease is QUADRATIC then the decrease slows down (quasi
linear) down to 10FS and then increases due to numerical errors I suppose.
Here some value (TSTEP,ERROR PEAK)
10PS, 1.1e-5 1PS,1.1e-7 100FS, 1.1e-9 10FS, 1.8e-10 1FS, 2e-9
In this case the GOLDEN REFERENCE should be DWSSTUB_10FS result. May be ngspice at TMAX=10FS
achieves the same accuracy.AT TSTEP=TMAX=10FS I think that the DWS/NGS speedup will be in the order of
100X (as already experienced.)

It is interesting to point out that the 85e-9V NGSPICE_1PS/DWSLINK_1PS peak error is about the same of
DWSLINK_1PS/DWSSTUB_1PS ERROR. Probably DWSSTUB is even better matched to ngspice at 1PS than to
DWSLINK.
Tried withNGSPICE_100FS, attached results. At TMAX=10FS I get timeout error on Spicy SWAN.
LTSPICE_10FS elapsed time 80sec (NORM SOLV.) 65sec (ALT- SOLV) 4 CPU
DWS_10FS_LINK elapsed time: 6sec 1CPU DWS/LTSPICE SPEEDUP=40-52
(as usual).
https://plot.ly/~piero.belforte/5913.embed (DWS only 1KS)
MC11_10FS elapsed time 45 sec 1CPU, DWS/MC11 SPUP=7.5
MC11 seems faster than LTSPICE at 10FS TMAX (default options for both).
10FS_CAUER_FILTER.cir
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CAUER_FILTER_DWS_10FS_CMP.csv
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CAUER_FILTER_CMP_report.pdf
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CAUER_FILTER_NGSPICE_100FS.csv
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
marcel hendrix
2015-10-19
From previous experience, running SPICE and DWS with TMAX (Spice)=TSTEP (DWS) can be an acceptable rule
to compare simulation times
For SPICE this would be very bad for both accuracy and run-time. SPICE can use up to a 6th order integration
method with embedded error control for linear networks -- forcing it to use Backward Euler is like using a
race-horse to plough the field.
-marcel


Piero Belforte
2015-10-19
I understand. Do you think that at limited step (and TRAP method) Spice is affected by accuracy issues?. My
experience with MC11 seems demonstrate the opposite
This can be a circuit to evaluate the effects of TMAX and various options on Spice:
https://www.ischematics.com/webspicy/report.py?RCODE=35643120267137413840a#newwin.
From several trials it seems that at the same accuracy level the Spice elapsed time is about the same using
reltol and vrtol or TMAX.
I tried with MC11 because ngspice timed out. MC11 with TMAX=10PS has an elapsed time of 337 sec and
error (peak value) at 100us is 8.164mV.
With no TMAX but reltol=vrtol=1e-9 the elapsed time is 154sec and the error at 100us is 29mV.
With reltol=vrtol=1e-12 the elapsed time is about 1380 sec and the error is 1mV (constant with time)
DWS_1PS elapsed time is 37sec error is 2uV at 100us but about 50uV at t=0usec (phase error decreasing
with time, see next discussions).
MC11_1PS elapsed time will be in the order of 1hour peak error will be more than 50uV (guess)
See

For this circuit it seems that Spice (MC11) is not able to reach the accuracy of DWS acting on tolerances.
TMAX reduction seems the best way for MC11 to achieve lower errors, similar to DWS errors. DWS/MC11
speedup is about 100X.
Looking at DWS error vs TSTEP (attached) I pointed out a sistematic error due to a TSTEP/2 anticipated
response of LC oscillator (to be investigated).
This is the reason why DWS error at 1PS starts from 50uV and then decreases while MC11 (ngspice too)
starts from 0 and then increases. To compare the results the DWS peak error should be corrected
subtracting the initial 50uV from the peak error profile values. In this way the peak error profile will look
very similar (YELLOW AREA in the related plot). I tried to correct this adding delaying the LC output
of TSTEP but this overcompensate the error because the correction should be of TSTEP/2 (non
implementable).
I have recalculated a more accurate (more digits) value of capacitance to get 50MHz:
C = 10.13211836424pF
By the way LTSPICE seems not to work correctlly : the LC output is always 0 even if UIC has been added to
.TRAN. To be clarified (LTSPICE BUG?)
LC_OSC_ERROR_MC11_1E-12_TOL_2.jpg
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LC_OSC_ERROR_DWS_1PS_2.jpg
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LC_OSC_ERROR_VS_TSTEP_DWS.jpg
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LC_OSC_ERROR_MC11_1PS_2.jpg
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LC_OSC_ERROR_report.pdf
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
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Piero Belforte
2015-10-23
Marcel,
about host pc benchmarking I propose to run the same test circuit with the same application with the same
options (LTspice and or MC11) and comparing the simulation times. This comparative benchmark can be
more significant than a generic one because is focused on the application of interest.

marcel hendrix
2015-10-23
Hi Piero,
At first I thought that a good idea, but the problem is that there are many NGSPICE variations around (e.g.
32/64 bit, Windows native, Windows console, Cygwin, Linux, with KLU, CUSpice,-- and there are many
options possible for each binary (from debug mode to fully optimized with AVX-2).
We could change to a real floating-point benchmark as PI could be using integers only.
-marcel

Piero Belforte
2015-10-23
Yes, I proposed to use MC11 or LTSPICE (latest releases) installed on our pcs, so there is no compilation
option to choose from.


Piero Belforte
2015-10-19
Marcel, here my considerations:
DWS (L-STUB) and Spice (TRAP) at the same fixed should give exactly the SAME RESULTS for RLC networks
(except numerical issues).
From previous examples it seems that a simplified method for SPICE vs DWS speed comparison at the same
accuracy level is to simulate at TMAX=TSTEP with default Spice options.DWS STUB (TRAP) model for
inductors is recommended to get the best matching.
If this criterion is followed, a DWS speedup from about 10 to 100 is experienced on lumped small-size RLC
networks. Increasing circuit complexity this speedup can increase up to a level where Spice is no more able
to give accurate results (1000 ZY cells example).
For networks with TLs a 100X speedup is normally experienced up to a complexity level where Spice is no
longer able to deal with the circuit. TL model issues are present in all Spice version tested (except MC11 but
with the IC cap bug).

Both DWS and Spice can produce a reference waveform (DWS is faster) if a enough small TSTEP/TMAX is
chosen (not too low to avoid numerical roundoff errors). A DWS/SPICE comparison (at the same plot step) of
lowest TSTEP/TMAX results can be used as reference result validation.

marcel hendrix
2015-10-19
I understand. Do you think that at limited step (and TRAP method) Spice is affected by accuracy issues?. My
experience with MC11 seems demonstrate the opposite
I am almost certain of it. A suitable stiff differential equation will force a fixed-step solver to very small steps
where round-off kills it. When I have time again I will construct an example.
-marcel
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Piero Belforte
2015-10-19
ok. In meantime I'm doing experiments with the LC oscillator.


marcel hendrix
2015-10-21
By the way LTSPICE seems not to work correctly : the LC output is always 0 even if UIC has been added to
.TRAN. To be clarified (LTSPICE BUG?)
This is because LTspice optimizes for power-electronics and adds 1mOhm in series with the inductor and
maybe also an Rpar.
You have to switch both these defaults off and use .options method=TRAP.
By the way it works, Gear damps high-frequencies. For NGSPICE, TRAP is implemented wrong and will be
fixed in a coming release.
o
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Piero Belforte
2015-10-21
Tried ngspice on a short time window (100ns). It works well at TMAX=1PS and gives results similar to MC11.
DWS gives the initial error due to the TSTEP/2 shift of output, and is not directly comparable at these short
time windows.
Here the related report in spice mode (ngspice 25):

https://www.ischematics.com/webspicy/report.py?RCODE=12867061278440206850a#newwin
It's interesting to point out that the error with more accurate CAP value is worse than with truncated cap
value. This means that the slightly higher frequency compensates the phase shift due to trap integration
method. Ngpsice online gives the same results.
At TMAX=50fs (lowest possible before SpicySWAN time out in Spice mode) the nominal value gives a better
response with the peak errror less than .3nV.
Attached the results of MC11 on the 100ns window, working at fixed step. They match ngspice results.
Interesting to point out the ACCURACY CEILING at very low TSTEP/TMAX (10fs) due probably to roundoff
issues. A 100fs TMAX should be chosen to minimize the phase shift error.
For long time windows (100us and up to ms) Spice gets too slow to be utilizable while DWS is able to run at
about a 100X speed.
Attached the DWS result at TSTEP=1ps on a 100us window. In yellow the error subctracting the initial value
due to T/2. Elapsed time 173sec on my PC 72sec on line (It's time to change my PC!). At TSTEP=100FS the
error grows up with respect TSTEP=1PS.
Elapsed time MC11_10PS is about 10min (100us window) , DWS_10PS 15sec DWS/MC11 speedup=40X,
error is about the same.
Setting GEAR instead of TRAP on MC11 at TMAX=1ps the error grows up to 30uV instead of 8uV at
100usec).
Also interesting to consider that this simple circuit is equivalent (TRAP METHOD) to a 2 OPEN TL STUBS
WITH TSTEP/2 DELAYS CONNECTED TOGETHER. The resonant frequency error is due to the extra
capacitance of L model and extra inductance of C model.
LC_OSC_ERROR_CMP_DWS_100FS_100US.jpg
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LC_OSC_ERROR_ACC_MC11_0.5-1PS.jpg
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LC_OSC_ERROR_ACC_MC11_10FS_100FS.jpg
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LC_OSC_ERROR_CMP_DWS_1PS_100US.jpg
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LC_OSC_ERROR_CMP_report.pdf
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
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Piero Belforte
2015-10-21
LTSPICE still doesn't work, seems an issue due to IC. Attached netlist
LC_OSC_ERROR_CMP_LTSPICE.cir
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
Piero Belforte
2015-10-22
New TEST CIRCUIT: LC OSCILLATOR WITH CLAMPED OUTPUT
Can be simulated by both DWS and ngspice. LTspice and MC11 can't because don't have the behavioral
elements (B).
First DWS version:
Second DWS version (Nominal capacitance)
ngspice version
https://www.ischematics.com/webspicy/report.py?RCODE=46015345256074416666a#.VikqVsmLTDc
DWS elapsed time: 500s window 0-1msec TSTEP=10ps (100 Msamples) see attached result. Error=22uVpeak
Signal=100mV peak
To be compared to ngspice (if it is affordable).
LC_OSC_CLAMPED_ERROR_DWS_10PS_1MS.jpg
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LC_OSC_CLAMP_ERROR_report.pdf
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LC_OSC_CLAMP_SWAN_report.pdf
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LC_OSC_CLAMP_SPICE_report.pdf
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
Piero Belforte
2015-10-23
ADDING A NEGATIVE RESISTIVE LOAD (-1K) TO PREVIOUS CLAMPED LC OSCILLATOR
DWS version:
https://www.ischematics.com/webspicy/report.py?RCODE=46423824471250603010as#.Vin0MsmLTDc
NGSPICE version:
Here the comparative plots:
DWS vs NGSPICE at 1PS TSTEP TMAX
DWS INTEGRATION ERROR EVALUATION (1PS,100FS,10FS TSTEP COMPARISON)
Peak error (1PS -10FS)of error waveform at 1PS is 50uV
Peak error (100FS -10FS)of error waveform at 1PS is about 5uV near the ceiling of accuracy.Should be tried
with ngspice at 10FS TMAX
DWS elapsed time at TSTEP=10FS: 102 sec (my pc)
LC_OSC_CLAMP_-1K__DWS_ERROR.jpg
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LC_OSC_CLAMP_-1K_1PS_DWS_VS_NGS.jpg
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LC_OSC_CLAMP_-1K_1PS_DWS_VS_NGS_DETAIL.jpg
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LC_OSC_CLAMP_SWAN2_report.pdf
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LC_OSC_CLAMP_SPICE2_report.pdf
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Attach
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
Piero Belforte
2015-10-23
CLAMPED LC OSCILLATOR WITH SWITCHED NEGATIVE RESISTIVE LOAD
Should be tried with ngspice to make the comparison.
LC_OSC_CLMP_SW_SWAN_report.pdf
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
Piero Belforte
2015-10-23
A SIMPLE CIRCUIT : 178 Mhz FIFTH HARMONIC QUARTZ CRYSTAL, CURRENT STEP RESPONSE.
Tried with DWS at 10FS 100FS 1PS TSTEP
NGSPICE TMAX=1PS
Here the plot including DWS errors:
DWS and NGSPICE give DIFFERENT RESULTS with similar behaviors : the difference in VOUT is about 1V/45V
(2.2% relative error).
DWS errors relative to 10FS are about 200uV peak at 1PS and 20uV peak at 100FS.
DWS_100FS elapsed time=5.3sec
NGS_1PS : VOUT(500ns)=-44.9894V at NO TMAX, RELTOL=1E-6 VRTOL=1E-9 -44.9842V
RELTOL=1E-9 VRTOL=1E-9 : SIM ABORTED TIME STEP TOO SMALL
With DEFAULT TOLERANCES and NO TMAX VOUT(500ns)= -45.0264V
TMAX=100FS : SIM ABORTED (TIMEOUT?)
MC11 FIXED STEP: 100FS VOUT=-45.007V Elapsed time=63sec
1PS VOUT=-45.009V
LTSPICE (Alt SOLV) TMAX=100FS VOUT=-45.054V
TMAX=10FS VOUT=-45.046V Elapsed time:368sec
All spice version give approximately the same result.

DWS/MC11 speedup at 100FS=12X
NEW DISCOVERY:
DWS is affected by a voltage error on low capacitances (order of 10FF) charged at constant current that is
higher than Spice. See next post related to specific test circuit to pinpoint the issue. The error is probably due
to numerical reasons (reflection coefficient of very low caps related to very high impedance) and is near
independent with respect TSTEP.
Spice is also affected by a similar error but it is lower than DWS.
178MHz_QUARTZ_CRYSTAL_DWS_VS_NGS (3).jpg
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178MHz_QUARTZ_CRYSTAL_DWS_VS_NGS.jpg
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X
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AN_XTAL_TEST_I_SPICE_report.pdf
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TEST_XTAL_STEP_RESP_SPICE_report.pdf
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
Piero Belforte
2015-10-24
TEST_CAP_CURR_CHARGE
Test circuit to pinpoint voltage error at constant current charge for low cap values.
The theoretical value at 500ns for I=1e-6A is :Vc=500e-15/C where C is the capacitance in Farad.
C=10FF at 200ns DWS error: -22mV/20V=-1.1e-3
C=10FF at 500ns DWS error: -1.5V/50V=-3%
C=10FF at 500ns NGSPICE error= -2.4mV/50V=.048e-3
C=10FF at 500ns MC11 error= -2.5mV/50V
The error grows exponentially (due also to RC 10FFX10GIG time constant of 100us): C=10FF at 5uS NGSPICE
error is -25V/500V=-5%
DWS error is -125V/500V=-25% 5X NGSPICE ERROR
1PS_TEST_CAP_CURR_CHARGE_DWS_VS_NGSPICE_CMP.xls
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TEST_CAP_CURR_CHARGE_DWS_VS_NGSPICE_1PS.jpg
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TEST_CAP_CURR_CHARGE_report.pdf
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
Piero Belforte
2015-10-25
QUARTZ CRYSTAL VOLTAGE STEP RESPONSE.
Here the reports in SWAN and SPICE modes:
SWAN
https://www.ischematics.com/webspicy/report.py?RCODE=77684535521652004506as#.Vi0lVsnhDDc
SPICE
https://www.ischematics.com/webspicy/report.py?RCODE=18531585003780408164a#.Vi0l6cnhDDc
the results in the window 0-20ns are compared in this interactive plot:
After 20us from startup:
DWS, MC11 and LTSPICE results in the 0-200us window are compared
in the attached collage. The responses look different, the Q of the quartz crystal seems
lower for MC11 and LTSPICE (lowest Q, maximum attenuation of oscillations with time).

178MHZ_XTAL_STEP_RESPONSE_20US_CMP.jpg
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TEST_XTAL_STEP_RESP_report.pdf
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TEST_XTAL_STEP_RESP_SPICE_report.pdf
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
Piero Belforte
2015-10-26
178.561 Mhz FIFTH HARMONIC QUARTZ CRYSTAL, RESPONSE AT RESONANCE.
SWAN (DWS) version (TSTEP=1PS)
https://www.ischematics.com/webspicy/report.py?RCODE=00646384261013782368as#.Vi4FXcnhDDd
NGSPICE VERSION (TMAX=1PS)
The responses (DWS,NGS,MC11) on a 500ns window are compared here:
MC11 at fixed step and DWS are practicaly coincident. Peak difference is 600pV with peak out voltage of 10mV
(PEAK RELATIVE ERROR=1e-8) .NGSPICE is very close, a linear interpolation at fixed step would be required to
evaluate the differences.
On a window of 100us MC11 and DWS (10PS) have slighly different behaviors while LTSPICE gives a completely
different response. LTSPICE output voltage is about 1/8 the values given by DWS and MC11 30mV vs 240mV).
This confirms the "lossy" behavior of LTSPICE. (see attachments).
LTSPICE STANDS FOR LOSSY TRANSIENT SPICE!!
DWS elapsed time (100us window/10PS tstep)=13sec
MC11 elapsed time (100us window/10PS tstep)=192sec.
With default options (no TMAX) MC11 elapsed time is about 420sec.
LTSPICE elapsed time (100us window/10PS tstep, alt solv.1CPU) = 233.011 seconds.
DWS/MC11 speedup = 15X
DWS/LTSPICE speedup= 18X
Attached the comparison of responses at 3 frequencies (DWS 10PS) . 178.5Mhz is the nominal resonance
frequency of the 5th harmonic branch of the model calculated as 1/(2Pi*SQRT(LC)).

178MHZ_XTAL_STEP_RESPONSE_RESONANCE_1PS_500NS_CMP.jpg
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178MHZ_XTAL_STEP_RESPONSE_RESONANCE_100US_LTSPICE.jpg
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178MHZ_XTAL_STEP_RESPONSE_RESONANCE_100US_MC11_VS_DWS_10PS.jpg
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TEST_XTAL_RESONANCE_LTSPICE.cir
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1PS_500NS_TEST_XTAL_RESONANCE_DWS_MC11_NGSPICE_CMP.xls
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178MHZ_XTAL_SIN__RESPONSE_CMP_100US_DWS_10PS.jpg
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TEST_XTAL_RESONANCE_report.pdf
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TEST_XTAL_RESON_SPICE_report.pdf
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
Piero Belforte
2015-10-27
SWITCHED QUARTZ CRYSTALS
DWS TSTEP=10PS TSTOP=20US elapsed time: 11 sec
DWS TSTEP=2PS TSTOP=20US elapsed time: 30sec

LTSPICE (TMAX=2PS, TSTOP=20US Alt. solv.) Total elapsed time: 469.372 seconds.
The waveforms are similar but not equal. The overall behavior on 20us is more damped with LTSPICE as usual
(see ).
NGSPICE version:
The match between DWS (TSTEP=1PS) and ngspice (TMAX=10PS) is good in the window chosen (5-6us).
This confirms that LTSPICE result IS VERY INACCURATE.
Trying to set RELTOL and VNTOL to tighter value the sim abotrs while using TMAX the ngpsice sim runs.
See also the attachement.
MC11 DOESN'T WORK. the result is unaffected by the switches.
TEST_XTAL_SWITCHES.jpg
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1PS_20US_TEST_XTAL_SWITCHES2.g.csv
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TEST_XTAL_SWITCHES_LTSPICE.cir
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TEST_XTAL_SWITCHES_LTSPICE_VS_DWS_2PS.jpg
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TEST_XTAL_SWITCHES_LTSPICE_VS_DWS_2PS (2).jpg
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TEST_XTAL_SWITCHES_NGSPICE_10PS_VS_DWS_1PS .jpg
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TEST_XTAL_SWITCHES_NGSPICE_10PS_VS_DWS_1PS (4).jpg
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TEST_XTAL_SWITCHES_NGSPICE_10PS_VS_DWS_1PS (3).jpg
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TEST_XTAL_SWITCHES_report.pdf
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TEST_XTAL_SWITCHES_SPICE_report.pdf
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Piero Belforte
2015-10-28
SWITCHED QUARTZ CRYSTALS WITH CLAMP
Added an ideal pwl clamp (-1V 1V) at the output
Both LTSPICE and MC11 can't simulate this circuit due to the pwl element.
DWS version
https://www.ischematics.com/webspicy/report.py?RCODE=08243544351160756828as#.VjEkXGLhDDc
NGSPICE version:
https://www.ischematics.com/webspicy/report.py?RCODE=32128002100106615301a#.VjEk6GLhDDc
DWS vs NGSPICE COMPARISON:
DETAILED DWS vs NGSPICE COMPARISON:
DETAILED DWS ERROR EVALUATION:
The match between NGSPICE and DWS is VERY GOOD.
At 10PS DWS and NGS responses are already well matched and so happens between the responses at 2PS.
DWS peak error (with respect 200FS TSTEP)= 400uV at 10PS 10uV at 2PS (0.5V peak signal).
NGSPICE/DWS ERROR at TSTEP=TMAX=2PS:about 30uV peak
DWS elapsed time (TSTEP=10PS TSTOP=20usec)= 13.8 sec
On a 100us window with TSTEP=10PS DWS elapsed time is 26.3 sec.
Trying with local ngpsice 26, elapsed time will be in the order of 150min (still running)
STOPPED at 62.9% after about 2h 30min
Fatal error in NGSPICE ---------------------------
Ngspice Info realloc internal error cann't allocate abot 50 Mbytes.
Down to NGSPICE26 TMAX=100PS elaped time=290 sec The NGSPICE elapsed time increases EXPONENTIALLY
with time while DWS growth is LINEAR.
DWS/NGSPICE26 speedup= 22 at 100US/100PS

TEST_XTAL_SW_CLMP_SPICE_report.pdf
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SWITCHED_XTALS_CLAMP_NGSPICE_VS_DWS.jpg
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SWITCHED_XTALS_CLAMP_NGSPICE26_100PS_100US.jpg
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TEST_XTAL_SW_CLAMP_report.pdf
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Piero Belforte
2015-10-28
4 X SWITCHED QUARTZ CRYSTALS WITH CLAMP
DWS version:
https://www.ischematics.com/webspicy/report.py?RCODE=32880185410632646813as#.VjEC9WLhDDd
NGSPICE version
https://www.ischematics.com/webspicy/report.py?RCODE=83682836425075887531a#.VjE9oWLhDDc
The ngspice result is affected by a DIFFERENCE among VOUTs. Increasing the simulation window
the sim stops due to TIME STEP TOO SMALL.
DWS elapsed time (TSTOP=5.1us TSTEP=10PS): 12 sec.
4XSWITCHED_XTALS_CLAMP_DWS.jpg
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4XSWITCHED_XTALS_CLAMP_NGSPICE_ERROR (2).jpg
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TEST_XTAL_SW_CLAMP_X4_DWS_report.pdf
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TEST_XTAL_SW_CLAMP_X4_DWS_report.pdf
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TEST_XTAL_SW_CLAMP_X4_report.pdf
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Piero Belforte
2015-10-29
Back to SWITCHED QUARTZ CRYSTALS WITH CLAMP
Compared DWS and ngspice on the 98us-100us window.
To get relatively quick sims from ngpsice a TMAX= 1NS has been chosen.
Here the comparison of NGSPICE_1NS vs DWS_100PS and DWS_1NS.
The responses look VERY DIFFERENT: 1NS choice of TSTEP or TMAX is not suitable to get accurate results. Even
the difference between DWS_1NS and DWS_100PS is too big in this time window. At 100PS DWS and NGSPICE
look well matched (98-100us).
This confirms the need to work at small tsteps or tmax (or tighter tolerances) to get enough accurate results at
these time scales. Ngspice requires LONG SIM TIMES to get accurate results while DWS can still perform well
thanks to its SPEED ADVANTAGE. Growth of NGSPICE sim time is EXPONENTIAL while for DWS is LINEAR. At
high values of TSTOP/TMAX (eg. 1ms/100ps or 100us/10ps the ngspice sim stops after hours due to FATAL
ERROR ( realloc internal error).
SWITCHED_XTALS_CLAMP_NGSPICE_VS_DWS_100US (2).jpg
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SWITCHED_XTALS_CLAMP_NGSPICE_VS_DWS_100US_DETAIL (2).jpg
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SWITCHED_XTALS_CLAMP100US_DWS_1PS_VS_NGS26_100PS.jpg
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
Piero Belforte
2015-10-29
Next TestCircuit: PERIODICALLY SWITCHED CAPACITOR CHAIN:
DWS version:
https://www.ischematics.com/webspicy/report.py?RCODE=48717241523204222826as#.VjZcJWLhDDd
The ideal switches have a default RON=1/GMAX= 1E-6 and default ROFF=1/GMIN=1E9.
To get a corrrect behavior of this circuit using DWS, TSTEP has to be equal or lower than 2PS.
Using a larger TSTEP causes a WRONG response due to cap charging currents that can show an oscillatory
behavior due to TRAP metod used by DWS.The DWS responses at TSTEP larger than 2ps become oscillatory
with period corresponding to swirtch control period.. The persistence of oscillations depends on switch RON.
Charge is conserved even in this ANOMALOUS response and slow discharging depends on switches RON that
can be set as low as 1E-20 ohm Using GMAX=1E20.
The behavior of cap currents for the right non-oscillatory reponse has been monitored using the following
circuit:
The response at TSTEP=1PS is show here:
The error of cap voltages with respect the theoretical values is lower than 100nV after about 6 ns
from the switching time.
Capacitor currents at different TSTEP (10FS,100FS,1PS) are compared here:
At lower TSTEP charge current peaks get lower.
DWS elapsed time at TSTEP= 1PS, TSTOP=100ns is 0.6sec.
6_SWITCH_CAP_CHAIN_DWS_1PS_DETAIL.jpg
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TEST_SW_CAPS_report.pdf
X
TEST_SW_CAPS_CURRENT_report.pdf
X

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marcel hendrix
2015-11-02
Hi Piero,
I'm still very busy, but here is a circuit to try to handle with a fixed step solver. In NGSPICE there
is no way to force a fixed step, as even method=TRAP with MAXORD=1 (backward Euler) will examine and
act on the estimated truncation error.
Only the part after T=1us is interesting to me. The target accuracy is 0.1% and the run time is important. Do
not change the .TRAN line for SPICE.
-marcel
PS: NGSPICE online cannot run the circuit -- the latest
git version is recommended.
.TITLE piero I
C1 out 0 {tau} ic={k}
R1 out N001 1
V1 in N001 0
B1 in 0 V=1-exp(-time)
B2 golden 0 V=1-exp(-time)+{k}*exp(-time/{tau})
B3 0 out I=I(Vsense)
C2 in N002 {tau} ic=0
Vsense N002 0 0
.tran 1n 5 1u uic
.options reltol=1m method=gear
.param tau=1ns k=2
.ic V(out)={k}
.control
run
plot v(out) v(golden) (v(golden)-v(out))/v(golden)
quit
.endc
.end


Piero Belforte
2015-11-03
Hi Marcel,
I tried to build up a simplified version of your circuit. The exp function is not included in DWS syntax, so I
used a simplified 3-point pwl for element B1. A more accurate FILE description of B1 behavior can be used
instead of the pwl. Please check if I interpreted correctly your circuit (the golden reference is not
included):https://www.ischematics.com/webspicy/report.py?RCODE=86087467334225186745as#newwin

TEST_PIERO_report.pdf
X


Piero Belforte
2015-10-30
Deleted post for corrections. See next posts.
o

Piero Belforte
2015-10-30
Deleted post for corrections. See next posts.

Piero Belforte
2015-11-03
Resuming the DWS vs Spice comparison for this test circuit:
https://www.ischematics.com/webspicy/report.py?RCODE=48717241523204222826as#.VjjNwGLhDDe
Unfortunately the DWS syntax of control generators:
PULSE(0 1V 10ns 0ns 0ns 110ns 200ns)
is NOT valid for Spice due to 0 values for trise and tfall, and so the use of this syntax has led to several mistakes
in result interpretation.
Correcting the syntax into:
PULSE(0 1V 10ns 1fs 1fs 110ns 200ns)
equivalent test circuit are obtained as Spice versions.
A first example is shown here:
The sim seems working up to about 1us reaching an APPARENT STEADY STATE . then the cap voltages becomes
oscillatory, in a way similar to that experimented with DWS for TSTEP>2ps.
The previously shown result applies for NGSPICE25 (Spicy SWAN) with DEFAULT options and NO TMAX
specified.
Specifying TMAX=1PS the oscillations are less visible but a true steady state is not obtained. The sustained
oscillatory behavior will probably happen at a larger time. The capacitor current is also shown.See attached
plots.
Tried to run on local NGSPICE26, SIM DOESN'T RUN due to SINGULAR MATRIX error.
LTSPICE (ALT. SOLVER, MOD.TRAP) with TMAX=10PS is more stable than ngspice, the fluctuations of steady
state are very low .Total elapsed time: 40.207 seconds. (10us).
It works even without TMAX setting and is faster Total elapsed time: 1.656 seconds.
. Using the NOM solver the steady state is NOT REACHED and the sim slows down suddenly at about 4.9us
(340ps/sec), see attached plot.

TEST_SW_CAPS2_SPICE_APPARENT_STEADY_STATE_TMAX=10PS.jpg
X
TEST_SW_CAPS2_SPICE_APPARENT_CAP_CURRENT_TMAX=10PS.jpg
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TEST_SW_CAPS2_SPICE_LTSPICE_NORMAL_SOLVER.jpg
X
TEST_SW_CAPS2_SPICE.cir
X
TEST_SW_CAPS_report.pdf
X
TEST_SW_CAPS2_SPICE_report.pdf
X

Piero Belforte
2015-11-04
Replacing C3 with a 100 nh inductor (L3) in the switched capacitor chain. Staircase charge of capacitors.
DWS version:
https://www.ischematics.com/webspicy/report.py?RCODE=08037754376534828572as#.VjnzsmLhDDc
After the initial transient the behavior of cap waveforms becomes periodic due to the effect of switched
inductor.
As usual the capacitor currents behaviors strongly depends on TSTEP choice as also happens for the L3 voltage.
Capcitor voltages are less influenced by TSTEP choice from 1PS down to 100FS or less.
The comparison of DWS responses at TSTEP=1PS and 100FS are plotted here:
The absolute error (1PS vs 100FS) is about 400uV peak.
Both absolute and relative error are plotted here:
Here the comparison of currents of capacitor C is shown with all cap waveforms at TSTEP=100FS:

TEST_SW_CAP_L_SWAN_report.pdf
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
Piero Belforte
2015-11-04
Replacing C3 with a 100 nh inductor (L3) in the switched capacitor chain. Staircase charge of capacitors.
NGSPICE25 version:
https://www.ischematics.com/webspicy/report.py?RCODE=18400550803181347013a#.VjoczmLhDDc
The simulation becomes UNSTABLE after about 1.2us from the startup, and it seems there is no way to make it
stable.
Here the comparison between the DWS reference at TSTEP=100FS and ngspice25 results:
SWITCHED_CAPACITOR_WITH_INDUCTOR_NGSPICE_INSTABILTY_VS_DWS.jpg
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TEST_SW_CAP_L_SPICE_report.pdf
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marcel hendrix
2015-11-04
Hi Piero,
Doesn't look so bad here.
What's that super-HF inductor resonance doing there?
-marcel
sccchain.png
Reply
Link

Attach


Piero Belforte
2015-11-04
Hi Marcel,
are you able to simulate beyond 1.2us?

marcel hendrix
2015-11-04
are you able to simulate beyond 1.2us?
See attached.
sccchain.png


Piero Belforte
2015-11-05
Why I can't ? Ngspice25 (Spicy SWAN) gets unstable beyond 1.2 us (see previous posts) and local nspice 26
doesn't run (matrix is singular).

marcel hendrix
2015-11-05
This runs online, but doesn't plot.
* SCC chain
C0 N_C 0 1n IC=1V
V0 UN_3 0 dc=0 PULSE(0 1V 10ns 1ns 1ns 110ns 200ns)

X0 UN_9 N_C1 UN_3 SW_NO2
C1 N_C1 0 1n IC=3V
X1 N_C1 N_C2 UN_4 SW_NO2
C2 N_C2 0 1n IC=5V
X2 N_C2 N_L3 UN_5 SW_NO2
X3 N_L3 N_C4 UN_6 SW_NO2
C4 N_C4 0 1n IC=9V
C5 N_C5 0 1n IC=11V
C6 N_C6 0 1n IC=13V
L3 N_L3 0 100n ic=0
V_C UN_9 N_C 0
.subckt sw_no2 in out ctr
S_NO in out ctr 0 switch_no
.model switch_no SW(Ron=1m Roff=10MEG Vt=0.5 Vh=-0.45 )
.ends sw_no2
.options reltol=1m method=gear
.TRAN 1n 5u uic
.end

marcel hendrix
2015-11-05
I specified to plot V(n_c3) which doesn't exist. This causes ngspice to not plot anything.
With correction - see attached.
scc.png

Piero Belforte
2015-11-05
I understand...to make it run you decreased the dynamics of switch resistance to Ron=1m Roff=10MEG and
increased the risetime of switch control voltages from 1fs to 1ns.
These are all critical factors for spice (even LTSPICE, see attachment) but not for DWS.

LTSPICE doesn't show the numerical instability as ngpsice does, but the simulation run suddendly slows down
to ps/sec. The time of this freezing up depends on chosen option.
TEST_SW_CAP_L_STAIRCASE_LTSPICE.jpg
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TEST_SW_CAP_L_SPICE_LTSPICE.cir
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
Piero Belforte
2015-11-05
Increasing the size of switched caps test circuit (DWS versions):
10 equal cells (without L3), staircase charge:
https://www.ischematics.com/webspicy/report.py?RCODE=31635145215654028678as#.VjsozlThDDc
10 mixed cells
https://www.ischematics.com/webspicy/report.py?RCODE=25076446761564873723as#.Vjsnn1ThDDc
10 mixed cells with randomly connected reactive parts including coupled inductors:
50 mixed cells:
https://www.ischematics.com/webspicy/report.py?RCODE=54620011680415517640as#.VjsoF1ThDDc
TEST_SW_CAP_ARR_SWAN_report.pdf
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TEST_SW_CAP_L_ARR_SWAN_report.pdf
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SW_CAP_ARRAY_COUPL2_report.pdf
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TEST_SW_CAP_ARR_SWAN_report_2.pdf
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
Piero Belforte
2015-11-05
Here the netlists of multiple switched cap cells spice versions.
I was unable to run ngspice with them.
LTSPICE runs but shows the simulation freezing up afters a few tens of ns.

To make them run the Marcel modifications on switch model (LESS IDEAL SWITCH) and slowing down of
Vcontrol risetime will be required (but the circuit will be not the same of DWS).
TEST_SW_CAP_ARRAY_LTSPICE.cir
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TEST_SW_CAP_ARR50_LTSPICE.cir
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TEST_10_CELL_SWITCHED_CAPS_ARRAY_LTSPICE_FREEZING_UP.jpg
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Reply
Link
Edit
Attach
o
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marcel hendrix
2015-11-05
To make them run the Marcel modifications on switch model (LESS IDEAL SWITCH) and slowing down of
Vcontrol risetime will be required (but the circuit will be not the same of DWS).
Let's turn this around a bit: show what DWS makes of these simulations with Vcontrol slowed down from
1 fs to 3.333 ns.
Or: show these simulations with
V0 UN_3 0 PULSE(0 1V 10.31459ns 4ns 4ns 110ns 200ns)
Or: show these simulations with exponential rise-time
control voltages.
Like discussed before, state what accuracy you want to get from the simulation, and mention the
simulation times you got. To my liking would be 0.01% and below a few seconds.
-marcel


Piero Belforte
2015-11-05


Marcel,
here the DWS result with the control setting you proposed:
At TSTEP=1PS the sim elapsed time is 10.5 sec. The accuracy is in the order of 100uV.
For DWS the Vcontrol risetime has no effect (except a delay) because the switches change state at the .5V
crossing of the control voltage. The effect on Spice result (stability) should be explained.
The true problem for this circuit is the accuracy of cap charging currents and the energy loss due to
switches that is well visible on a time scale in the order of tens of microseconds.
TEST_SW_CAPS_L_MARCEL_SETTINGS_DETAIL.jpg
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1PS_2US_TEST_SW_CAP_MARCEL.csv
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TEST_SW_CAP_MARCEL_report.pdf
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
marcel hendrix
2015-11-06
The true problem for this circuit is the accuracy of cap charging currents and the charge loss due to RON of
switches that is visible on a time scale in the order of tens of microseconds.
As we all know, without a load resistor the only losses are by redistribution of charge. These are independent
of switch on resistance, unless it is so large that the charge can not redistribute during the on-time
of the switch. Famous example: parallel two ideal equal capacitors
(one +10V, the other empty) through an ideal switch. After the switching event the capacitors are both +5V.
Where did the energy (0.5CV^2 -> 20.5C*(V/2)^2) go? In SPICE you must define some resistance
to make this work, without it we get to complicated and not (yet) very practical
piece-wise affine stuff (Siconos etc.)
o
o
Piero Belforte
2015-11-06
Yes,
even if the question is: where the energy dissipated by the switch has gone? I built up this simple DWS
circuit to evaluate the power dissipated inside the
switch: https://www.ischematics.com/webspicy/report.py?RCODE=65533433666384411263as#newwin T
he RON is 1milliohm.

Looking at the plot https://plot.ly/~piero.belforte/6449.embed
TEST_TWO_CAPS_CHARGE.jpg
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TEST_TWO_CAPS_CHARGE_report.pdf
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
marcel hendrix
2015-11-06
Try this in LTspice (to stay on neutral ground).
For all resistances between 1n and 1Ohm the energy dissipated in the switch is 25 J.
In the limit for R goes to zero, the E_dissipated must stay 25J (+/- simulation accuracy).
-marcel
cswitch.png
E_cswitch.png
o
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Piero Belforte
2015-11-06
Yes,
you are right , the charge is conserved but there is a loss of energy due to charge redistribution. and this loss
is independent on switch resistance. In my case the initial energy stored in C0 (1V,1nF) is 500 pJ and so the
energy dissipated in the switch is 250pJ.



Piero Belforte
2015-11-07
To better clarify how the power is dissipated by the switches I created the following test circuit:
A pre-charged capacitor is periodically connected to an inductor by means of a switch implemented as a DWS
time-controlled resistor (PULSE). Two circuits are compared with different switch RON (1 Milliohm and
1microohm). The I/O powers of the two switches are monitored and compared. The power dissipated within
the switches is obtained as sum of I/O incident powers.
To get a right response the circuit must be simulated with very short TSTEPS in the order of 10FS or less,
otherwise the response is completely wrong. At 10FS TSTEP for a window of 200NS the DWS elapsed time is
26sec.
In the following plots the results:
Panoramic view of capacitor voltages decay and I/O switch powers:
Detailed view of power peak dissipated by the switches:
Also in this case the power is practically independent with respect the switch RON.
LC_SWITCHED_OCILLATOR_POWER_DISSIPATION.jpg
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TEST_LC_SWITCH_report.pdf
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
marcel hendrix
2015-11-07
Also in this case the power is practically independent with respect the switch RON.
I guess that in this case you are interrupting the inductor current, i.e. trying to destroy flux. The energy decay
should be related to 0.5LI_turnoff^2, which is probably much larger than the RMS loss in the series resistance.
If you increase the resistor values a few orders, there should be loss differences per cycle for different
resistance values.

o
Piero Belforte
2015-11-07
Yes, the difference is pointed out by this plot:


Piero Belforte
2015-11-07
Tried previous circuit Spice version.
Both ngspice26 and LTPICE seem FASTER than DWS at 10FS. The LTSPICE result looks different with respect
previous DWS result (see ttachement).
This is due to the different implementations of switches that changes the ON/OFF timing.
A SPICE equivalent SWAN version using a THR model of the switch Spice is here:
The VC decay is now similar to LTSPICE result.
NGSPICE26 Local version (TMAX=1PS, elapsed time 12 sec) is about 2X faster than DWS (DWS elapsed
time=26sec) at 20FS on a 200ns window.
LTSPICE required about 10 sec with TMAX=1PS and with ALT. SOLVER.
LTSPICE VC decay seems still faster than DWS (about .6mV last VC step vs about 5.4mV odf DWS 10FS and 1FS).
LC_SWITCHED_OSCILLATOR_LTSPICE.jpg
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TEST_LC_SWITCH_SPICE.cir
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TEST_LC_SWITCH_SWAN_report.pdf
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
Piero Belforte
2015-11-07
Here a more accurate DWS NGSPICE comparison.
Ngpsice25 version TMAX=50FS

DWS version TSTEP=10FS
https://www.ischematics.com/webspicy/report.py?RCODE=35320806211310524626as#.Vj5a61ThDDc
After several trials TMAX=50FS resulted the best speed/accuracy tradeoff for ngspice25 (Spicy SWAN). The
response is strongly affected TMAX choice. TOL setting is not as good as TMAX to get an accurate (similar to
DWS 10FS) response and below RTOL=1e-6 the sim aborts.
Local Ngspice26 gives similar results with TMAX=100FS and TMAX=10FS. The elapsed times are 46sec and
292sec respectively. DWS_10FS /ngpsice26 speedup is 1.7X and 11.2X respectively. Even ngspice26 aborts the
sim below RELTOL=1e-6 VTOL=1e-9.
DWS_10FS and ngspice25 results looks similar confirming that LTSPICE is TOO LOSSY (as usual).
Here the DWS_10FS vs Ngspice25_50FS comparative plot:
https://plot.ly/~piero.belforte/6533.embed NGSPICE/DWS VC relative error is in the order of +6% at 200ns,
the NGSPICE decay is lower than DWS (the opposite of LTSPICE where the difference is in the order of 50%).
MC11 needs a different switch model specifying VON and VOFF, At fixed step TMAX has to be 10FS otherwise
the result is wrong,VC decay is faster than DWS/NGSPICE (more lossy) but slower than LTSPICE (see
attachment). MC11 elapsed time is about 22min (DWS/MC11 speedup=50X). At variable step TMAX has to be
set to 1PS to get about the same result but with 15 sec elapsed time (faster than DWS).
LC_SWITCHED_OSCILLATOR_NGSPICE26_10FS.jpg
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LC_SWITCHED_OSCILLATOR_NGSPICE25_VS_DWS.jpg
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LC_SWITCHED_OSCILLATOR_MC11_10FS.jpg
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TEST_LC_SWITCH_SPICE2_report.pdf
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TEST_LC_SWITCH_SWAN_report.pdf
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
Piero Belforte
2015-11-08

ADDING AN IDEAL +-.5V CLAMP to the INDUCTOR of previous switched oscillator test circuit.
This circuit is affordable only by DWS and NGSPICE.
DWS version:
https://www.ischematics.com/webspicy/report.py?RCODE=05474657061367723652as#.Vj-JElThDDf
NGSPICE25 version:
Local ngpsice26 ABORTS the simulation (gmin stepping failed).
As happened in the previous circuit, the ngpsice25 is STRONGLY DEPENDENT on TMAX, the correct results is
obtained under TMAX=10FS. Due to server time limitation only the first 2ns are simulated down to TMAX=5FS.
The comparative plots reporting NGS_5FS, DWS_5FS and DWS_1FS (reference) results is available here:
The behaviors look very well matched.
The I(L0) current error at 262ps is less than 1nA/50mA for DWS_5FS and about -30nA/50mA (-.6e-6 relative
error) for NGS_5FS/DWS_1FS. Obviously DWS run faster than NGspice, not able to estimate ngspice on my pc
due to ngspice26 failure. The DWS speedup with TSTEP=TMAX should be in the order of 10-50.
LC_SWITCHED_OSCILLATOR_WITH_CLAMP_DWS_VS_NGSPICE25.jpg
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TEST_LC_SWITCH_SPICE_CLP_report.pdf
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TEST_LC_SWITCH_SWAN_CLP_report.pdf
X
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
Piero Belforte
2015-11-08
GENERAL CONSIDERATIONS
Analyzing the results coming from previous LC SWITCHED CIRCUITS it seems that ONLY DWS and NGSPICE are
able to give accurate results. Due to very low TSTEP or TMAX (FS range) required to get accurate results from
both simulators, DWS is FASTER especially on large time scales and/or complex circuits.
LTSPICE is able to deal with these circuits at a good speed even in the case of 50 cells (can be faster than DWS),
but the result is affected by an EXCESSIVE LOSS and the simulation error is TOO LARGE. A similar result (even if
with with less simulator losses) applies for MC11 that shows a good speed if used at VARIABLE step with TMAX
limitation in the order of 1PS or less (as happens for LTSPICE too). MC11 and LTSPICE can be even FASTER than
DWS (and NGSPICE) but the RESULTS can be INACCURATE especially with time scales in the order of several
microseconds.
o


Piero Belforte
2015-11-10
WHERE THE ENERGY HAS GONE?
To answer this question I created an ENERGY METER to monitor by simulation the energy behavior of a circuit.
Here an application example (from previous post) related to energy dispersion due to chargr redistribution:
https://www.ischematics.com/webspicy/report.py?RCODE=71025785405806326672as#.VkHkvFThDDd
In this way it is possible to monitor both POWERS and ENERGIES (excluding static energy that can be added as
integration constant).
Here the plot showing how the energy is dissipated by the switch and resistributed:
The application is quite general, here the case of lossy switch (RON=1ohm) with indusctance (.5nH):
DWS_ENERGY_METER.jpg
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TWO_CAPS_SWITCH_DISCHARGE_ENERGY_AND_POWER.jpg
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TEST_TWO_CAPS_ENERGY_report.pdf
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TEST_TWO_CAPS_EN_2_repor.pdf
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
Piero Belforte
2015-11-10
POWER AND ENERGY BY DWS SIMULATION
Here a more complete DWS meter for energy and power monitoring during the simulation run (see
attachement).

Total capacitor (C0 + C1)energy after the switch off (20ps) from the previous plot = 125pJ+ 375pJ = 500pJ vs
theoretical 500pJ (.5CV*C) : ERROR = 0pJ.
DISSIPATED POWER on THE SWITCH =249.2522 pJ vs 250pJ thoeretical: ERROR=.7478pJ (relative error=-3e-3).
https://www.researchgate.net/publication/283659327_CAPACITOR_CHARGE_REDISTRIBUTION_BY_SWITCHIN
G_DIGITAL_WAVE_SIMULATION_%28DWS%29_OF_POWER_AND_ENERGY_BEHAVIORS
DWS_ENERGY_AND_POWER_METER (2).jpg
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TWO_CAPS_SWITCH_DISCHARGE_ENERGY_AND_POWERS_BY_SIMULATION.jpg
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TEST_TWO_CAPS_EN_POW_report.pdf
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
Piero Belforte
2015-11-11
SWITCHED LC OSCILLATOR: ENERGY AND POWER DISSIPATION WITHIN THE SWITCH
The dissipated energy behavior difference between the 1milliohm and 1uohm RON version of the switch is
negligible. After 200ns 4.99982 PJ of energy of the 5PJ initial energy of the 10pF capacitor have been
dissipated by the switch after about 120 switchings.
TEST_LC_SWITCH_SWAN2.pdf
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
Piero Belforte
2015-11-12

A SLOWER DWS SWITCH FOR FASTER SIMULATIONS OF LOW ACTIVITY REACTIVE SWITCHED CIRCUITS.
Previous test circuits using instantaneous response switches for reactive load switching often require very
small time steps in the sub-picosecond range to get accurate simulation results. Despite DWS speed advantage
with respect Spice, this requirement slows down the simulation working at fixed steps as DWS does. This effect
has been well experienced on MC11 that allows the user to run the simulation both at fixed or variable step.
The variable step sim is faster than fixed step without loosing accuracy. This effect is evident dealing with LOW
ACTIVITY circuits like capacitor charge switching. For this reason a slower DWS switch has been developed and
compared to the faster model and to Spice simulations.
This switch has been created using the Voltage controlled resistor primitive of DWS (see attacment).
All DWS controlled elements of DWS include a control chain allowing the user to specify a DELAY, a DYNAMIC
TRANSFER FUNCTION, and a STATIC TRANSFER FUNCTION. In particular the dynamic transfer function can be
defined in the s-plane, in the z-plane or directly in time domain.
A pwl representation of dynamic transfer function is very suitable to slow down the response of the switch by
defining a two-points (slew rate) STEP RESPONSE in time domain. This block is computationally very efficient
due to FAST CONVOLUTION adopted in case of pwl behavior. The static block is used to describe in pwl form
the behavior of switch resistance. Instead of an abrupt transition between the on off states as happens with a
threshold (or hysteresis) of the ideal switch , a more smoothed transition can be defined even in pwl format. A
100ps slew rate has been chosen as a good tradeoff: RSW 1 2 3 0 PWL(-1V 10GIG 0V 10GIG .1V .1GIG .2V
.1MEG .3V 10K .4V 1K .5V 100 .6V 10 .7V 1 .8V .1 .9V 10M 1V 1M 2V 1M ) S(T)=PWL(0PS 0 100PS 1)
https://www.researchgate.net/publication/272576412_DWS_8.5_USER_MANUAL
DWS_VC_RESISTOR.jpg
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DWS_8.5_manual_REV_12012015 .pdf
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
Piero Belforte
2015-11-12
THREE-CAPACITOR SWITCHED CIRCUIT.
In this test circuit TWO EQUAL PRECHARGED CAPACITORS ARE CONNECTED IN SERIES BY SWITCHES AND THEN
CONNECTED TO AN UNCHARGED C/2 CAPACITOR.
The theoretical response is known and can be compared to simulation result.
Here the first DWS version using INSTANTANEOUS SWITCHES:
The right result ( Cap voltage error =0V) is obtained using a TSTEP<=1PS. At higher values of TSTEP the result
shows an error in the steady state portion due to periodic switching of the switch X2.
DWS elapsed time is 300 msec(100NS window, TSTEP=1PS).
Here the DWS version using the 100ps slew rate switches:
In this case the simulation still gives correct results using a TSTEP=10PS and with a small integration error up to
TSTEP=50PS. In this way a DWS speedup of 10-50X is gained with respect the version using the instantaneus
switches.
DWS elapsed time is about 30msec at TSTEP=10PS and 6msec at TSTEP=50PS.

Obvious result differences are due to the risetime of capacitors voltage steps, while the steady state responses
are practically coincident.
Here the Ngspice25 version of the same circuit:
The result is similar to DWS EXCEPT THE VALUE of V(C1) before 10ns (1.333V instead of 1V that is the RIGHT
value). This ERROR is put in evidence in yellow in the attachment.
Here the comparative plot:
Here the comparative plot between DWS instantaneous switch at TSTEP=1PS and NGSPICE25 NO TMAX:
In addition to previously pointed out error of NGSPICE, there are some aberrations in VC1 and VC2 waveforms
between 20 and 40ns. (see attachement). These aberrations disappear setting TMAX=1PS.
Here the comparison between NGSPICE25 TMAX=1PS and DWS TSTEP=1PS
Local ngspice26 fails (Singular matrix, source stepping failed).
LTSPICE and MC11 results are similar to ngspice25 result with the issue related to VC1=1.33V
before 10ns instead of 1V. Also the aberrations between 30 and 40ns are present.
On LTSPICE the 30-40ns aberrations disappear setting TMAX=1PS (ALT. SOLVER). The elapsed time is 4.356
seconds (about 7X with respect DWS using instantaneous switches and TSTEP=1PS and 70X with the 100ps
slew rate switches).
Using MC11 the 20-30ns aberrations fully disappear with TMAX=100FS (elapsed time=27sec).
TEST_NET_CAP_SWITCH2.pdf
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TEST_NET_CAP_SW_TF2.pdf
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TEST_NET_CAP_SW_TF2_DWS_TSTEP=50PS.jpg
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TEST_NET_CAP_SW_SPICE.pdf
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TEST_NET_CAP_SW_SPICE_2LTSPICE.cir
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TEST_NET_CAP_SW_TF2_DWS_TSTEP=1PS_VS_NGSPICE_ERROR.jpg
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TEST_NET_CAP_SW2_DWS_TSTEP=1PS_VS_NGSPICE_ERROR.jpg
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TEST_NET_CAP_SW_SPICE_report.pdf
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TEST_NET_CAP_SW_TF2_report.pdf
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TEST_NET_CAP_SWITCH2_report.pdf
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Piero Belforte
2015-11-26
https://plus.google.com/photos/photo/118285010585894969594/6190712616452690818

DWS VS. SPICE COMPARISONS FROM NGSPICE USERS FORUM DISCUSSION " SPICE- DWS INTEGRATION"

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