20181015 m3 l-kojioyama_vsf-october-meeting_presentation_v100
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We M3L believe that the clock recovery technology on a receiving side is one of the most important factors when transmitting broadcast-quality signals with ST 2110 or ST 2022 according to decades of our Video-over-IP design experience. In particular, the quality of a recovering clock in ST 2059 Slave module represents how much reliability the data transmission paths have for the next-coming 4K/UHD uncompressed videos via ST 2110 over 25-GbE. We obtained some data which indicates the effect on the quality of the receiving video signals with various parameters such as PTP Sync Interval, network loadability, and number of IP switches. These data will be very helpful for broadcasting engineers when building broadcasting networks for IP production in the future. Our presentation shows you some data compared with the one on 10-GbE so that we can consider how each parameter affects the jitter of reproduced SDI signals on the receiving side.
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20181015 m3 l-kojioyama_vsf-october-meeting_presentation_v100
- 1. © 2018 M3L Inc. Effect on Reproduced SDI Signal Quality by Various Parameters on ST 2110 over 25 GbE Network October 2018 VSF Meeting Series Koji Oyama, M3L Inc.
- 2. 2 © 2018 M3L Inc. I. Introduction – 1. Concerns, 2. Objective II. Evaluation Environment – 3. Connections, 4. Parameters III. Results – 5. 12G-SDI over 25GbE wo/L2 switch, 6. 12G/25GbE vs 3G/10GbE – 7. 12G-SDI over 25GbE w/L2 switches, 8. 12G/25GbE vs 3G/10GbE – 9. Separated PTP channel – 10. Lock time example IV. Conclusion Agenda
- 3. 3 © 2018 M3L Inc. • Decrease motivation to shift to ST 2110 based system – Some customers: the same quality with the current SDI-based system • New features without degradation • They understood its benefit but don’t know how to use it well yet • Ideally seamless transition required • Confusion could be negative factor – New skill for ST 2110 network design and parameter settings • Which parameters ? How much of degrees ? 1. Our Concerns
- 4. 4 © 2018 M3L Inc. • Correct understanding of Parameters and their influence – Never reproduce completely the same SDI signal unfortunately – But it can be as same as its possible by setting the adequate parameters • Our data would be some hint when you want to improve it – You could be in trouble in the near future if you don’t know it well 2. Objective for our Evaluation Packetize & Transport Similar … Signal Quality (meet in spec) How much different ? → Depends on your parameter settings Same … Image Quality Original Reproduction Just in Time (min inventory) Time Synch Lower Latency
- 5. 5 © 2018 M3L Inc. 3. Evaluation Environment (Basic Setups) 10/25G L2 SW Mellanox SN2070 10/25G L2 SW Arista Networks 7280SR2A SG / PTP Grandmaster LEADER LT4610 SFP28 /SFP+ M3L 2110 Ingress Core Xilinx FPGA M3L 2059 Slave Core SFP28 /SFP+ Xilinx FPGA M3L 2110 Egress Core M3L 2059 Slave Core FPGA Eva Board Xilinx KU116 FPGA Eva Board Xilinx KU116 Embrionix 3G/12G-SDI SFP Module 10GbE 10/25GbE 3G-SDI (1080/59.94p) /12G-SD I(2160/59.94p) BB Analysis / Monitor Phabrix Qx12G 3G-SDI /12G-SDI 10/25GbE 10/25GbE
- 6. 6 © 2018 M3L Inc. • Parameters – PTP Interval (portDS.logSyncInterval) : n=[-1, -2, down to -7] (2n sec) – Ethernet media : 25GbE, 10GbE – SDI media : 12G-SDI(2160/59.94p), 3G-SDI(1080/59.94p) – Number of cascaded L2 switches : m=[0, 1, 2] – Network load : PTP_Only, Muxed-PTP_with-ST2110 • Results – Timing Jitter of a reproduced SDI signal (UI) – Phase Sync with BB/source signal (Pixels) → Wander – Lock time (sec) → still under evaluation 4. Evaluation Parameters and Results
- 7. 7 © 2018 M3L Inc. • Jitter and Wander – http://users.rcn.com/wpacino/jitwtutr/jitwtutr.htm – “the short-term (jitter) and the long-term (wander) variations of the significant instants of a digital signal from their ideal positions in time” 4. Evaluation Parameters and Results The figures are quoted from the site above.
- 8. 8 © 2018 M3L Inc. • No L2 SW on 25GbE network • Multiplexed PTP w/ ST-2110 • Best for M3L IP cores • Unrealistic use case 5. 12G-SDI over 25GbE wo/L2 switch SG / PTP Grandmaster LEADER LT4610 SFP28 M3L 2110 Ingress Core Xilinx FPGA M3L 2059 Slave Core SFP28 Xilinx FPGA M3L 2110 Egress Core M3L 2059 Master Core FPGA Eva Board Xilinx KU116 FPGA Eva Board Xilinx KU116 Embrionix 12G-SDI SFP Module 25GbE 12G-SD I(2160/59.94p) BB Analysis / Monitor Phabrix Qx12G 12G-SDI
- 9. 9 © 2018 M3L Inc. 5. 12G-SDI over 25GbE wo/L2 switch • Evaluation Results
- 10. 10 © 2018 M3L Inc. • PTP Interval has no effect on Jitter or Wander • Timing Jitter 0.4 – 1.0UI 5. 12G-SDI over 25GbE wo/L2 switch Timing Jitter (12G-SDI Spec: <= 2.0UI) Wander Sampling Rate: 1sec Sampling Rate: 1sec
- 11. 11 © 2018 M3L Inc. • Similar to 25GbE env – 3G-SDI over 10GbE wo/L2 SW – Multiplexed PTP w/ ST-2110 6. 12G-SDI/25GbE vs 3G-SDI/10GbE wo/SW SG / PTP Grandmaster LEADER LT4610 SFP+ M3L 2110 Ingress Core Xilinx FPGA M3L 2059 Slave Core SFP+ Xilinx FPGA M3L 2110 Egress Core M3L 2059 Master Core FPGA Eva Board Xilinx KU116 FPGA Eva Board Xilinx KU116 Embrionix 12G-SDI SFP Module 10GbE 3G-SD I(1080/59.94p) BB Analysis / Monitor Phabrix Qx12G 3G-SDI
- 12. 12 © 2018 M3L Inc. • 3G x4 Timing Jitter – Similar absolute value • Almost the same wander • No difference among PTP Intervals 6. 12G-SDI/25GbE vs 3G-SDI/10GbE wo/SW Timing Jitter (3G/12G-SDI Spec: <= 2.0UI) Wander Sampling Rate: 1sec Sampling Rate: 1sec
- 13. 13 © 2018 M3L Inc. • 1 x L2 switch (PTP BC mode) 7. 12G-SDI over 25GbE w/L2 switches 10/25G L2 SW Mellanox SN2070 SG / PTP Grandmaster LEADER LT4610 SFP28 M3L 2110 Ingress Core Xilinx FPGA M3L 2059 Slave Core SFP28 Xilinx FPGA M3L 2110 Egress Core M3L 2059 Slave Core FPGA Eva Board Xilinx KU116 FPGA Eva Board Xilinx KU116 Embrionix 12G-SDI SFP Module 10GbE 25GbE 12G-SD I(2160/59.94p) BB Analysis / Monitor Phabrix Qx12G 12G-SDI 25GbE
- 14. 14 © 2018 M3L Inc. • 2 x L2 switches (PTP BC mode) 7. 12G-SDI over 25GbE w/L2 switches 10/25G L2 SW Mellanox SN2070 10/25G L2 SW Arista Networks 7280SR2A SG / PTP Grandmaster LEADER LT4610 SFP28 M3L 2110 Ingress Core Xilinx FPGA M3L 2059 Slave Core SFP28 Xilinx FPGA M3L 2110 Egress Core M3L 2059 Slave Core FPGA Eva Board Xilinx KU116 FPGA Eva Board Xilinx KU116 Embrionix 12G-SDI SFP Module 10GbE 25GbE 12G-SD I(2160/59.94p) BB Analysis / Monitor Phabrix Qx12G 12G-SDI 25GbE 25GbE
- 15. 15 © 2018 M3L Inc. 7. 12G-SDI over 25GbE w/L2 switches Timing Jitter (12G-SDI Spec: <= 2.0UI) Wander 1x SW 2x SWes 1x SW 2x SWes
- 16. 16 © 2018 M3L Inc. • 2 switches on 25GbE might have a greater timing jitter • Timing jitter sometimes jumps up when using L2 switches, regardless of PTP intervals – Range of timing jitter still under the upper limit – Due to error correction by feedback control ? • Switches could not affect wander on 25GbE 7. 12G-SDI over 25GbE w/L2 switches
- 17. 17 © 2018 M3L Inc. 8. 12G-SDI/25GbE vs 3G-SDI/10GbE w/SWes 10/25G L2 SW Mellanox SN2070 10/25G L2 SW Arista Networks 7280SR2A SG / PTP Grandmaster LEADER LT4610 SFP28 M3L 2110 Ingress Core Xilinx FPGA M3L 2059 Slave Core SFP28 Xilinx FPGA M3L 2110 Egress Core M3L 2059 Slave Core FPGA Eva Board Xilinx KU116 FPGA Eva Board Xilinx KU116 Embrionix 12G-SDI SFP Module 10GbE 25GbE 12G-SD I(2160/59.94p) BB Analysis / Monitor Phabrix Qx12G 12G-SDI 25GbE 25GbE
- 18. 18 © 2018 M3L Inc. 8. 12G-SDI/25GbE vs 3G-SDI/10GbE w/SWes • Lower PTP intervals on 10GbE have greater wander • Lower PTP intervals with more switches could make greater timing jitter Timing Jitter Wander
- 19. 19 © 2018 M3L Inc. 9. Separated PTP channel • Separate PTP transactions from ST-2110 data streams • The L2 switches are used for PTP time synchronization 10/25G L2 SW Mellanox SN2070 10/25G L2 SW Arista Networks 7280SR2A SG / PTP Grandmaster LEADER LT4610 SFP28 M3L 2110 Ingress Core Xilinx FPGA M3L 2059 Slave Core SFP28 Xilinx FPGA M3L 2110 Egress Core M3L 2059 Slave Core FPGA Eva Board Xilinx KU116 FPGA Eva Board Xilinx KU116 Embrionix 12G-SDI SFP Module 10GbE 25GbE 12G-SD I(2160/59.94p) BB Analysis / Monitor Phabrix Qx12G 12G-SDI 25GbE
- 20. 20 © 2018 M3L Inc. 9. Separated PTP channel • Lower PTP interval on separated PTP is lower both jitter and wander than multiplexed one – Effect on being nothing to disturb the PTP transactions ? Timing Jitter (12G-SDI Spec: <= 2.0UI) Wander
- 21. 21 © 2018 M3L Inc. • Lock-time evaluation w/various parameters – Still under improvement for the production release 10. Lock-time evaluation (future plan) Sampling Rate: 1sec Lock time
- 22. 22 © 2018 M3L Inc. • No error by any parameter settings • But the quality of reproduced SDI signals can be changed with settings. Recommend you to evaluate your own system. – PTP Intervals, Ethernet Media (10GbE/25GbE), Number of cascaded L2 switches, Multiplexed/Separated PTP (Ethernet Load) • The result of lock-time evaluation is coming soon • Hope that ST-2110 will be spread out by correct understanding with quantitative number – We M3L will publish such information to you in the future • Questions and comments : Email oyama@m3l.co.jp 11. Conclusion
- 23. © 2018 M3L Inc. Thank You ! Special Thanks to: