1. LOKESH MISTRY
Mobile: +91-9461450360
Email: lokesh.mistry90@gmail.com
Address: Near Hinglaj Temple Suthar Vas, Sirohi (Rajasthan)
• PROFESSIONAL EXPERIENCE:
• 6 months trainingand 2 months internshipexperience in:
• ASIC Verification experience using UVM and System Verilog (SV) that includes development of
the Verification Environment, Testbench development, Testplan definition and development,
Testcase implementation, Functional Coverage and checker coverage implementation,
RegressionanalysisandCode Coverage.
• Hand on scripting– Perl
• Knowledgeof SPIProtocol.
• EXPERIENCE:
Training & internship at Maven Silicon Pvt. Ltd. Bangalore as ASIC Design andVerification Engineer, from
Sep2015 to till date.
• PROFESSIONAL SKILLS
OperatingSystems Linux,Windows
HDL VerilogHDL
HVL SystemVerilog
Methodology UVM,
Scripting languages Perl
EDA Tools Questasim, ISE,RiveraPro.
Other Tools ModelSim
EDUCATIONAL BACKGROUND
Examination College/school Percentage Year
B.E M.B.M Engg. College,J.N.V.U 59% 2013
Class 12th
Govt Sr. Sec.School,New Building,Sirohi 78% 2008
Class 10th
Govt Sr. sec.School,OldBuilding,Sirohi 80% 2006
EXPERIENCE DETAILS
Project #3:

2. Project : VerificationOfAXI-4 BFM
Technology: AXI
Language : SystemVerilog/UVM
Tools Questasim
Description:
• The AMBA AXI protocol supports high-performance, high-frequency system designs. The AXI4-
Stream and AXI-Full protocols are used as a standard interface to connect components that
wish to exchange data. The interface can be used to connect a single master that generates
data, to a single slave, that receives data. The protocol can also be used when connecting
largernumbersof masterand slave components.
Role and responsibility:
• Understandingthe AXI4specification.
• Writingtestplantoverifythe AXIBFM.
• DevelopingSV/UVMenvironmentandscoreboard.
• Implementationof testcasesanddebugging.
Project #2:
Project : DesignOf Amba AHB-APB BRIDGE
Language : VerilogHDL
Tools Questasim,RiveraPro.
Description:
An AMBA basedsystemconsistof a highperformance bus(AHBor ASB),On-chipmemoryandother
DirectMemory Access(DMA) devicesreside.Thisbusprovidesahighbandwidthinterface betweenthe
elementsthatare involvedinthe majorityof transfers.Alsolocatedonthe high-performance busisa
bridge tothe lowerbandwidthAPB.
Role and responsibility:
• SpecificationandwritingRTLUnderstandingAmbadesign.
• SpecificationandwritingTB UnderstandingAmbadesign
• Developingcomplete UVMEnvironmentfromscratch.
• Coverage analysis.
Project #1:
Project : VerificationofSPI

3. Role : Team Member
Language : SystemVerilog
Tools Questasim,RiveraPro.
Methodology UVM
Description:
• Synchronous serial interfaces are widely used to provide economical board-level interfaces
betweendifferentdevicessuchasmicrocontrollers,DACs,ADCsandother.
Role and responsibility:
• Understandingof SPIMasterCore Specification.
• Writingtestplanandverificationstrategy.
• Developingcomplete UVMEnvironmentfromscratch.
• Writingtestcasesandregressionanalysis.
• Functional Coverage andCode Coverage Analysis.
ACHIEVEMENS
• Got state rank 236 (Gen.) in Rajasthan Pre Engineering Test and Category rank 50.
• Got selected in All India Engineering Entrance Exam (AIEEE).
• Got selected in M.H.T.C.E.T.
• Got 5th position in district merit in senior secondary examination.
• Got 9th position in class 8th district board with 94%.