Whole Die and Circuit Component Reverse Engineering Solution

1. VECTOR EXPORT
3D MODEL
FEATURE
EXTRACTION
Capture chip Reconstruct layers Create 3D layout Output 3D layout to Perform analysis or
layer set into image map using ChipReveal-3D desired format chip recreation
ChipReveal-3D™
Cerium Labs Chip Analysis Tool Suite
Cerium Labs services include partial or A One-Stop Solution for Chip Re-engineering
whole die imaging, pattern recognition To recreate lost or obsolete technologies, Cerium Labs offers a one-stop
and extraction, circuit functionality solution to custom chip recreation. Using ChipReveal-3D, a complete
modeling, and creation of 3D renditions suite of proprietary acquisition methods and software tools, we create
of specific circuits or the entire device. three-dimensional visualization of VLSI circuits. ChipReveal-3D provides
Our technologies can visualize your visualization for:
recovered designs and data in a variety Block extraction – circuit, component, systems design level
of ways: Functionality – floor plans, block diagrams, conceptualization
Feature extraction Reverse engineering – PCB, package, interconnects,
die layer-by-layer teardown, CAD layout extraction, SPICE modeling,
Layer reconstruction
Netlists, and GDSII files
3D models Design verification – layer comparison, mission-critical electronics,
verification
Learn more about the Cerium Labs one-stop solution to
chip re-engineering at www.ceriumlabs.com
Cerium Labs
5204 E. Ben White Blvd., Building 1, Austin, TX 78741 | 512.691.7752 | toll free 1.866.770.7752 | www.ceriumlabs.com
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