1. Indiana Integrated Circuits, LLC and
Quilt Packaging® Technology: An Overview
Jason Kulick, President & Co-Founder
jason.kulick@indianaic.com
574-217-4612 (South Bend, IN)
Alan Isaacson, VP Business Development
alan.isaacson@indianaic.com
719-442-0194 (Colorado Springs, CO)
February 2016
2. Indiana Integrated Circuits, LLC (IIC)
Formed to commercialize Quilt Packaging (QP) – a ground
breaking packaging technology invented at Notre Dame.
•Founded by Kulick & Bernstein (2009)
•Main office South Bend, IN at Innovation Park (also CO & NC)
•IIC has experienced steady growth with customers & partners
across multiple industry sectors since early in it’s inception.
•Operations funded directly through revenue growth and
through equity investment (Series A closed late 2015).
•The QP process is commercially available at RTI International.
•Process development for medium volume requirements is
ongoing at Rogue Valley Microdevices in Medford, OR.2
3. IIC Business Model--Licensing
(supported by prototyping)
• IIC partners with
customers to integrate
QP into their systems.
• First-adopters for QP are
DOD high-performance
applications.
• Transition from DOD to
commercial applications
are planned as the
technology matures and
risks are reduced.
3…and more proprietary.
4. Segment Penetration & Selected
Customers / Partners
Microwave & RF
Large Format Array
Power Electronics
MEMs/Internet of Things
Optical Integration
Biomedical/Biosensors
4
Confidential Customer
Confidential Customer
5. Existing Supply Chain—Wafer Processing
• RTI International, Inc.
– ITAR compliant BEOL facility
located in Durham/RTP, NC
– Wafer post-processing for
deep etch, plating, CMP,
singulation
– Si & SiC substrates from
pieces up o 8” wafers
– IIC partner since 2012
– Offering QP MPW service
– Can support up to 100 wafer
starts per month
• Rogue Valley Microdevices, Inc.
– Pure-play MEMS foundry located
in Medford, OR
– Wafer post-processing for thin
film, etching, litho (deep etch
coming)
– Multiple substrates, up to 8”
wafers
– IIC partner since January 2015
(MIG Tech. Pitch win award)
– Can support several hundred
wafer starts per month
5
6. Existing Supply Chain—Assembly
• Automated Tooling Partner:
MRSI Systems, Inc.
– Global supplier of fully-
automated solutions for
assembly of microelectronic
devices
– High precision die attach &
dispensing systems
– Demonstrated automated
Quilt Package assembly on
MRSI 705 system
– Working with since 2012
– Based in Billerica, MA
• North American-based Low
to Medium Volume
Assembler
– Public announcement coming
soon (March 2016)
– Leader in electronics design,
manufacturing and
aftermarket services
– Can support DOD applications
6
7. The Problem:
Existing Microchip Packaging
7
A
B
Electrical Signal
Existing technologies waste:
•Power
•Time
•Money
•Space
Now a system constraint!
ch
ip
packa
ge
PC board
Chip A Chip B
Package Package
“…Overall performance, cost,
size and functionality of a
system will be limited by….the
off-chip interconnects.”
-International Technology Roadmap For Semiconductors
8. 8
Quilt Packaging enables
10x to 100X improvement!
•Power--- 10x lower parasitic losses
•Time---10x faster
•Money---Order of magnitude total
system cost savings
•Space---Dramatic form factor reduction
Quilt Packaging is a patented, direct edge-
to-edge chip interconnect technology that
can be implemented in disparate materials
and technologies.
The Solution:
Quilt Packaging Interconnect Technology
Electrical
Signal
Chip A Chip B
Package
Chip A Chip B
Quilt Packaging
interconnect
Solder
Quilt Packaging enables new
system designs
Quilt Packaged chipsets and interconnects
9. Quilt Packaging (QP) Technology
• Edge-connections joined to
create multi-chip “quilt,”
developed at Notre Dame
• “Monolithic” assemblies
from same or disparate
materials & process
technologies
• Extremely low impedances
• Enables optimization for
cost and functionality
• Industry-standard tools and
fabrication processes
(available in Si at RTI)
9
CHIP 1 CHIP 2
10. QP-Interconnect Structures
• Edge connection
structures called
“nodules”
• Solid metal, typically
Cu, 5-500 um wide,
20-50 um thick
• 10 um pitch possible
• Customizable shapes-
including interlocking-
enables sub-micron
chip alignment
10
14. Why use Quilt Packaging?
• Optimized integration of disparate materials and process
technologies (Si, GaAs, GaN, SiGe, AlN, more)
• Chip partitioning for optimal yield/functionality
• Sub-micron chip-to-chip alignment (FPAs, IRSPs, Optical)
• Better thermal management due to all chips on heatsink
• Reduced power dissipation, die size, design cycle time
• Variety of interconnect geometries & sizes available
simultaneously
• Increased IP flexibility, security & design re-use
• Complementary with existing packaging approaches---can be
combined w/TSV, WB, bumping, etc.
14
15. Quilt Packaging: Processing &
Implementation
• Based on standard
process flows in Si, III-Vs
– Dry etch, plating, CMP,
wafer thinning
• No exotic processes or
materials required
• Demonstrated: Si, GaAs, InP
Etch Nodules Seed & Plate
Interconnect ICP-RIE Streets
Thin & Dice Assembly
16. Quilt Packaging Process
The Quilt Packaging fabrication process is also described in the figure below. To fabricate QP in Si or III-
V substrates, conventional photolithography is used to define the nodule features, which are then
etched to a depth of ~ 25 microns into the wafer using Bosch deep reactive ion etching (for Si) or a
chlorine-based inductively coupled plasma etching (for III-Vs). After the nodules shapes are defined, a
seed layer, Ti/Cu is deposited and the nodules are filled using a Cu electroplating step. Electroplating
overburden is removed with a chemical mechanical polishing (CMP) step. Wafers are singulated by a
combination of deep etching and backside grinding.
QP Fabrication Process (starting at top left and following arrows to
bottom: 1)Front end finished; 2) Nodules etched; 3) Dielectric
insulating layer; 4) Nodule metallization; 5) Metal 1 deposition; 6)
Singulation etch; 7) separation grinding; 8) Die connection; 9) Final
quilt assembly.
17. Quilt Packaging Process
Quilt Packaging can be implemented at the IDM, Foundry or OSAT
In order to get the full benefit from Quilt Packaging, chips and packaging are designed with
QP in mind from the beginning. QP can be implemented in a variety of substrates, including
Si, GaAs, InP, SiGe, SiC, GaN, and more. Wafer fabrication on the front end is exactly like that
of any other process, and QP is implemented during the Back-End-of-Line processing.
1. Finish Front-End-Of-Line
The Quilt Packaging fabrication process begins as the front end work finishes, very similar to
a "via-middle" approach for fabricating TSVs. Quilt Packaging can occur at the foundry or at
an assembly house capable of the etching, metallization, and other Back-End-of-Line
process (just like via-middle).
2. Nodule Definition Etch, Metallization & CMP
An etch mask is used to define the nodule features, and the "mold" for nodules is created
by removing material through an etch process. Following nodule definition etch, the wafer
undergoes seed layer deposition, electroplating build-up of the nodule metal, and CMP
removal of the overburden.
18. Quilt Packaging Process
3. Finish Global Chip Interconnects
After the CMP step, the wafer now has metal nodules "embedded" in what would usually
be the dicing streets and the wafer looks otherwise as it did prior to nodule definition
etch. At this point the rest of the back end of line is completed, with signal connections
made across the chip and to nodules as needed.
4. Singulate QP Die, Assemble & Reflow
Once global interconnects are made, a final separation etch mask is used to protect the
die surface during the separation step. Wafer singulation is implemented by dry etching or
a combination of dry etching and grinding or sawing. Chips are then assembled into
"Quilts" and reflowed to form one large "Metachip." This quilt is then treated as if it were
one large chip, and ends up in a package, on a board, on ceramic, etc.
19. Quilt Packaging: Electrical Performance
(Performs as if it were an on-chip interconnect)
• Homogeneous (e.g. Si-Si, GaAs-GaAs) and
heterogeneous (Si-GaAs, Si-InP)
interconnects demonstrated
• Excellent RF/millimeter-wave, high-speed
digital performance:
– S21 ≤ 0.75 dB to 220 GHz
– 43 Gb/s eyes with no impairment
• Ultra-low parasitics
• Dense I/O pitch at chip edge (10 um pitch)
• Extremely high current-handling capacity
> 10 A through 30 µm x 20 µm nodules
without damage
Si-GaAs CPW
20. Quilt Packaging: Mechanical Performance
• Interconnects are
mechanically robust
• Interconnected modules can
be handled like larger chip
(e.g. pick & place, etc.)
• Preliminary pull testing
requires large force before
failure; resistant to thermal
shock
Pull test:
50 µm x 20 µm nodules,
40 nodules per edge
Four die connected;
mechanical handling as if
single chip
21. Preliminary Thermal Cycling Results
• Probe testing & optical
inspection before and after
cycling
• Cycled from -40 C to 125 C
• 22 minute dwell times
• Removed for inspection at
350 cycles & 1,000 cycles.
• No failures
• No increases in resistance
or opens
• No visible damage/defects
21
22. Summary of Quilt Packaging Advantages
• Optimized heterogeneous integration
of disparate materials and/or process
technologies (Si, GaAs, GaN, SiGe, SiC &
more
• Chip partitioning for optimal
yield/functionality
• Scalable technology using standard
fabrication & assembly tools
• Design re-use & reduced design cycle
time and reduced time-to-market
• Provides precise mechanical alignment
accuracy, better than 1 um
• Significant size, weight, power, and
cost reductions for systems
• Compatible with other packaging
approaches: flip-chip, TSV, wirebonds
Three ICs connected
by Quilt Packaging
Cutaway view
of
nodules
24. Silicon QP Microwave Performance
Less than 0.1 dB insertion loss from 50 MHz past 100 GHz, with no
resonances. Recent results under 1 dB at 220 GHz
24
(D. Kopp, C. Liang, J. Kulick, M. Khan, G. H. Bernstein, and P. Fay, “Quilt Packaging of RF Systems with Ultrawide
Bandwidth,” Proc. of the IMAPS - Advanced Technology Workshop on RF and Microwave Packaging, San Diego (2009).
25. Silicon QP Eye diagrams
• Measurement of 12 Gb/s eye
pattern (Anritsu MP1763B)
– Horiz. 100 mV/div
– Vert. 20 ps/div
• Data stream: 231-1 pseudo-
random bit sequence
• Nearly ideal interconnect
performance; indistinguishable
from PG.
• Error-free operation
– SNR (Q) = 12.9 for pattern
generator alone, 12.4 after
chip-to-chip interconnect
Raw pattern
generator
50 µm
GSG eye
25
(D. Kopp, C. Liang, J. Kulick, M. Khan, G. H. Bernstein, and P. Fay, “Quilt Packaging of RF Systems with Ultrawide
Bandwidth,” Proc. of the IMAPS - Advanced Technology Workshop on RF and Microwave Packaging, San Diego (2009).
26. Silicon QP Time-Domain Performance
• Single-ended GSG CPW
configuration
• Picosecond Pulse Labs
4022 TDR pulse
enhancement module:
< 9 ps risetime
• Total delay including
probe pads, launcher: 7
ps (820 μm length)
• Delay due to QP
nodules: 2.7 ps
100 µm nodule compared with
pads/launcher, GSG
26
(D. Kopp, C. Liang, J. Kulick, M. Khan, G. H. Bernstein, and P. Fay,
“Quilt Packaging of RF Systems with Ultrawide
Bandwidth,” Proc. of the IMAPS - Advanced Technology
Workshop on RF and Microwave Packaging, San Diego (2009).
27. GaAs Measurement Data Sample
Raw S-parameters De-embedded S-parameters
*Less than 3 dB (2.2 dB) insertion loss at 220 GHz
(Fay, P.; Kopp, D. ; Lu, T. ;, Neal, D. ; Bernstein, G.H., ; Kulick, J.M.; “Ultrawide Bandwidth Chip-to-Chip Interconnects For III-V
MMICs,” IEEE Microwave and Wireless Component Letters,, Volume: PP, Issue 99, 2013
29. Large Format Array Example: 2x2 Quilted
Chipset for IRSP/FPA
• Large format arrays suffer
from poorly- yielding ROIC
and RIIC chip sizes (Si CMOS)
• Tiling approach requires
small chip gap (<10 um) and
sub-micron alignment
accuracy
• QP delivers gap, alignment,
and dense edge I/O, enabling
tiling of arbitrarily large
arrays
• This approach can be utilized
for other larger Si chips
29
30. Optical Integration Example:
Multispectral Laser Concept
30
III-V Laser Diode Chips
(10’s of lasers per chip)
Silicon Waveguide Combiner
w/single facet for emission
QP interconnects for sub-micron
Chip-to-chip waveguide alignment
accuracy
31. Optoelectronics and Photonics Example
• Precision integration:
– High-density, low-loss silica planar
optical waveguides
– High-performance III-V emitters &
detectors
• Sub-wavelength passive chip-to-
chip alignment
• Experimentally demonstrated:
– Lateral alignment: << 1 µm
– Axial positional tolerance: < 5 µm
– Insertion loss ≤ 2 dB in mid-IR
(Courtesy S. Howard & S. Hoffman, Notre Dame)
32. Optoelectronic Sources & Sensors Example:
Lab-On-A-Chip
• Tunable, high-power THz sources
– Independently optimize mid-IR pump lasers and
difference frequency generator (DFG) nonlinearity
– High power (~mW), room-temperature, CW
• Sensitive and specific stand-off
material detection
• Integration with microfluidics for on-chip liquid,
gas analysis and sensing
Optical QP
A.G. Davies et al., Materials Today 11, 18 (2008).
Frequency (THz)
Absorption(103cm-1)
(Courtesy S. Howard & S. Hoffman, Notre Dame)
33. Millimeter-Wave/THz Electronics Example
• Ultra-wideband, low-loss interconnects with mechanical self-alignment
– Integration for advanced functionality; quartz filters, feeds with InP electronics
– Loss reduction enables lower power budget
– Compact “single block” realization, no change to active device technologies
• mm-Wave/THz sensing and imaging, communication
• Example: 340 GHz transceiver: Around 10”x10” to a 1” single block; applicable
to many mm-wave/THz systems
Conventional Split-Block
QP Single-Block Integration
QP interconnects
(Courtesy P.Fay & L. Liu, Notre Dame)
