Successfully reported this slideshow.

Metal bonding alternatives to frit and anodic technologies for wlp


Published on

* Overview of frit and anodic bond processing
* Mechanics of metal bonding options
* Process requirement comparisons
* Hermetic capabilities
* Equipment requirements for metal bonding

More technical papers on

Published in: Technology, Business
  • Be the first to comment

Metal bonding alternatives to frit and anodic technologies for wlp

  1. 1. Metal Bonding Alternatives to Frit and Anodic Technologies for Advanced Wafer Level Packaging James Hermanowski October 2010
  2. 2. 2 Overview Overview of frit and anodic bond processing Mechanics of metal bonding options Process requirement comparisons Hermetic capabilities Equipment requirements for metal bonding Summary
  3. 3. 3 Expanding CE (consumer electronics) market drives the Semiconductor innovation Push for integration Reduction in power consumption Smaller form factor Image sensors and memory stacking (for mobile applications) are two mass volume applications for TSVs with close time-to-market 1980‘s1950‘s Today Enabling new devices Advanced Wafer Level Packaging
  4. 4. 4 Fusion / Adhesive Bonding Lithography, Adhesive Bonding CMOS ImageSensor CMOS Image Sensor Integration (BSI) CMOS Image Sensor Packaging Wafer Level Optics Assembly Imprinting, UV Bonding Kodak / Intel / Samsung Memory Stacking DRAM FLASH NAND Metal to Metal Bonding Fusion bonding Adhesive Bonding SUSS Equipment for Advanced WLP and 3D-IC
  5. 5. 5 Materials and Process – Anodic Bonding Anodic Bond Materials – thermal matching Glass (sodium silicate) (8.6 x 10-6/°C) Pyrex (borosilicate) 3.25 x 10-6/°C) Si (2.6 x 10-6/°C) Spin-on glass or magnetron sputtered glasses, SOI Smooth and clean surfaces needed for best hermetic sealing Mechanical strength, ability to withstand stress Anodic Bond Process Parameters Temperature 300+ to 450C, some research at room temperature Lower is better for throughput, warpage, etc. Glass dependent, ion mobility important Voltage 400V to 1000+V, 800V typical, up to 2000V possible Current, maximum allowable 15mA up to 60mA Bond force used to hold wafers together, non-critical parameter 500N to 1000N normal
  6. 6. 6 - + Na+ Si+ Anodic Bonding - Theory The Na and O ions are diffusing due to the thermal energy. Due to the applied voltage the direction of the diffusion is controlled. It is necessary to apply a negative voltage (e.g. –800Volts) on the cathode, to attract the Na+ ions. Without Na+ diffusion there is little current. The “holes” created by the Na+ diffusion leaves bonding sites on the glass lattice for the Si to occupy and bond with the glass (forming SiOx). Silicon is also positive and directed towards the interface by the bias conditions. SUSS triple stack allows user to program third electrode Program Grounded Na+ + Na+ Normal anodic bond Triple stack anodic bond Programmable control to allow different process conditions at each bond Vacuum bond Overpressure bond
  7. 7. 7 Terminating the Bond Process Three common options Time based Charge based Current decay based – best for production, ~20% of initial current This is the best way to terminate the process. This is also the best way to develop a process. Time scale shows how each process begins to terminate close to each other.
  8. 8. 8 Issues Encountered – Anodic Bonding Metal ions on glass wafer
  9. 9. 9 Materials and Process – Frit Bonding Frit Bond Materials – Frit glass material Clean surfaces needed for best hermetic sealing Mechanical strength, ability to withstand stress Frit Process Usually frit is screened onto wafers – a dirty process Frit must be fired after screen print to remove organics and convert it to glassy material Frit Bond Process Parameters Temperature 400 to 450C, specific frit dependent Bond force used to hold wafers together, less critical paramete
  10. 10. 10 Issues Encountered with Frit Bonding Alignment shifting Contamination from screening process Non-planar frit coatings can damage CMOS wafer when force is applied
  11. 11. 11 Process Comparisons: Anodic, Frit, Metal Silicon Glass Silicon Silicon Silicon Glass Silicon Silicon Silicon Silicon Silicon Silicon AnodicGlassFritMetal Initial Substrates Bonded Substrates Die Packaged
  12. 12. 12 10 um Glass seal will remain10 um Glass seal will remain hermetic for ~1yr.hermetic for ~1yr. 10 um Metal seal will remain10 um Metal seal will remain hermetic for ~100yrs.hermetic for ~100yrs. 1 um Metal seals will remain1 um Metal seals will remain hermetic for years.hermetic for years. Hermeticity, Low Temperatures & Smaller Die Drive Metal Bonding Schemes Polymers = 10-6 cc/sec Glasses = 10-10 cc/sec Metals = 10-16 cc/sec Permeation rates
  13. 13. 13 Metal Bonds Enable Better Performance and Scaling 121233338989385385Max Added Die/wfr (100Max Added Die/wfr (100µµm > 2m > 2 µµm)m) 113181351Max Added Die/wfr (100µm > 10 µm) <1%1%1%1%10µm wide Seals 1%1%2%3%25µm wide Seals 2%3%4%6%50µm wide Seals 4%5%7%12%100µm wide Seals % Surface Area Consumed by Seals 10753Die Size (mm x mm) Assumes 200mm wafer, 3mm EE, 375µm dicing street • Over 300 Additional Die from Seal Ring Geometry Reduction • Device Scaling (due to better hermeticity) adds additional die. • e.g. 7mm→5mm die size adds > 500 die
  14. 14. 14 Requirements for Diffusion Bonding Proper materials system: Rapid Diffusion at Low Temperature Same crystal structure best Minimal size difference High Solubility High mobility and small activation energy Diffusion Barriers to protected regions High Quality films - No contamination or Oxide Intimate Contact between surfaces Process Variables Heat Pressure Gas Ambient Process Vacuum levels
  15. 15. 15 Complete Solid Solubility • Both Cu and Ni are FCC crystals • ρ(Cu)=8.93 gm/cm3 • ρ(Ni)=8.91 gm/cm3 • Lattice Spacing a0(Cu)=3.6148Å • Lattice Spacing a0(Ni)=3.5239Å Copper (Cu) - Nickel (Ni) αα liqliq CuCu NiNi
  16. 16. 16 Microstructure Development Interface Properties 1. Generally retain elastic properties of noble metals. 2. Resistivity usually obeys Vegard’s rule - linear with % atomic concentration of mix. 3. Full layer diffusion not needed. 4. Adhesion layers may be needed for initial substrate deposition process. 5. Diffusion barrier may be incorporated with adhesion layer to prevent diffusion into substrate. 6. Wetting agents between A & B layers assists in initialization of diffusion. Silicon Silicon Metal A (Ni) Metal B (Cu) Fully mixed with
  17. 17. 17 Diffusion Bonding 1. The mechanical force of the bonder establishes intimate contact between the surfaces. Some plastic deformation may occur. 2. During heating the atoms migrate between lattice sites across the interface to establish a void free bond. RMS <2-5 nm required. 3. Vacancies and grain boundaries will exist in final interface area. Hermeticity is nearly identical to a bulk material.
  18. 18. 18 Diffusion Pathways in Crystals: Poly vs Single Single CrystallineFine Grain Poly- Crystalline Dsurface > Dgrain.boundary > Dbulk Course Grain Poly- Crystalline
  19. 19. 19 Type A Kinetics: Rapid Bulk Diffusion Rates In Type A kinetics the lattice diffusion rates are rapid and diffusion profiles overlap between adjacent grains. gbgb gbgb gbgbgbgbbulk bulk bulk
  20. 20. 20 In type B kinetics the grain boundary is isolated between grains. Behavior mimics bulk diffusion. Diffusion is by both grain boundaries and bulk atomic motion. Dominate pathways are related to grain size and density. Type B Kinetics: Normal Bulk Diffusion w/ GB Effect gbgb gbgb gbgbgbgbbulk bulk bulk
  21. 21. 21 In Type C kinetics the lattice diffusion rate is insignificant and all atomic transport is dominated by grain boundary diffusion only For example room temperature diffusion. Type C Kinetics: Insignificant Bulk Diffusion gbgb gbgb gbgbgbgbbulk bulk bulk
  22. 22. 22 6 4 2 0 -6 -4 -2 6 4 2 0 -6 -4 -2 2 40 6 8 10 12 6 4 2 0 -6 -4 -2 2 40 6 8 10 12 Log[1/g.s.(cm)] Log ρd (cm-2) Log ρd (cm-2) Log[1/g.s.(cm)] T/Tm = 0.3T/Tm = 0.4 T/Tm = 0.6 T/Tm = 0.5 gbgb gbgbgbgb gbgb ll ll ll ll dddd dd dd • Regimes of grain size (g.s.) and dislocation density ρd over which (l) lattice diffusion, (gb) grain boundary diffusion of (d) dislocation diffusion is the dominate mechanism for atomic motion. • All data is normalized to the melting point and applies for a thin film fcc metal at steady state. • Shaded area is typical of thin film dislocation density 108 to 1012 lines/cm2. Low Temperature Diffusion Relies on Defects
  23. 23. 23 164°C8.5e-131.5e-22 210°C7.8e-121.4e-20 268°C7.5e-111.4e-18 444°C3.7e-91.8e-18 TemperatureDgb (cm2/sec)Dl (cm2/sec) Gold Lattice and Grain Boundary Diffusivities 6 4 2 0 -6 -4 -2 2 40 6 8 10 12 Log[1/g.s.(cm)] Log ρd (cm-2) gbgb ll dd Grain Boundary Diffusion Distance (um) 0 5 10 15 20 25 30 35 0 10 20 30 40 50 Time (minutes) DiffusionDistance(um) 444C 268C 210C 164C
  24. 24. 24 Metal Bonding Options Reaction Type Metal † Bond Temp Oxidizes CMOS Compatible Cu-Cu >350°C No Yes Au-Au >300°C Yes No Al-Ge >419°C No Yes Au-Si >363°C Yes No Au-Ge >361°C Yes No Au-Sn >278°C No No Cu-Sn >231°C No Yes † Eutectic bonds are done ~15°C above the listed eutectic tempereature. Diffusion bonds lower limit expressed. Diffusion Eutectic CMOS compatibility –barrier layers are often used to prevent metal migration to the CMOS structure.
  25. 25. 25 Key Different Requirements for Metal Bonds Surface roughness is important to allow the metal surfaces to come into intimate contact, especially for diffusion bonding Metal oxide formation can prevent strong bond formation Preventive actions and process controls need to be established Force requirements are much tougher Structural issues with bond chamber will become much more apparent during metal bonding For example, the chamber shape may change with the application of high heat and force causing unbonded areas to form in the devices Temperature controls will be pushed harder To obtain the tighter overlay possible with metal bonding, it is important to control both wafers to tight temperature tolerances To prevent oxide formation, it is more desireable to load wafers at lower temperatures into the bond chamber
  26. 26. 26 Gold-Gold bond at 300°C for 30 min. Au layer is 350nm, Cr is 50nm thick 0.5μm AuAu AuAu CrCr CrCr SiSi SiSi InterfaceInterface 0.5μm AuAu AuAu CrCr CrCr SiSi SiSi InterfaceInterface Surface roughness is important to maintain intimate contact and good bonds.
  27. 27. 27 Thin (400nm) Cu/Cu bonds at 300°C for 30 min. 1μm Si Si Cu Cu Interface Interface 1μm1μm Si Si Cu Cu Interface Interface Ultra smooth surfaces allow better molecular intermixing and deliver good bond quality
  28. 28. 28 SUSS Coater for 3D Packaging Main Applications Redistribution Layers (RDL) Main Market: Memory and WLCSP for memory center to edge rerouting, mainly for wire bonded stacks Inverse to typical WLCSPs -> edge to center for best distribution & lowest DNP (distance to neutral point) -> lowest stress for direct board attach Redistributed Chip Packages Wafer level (or better “substrate level”) package formation Fan-out option (contact grid larger than die size) Cheaper (parallel) package formation (encapsulation) Well suited for POP applications Image Sensor Integration Via contact from the back
  29. 29. 29 SUSS Aligner for 3D Packaging Applications CIS (Image sensor packaging) Back Side Alignment, Infra-Red Alignment, Warped Wafer Handling, high topography lithography Memory Stacking Resolution for TSV manufacturing, Infra-Red Alignment, RDL with tight overlay control, tight CD control WLP of Optical Devices UV-Bonding, Micro lens imprinting
  30. 30. 30 SUSS Bonders for 3D Packaging Applications CIS – CMOS Image Sensors CMOS Image sensor Packaging and Integration (BSI) Wafer Level Optics Assembly Memory Stacking Memory to Logic Integration Mixed Signal/Analog to Digital Integration Die to Wafer Stacking Wafer to Wafer Stacking Source: OmniVision Technologies
  31. 31. Equipment for Permanent & Temporary Bonding for Advanced WLP
  32. 32. 32 Permanent Bonding Cu-Cu Bonding Polymer / Hybrid Bonding Fusion Bonding Temporary Bonding/De-bonding capability Thermoplastics Process (eg. HT10.10) 3M WSS Process Dupont / HD Process Thin Materials AG (TMAT) Process Total Process Flexibility for 3D Applications XBC300 Standardized Platform
  33. 33. 33 XBC300 Configuration Examples SC300 For adhesive coating Module 3 PL300 (TMAT) Laser module DB300 Tape on frame LF300 SC300 for cleaning (optional) Temporary Bonding De-bonding
  34. 34. 34 True Modular Design
  35. 35. 35 True Modular Design
  36. 36. 36 True Modular Design
  37. 37. 37 True Modular Design True Modular Design Lowers investment risk Ideal for changing technology requirements Lowers COO Small footprint, high throughput
  38. 38. 38 BA300UHP Aligner CB300 Bonder CP300 Cool Plate SC300 Spin Coater PL300T Surface Prep LF300 Low Force Bonder DB300 Debonder Temporary Bonding Permanent Bonding CL300 Wafer Cleaning PL300 Plasma Activation Process Flexibility: Complete Line of Process Modules
  39. 39. 39 Permanent Bonding Configurations BA300UHP Aligner CB300 Bonder CP300 Cool Plate Fusion Bond Configuration Cu-Cu and Polymer Bond Configuration* BA300UHP Aligner (if alignment with keys required) PL300 Plasma Activation CL300 Wafer Cleaning *Optional Die to Wafer Collective Bonding
  40. 40. 40 Permanent Bond Configurations BA300UHP Bond Aligner – submicron alignment accuracy CB300 Bond Chamber – temperature & force uniformity CP300 Cool Plate – controlled cool rate *Optional Die to Wafer Collective Bonding Cu-Cu and Polymer Bond Configuration*
  41. 41. 41 Sub Micron Alignment Accuracy Path to 350nm PBA for Cu-Cu bonding Path to 150nm PBA for Fusion bonding ISA alignment mode for face to face alignment Allows smaller via diameters and higher via densities Built in Wedge Error Compensation (WEC) to make upper and lower wafers parallel prior to alignment Eliminates wafer shift during wafer clamping Closed loop optical tracking of mechanical movements Void free bonding in the BA with RPP™ Patent pending RPP™ creates an engineered bond wave for propagation Eliminates need for bond module BA300UHP Bond Aligner Module
  42. 42. 42 Fusion Bonding in the BA300UHP Wafers are loaded and vacuum held against SiC chucks Chucks and the vacuum or pressure, that can be controlled between the chuck and the backside of the wafer, “engineers” the shape of the bonding surface The chucks are used to align and bring the wafers into contact The chucks are also used to engineer the bond wave from center to edge using RPP (Radial Pressure Propagation). Click icon for RPP Presentation XBC300 Wafer Bonder RPP (Radial Pressure Propagation) in the BA300UHP Aligner Module
  43. 43. 43 Si C Chuck & Tool Fixture (Patent Pending) Transports aligned pair from BA300 to CB300 Delivers reproducible submicron alignment capabilities Maintains wafer to wafer alignment throughout all process and transfer steps No exclusion zone required for clamping Maintains alignment accuracy through temperature ramp Chuck CTE matches Si CTE Increases throughput by reduction of thermal mass
  44. 44. 44 CB300 Bond Chamber Module Production Requirement Closed Bond Chamber Contamination Free Open chamber lid introduces air- turbulence and particles into bond chamber Uniform heat Open chamber lid causes temperature gradient between the front and back 3 Post Superstructure takes force, not bond chamber Chamber lid is the structural force carrying element in clam shell design– this causes force distortion Safety Opening chamber lid exposes user to high temperatures
  45. 45. 45 CB Chamber Force Uniformity Excellent Force Uniformity Within ±5% pressure uniformity Patented Pressure Column Technology for up to 90kN of bond force Load Cell Verification Bond Force options Standard: 3kN to 60kN High Force Option: 3kN to 90kN Traditional PistonTraditional Piston Bond- Interface SUSS Pressure Column TechnologySUSS Pressure Column Technology
  46. 46. 46 CB Chamber Thermal Design Superior Thermal Performance Within ±1.5% temperature uniformity Fast ramp (to 30°C/min) and cool rate (to 20°C/min) Matched top and bottom stack assemblies Perfect symmetry Multi-zone, vacuum-isolated heaters Dramatically reduces hot spots and burnouts Eliminates edge effects
  47. 47. 47 CB Chamber Structural Design Best-in-Class Post Bond Alignment ±1.5µm post bond alignment for metal bonds Rigid superstructure Solid alignment stability High planarity silicon carbide chucks Maintains long term planarity for superior post-bond alignment accuracy
  48. 48. 48 CP300 Cool Plate Module Fixture and wafer cooling Unclamp, unload, and optional fixture load Queuing and buffer station for fixtures and wafers
  49. 49. 49 CL300 Wafer Cleaning Module for Fusion Bonding Wet spin process for wafer cleaning Twin ultrasonic head IR Assisted Drying NH4OH chemistry Simultaneous clean, mechanical align and bond two wafers Bond initiation integrated into CL300 Closed process chamber for maximum particle protection Rated for particle sizes down to 100nm Design based on CFD (computational fluid dynamic) modeling Example of KLA data w/ no adders down to 100nm CFD modeling of chamber
  50. 50. 50 PL300 Plasma Activation Module for Fusion Bonding Cleaning & surface conditioning for fusion bonding Simple operation with plasma activation times in <30 seconds Enables high bond strength at low annealing temperatures Vacuum chamber based plasma system Uniform glow plasma Power supply options for frequency and power level Ex: 100kHz/300W; 13.56MHz; 2.4GHz Automatic tuning Input gases with up to 4 MFCs Radially designed high conductance plenum and vacuum system
  51. 51. 51 Summary Anodic and Frit based bond processes are not suitable for advanced wafer level packaging processes Challenges with mobile ions (anodic) and footprint, accuracy (frit) Metal bonding processes are being implemented as the next generation solution Although metal bonding processes have many advantages over frit and anodic approaches they also require much more from the process equipment For example much more stringent specs for force and thermal control Process equipment proven to satisfy these requirements has been presented