FPGA Design with Python and MyHDL

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These are the slides from a talk I gave at the ALL PROGRAMMABLE PLC2 Days 2014 conference in Stuttgart, Germany.

Published in: Engineering, Technology, Design

FPGA Design with Python and MyHDL

  1. 1. 21.05.2014 1 FPGA Design with Python and MyHDL Guy Eschemann
  2. 2. 21.05.2014 2 Content • About us • A short introduction to Python • Introduction to MyHDL • Demo • Questions
  3. 3. 21.05.2014 3 About noasic • Quick Facts – Founded in 2014 – 14+ years experience in FPGA design – Located in Kehl, Germany • Areas of expertise – FPGA & IP core design and verification – VHDL code generators
  4. 4. 21.05.2014 4 VHDL Code Generators (1)
  5. 5. 21.05.2014 5 VHDL Code Generators (2)
  6. 6. 21.05.2014 6
  7. 7. 21.05.2014 7 A short introduction to
  8. 8. 21.05.2014 8 Python • Created 1991 by Guido van Rossum at CWI (Netherlands) • General-purpose, high-level programming language • Emphasizes code readability • Write less code • Strongly, dynamically typed • Object-oriented • Open-source • Runs on many platforms
  9. 9. 21.05.2014 9 Sample Python code
  10. 10. 21.05.2014 10 Python – Syntax • Blocks are specified by indentation • No mandatory statement termination • Comments start with # • Assign values using = • Test equality using == • Increment/decrement using += or -=
  11. 11. 21.05.2014 11 Python – Data Structures • Lists – like one-dimensional arrays • Tuples – immutable, one-dimensional arrays • Dictionaries – associative arrays („hash tables“)
  12. 12. 21.05.2014 12 Python – Strings • Can use either single or double quotation marks • Multi-line strings enclosed in triple quotes • Use modulo (%) operator and a tuple to format a string
  13. 13. 21.05.2014 13 Python – Flow Control • Flow control statements: – if – for – while – there is no case/switch. Use „if“ instead.
  14. 14. 21.05.2014 14 Python – Functions • Declared with the „def“ keyword • Optional parameters supported • Functions can return multiple values
  15. 15. 21.05.2014 15 Python – Importing • External libaries (such as MyHDL) must be imported before they can be used: from myhdl import intbv OR from myhdl import *
  16. 16. 21.05.2014 16 Python Libraries • String handling • Regular expressions • Random number generation • Unit-test framework • OS interfacing • GUI development • Modules for math, database connections, network interfacing etc. • Hardware design (MyHDL)
  17. 17. 21.05.2014 17 Introduction to
  18. 18. 21.05.2014 18 MyHDL • Python-based hardware description language • Created 2003 by Jan Decaluwe • Open source
  19. 19. 21.05.2014 19 Why MyHDL? • Write less code • Avoid common VHDL and Verilog pitfalls • Apply modern SW development techniques to HW design • Can generate both VHDL and Verilog • Simulator included • Open source • Runs on many platforms (Windows, OSX, Linux) • Python ecosystem
  20. 20. 21.05.2014 20 What MyHDL is not • Not a way to turn arbitrary Python into silicon • Not a radically new approach • Not a synthesis tool • Not an IP block library • Not only for implementation • Not well suited for accurate timing simulations
  21. 21. 21.05.2014 21 MyHDL Design Flow
  22. 22. 21.05.2014 22 Example – 8 bit counter
  23. 23. 21.05.2014 23 Modeling Components • Components are modeled using functions • Function parameters map to ports
  24. 24. 21.05.2014 24 Modeling Processes • Processes are modeled using special „generator“ functions • Decorators are used to create generator functions
  25. 25. 21.05.2014 25 The @instance decorator • Most general, creates generator from a generator function a 1 0b z
  26. 26. 21.05.2014 26 The @always decorator • Abstracts an outer „while True“ loop followed by a „yield“ statement a 1 0b z
  27. 27. 21.05.2014 27 Combinational logic: @always_comb • Automatically infers the sensitivity list a 1 0b z
  28. 28. 21.05.2014 28 Sequential logic: @always_seq • Infers the reset functionality • Equivalent code:
  29. 29. 21.05.2014 29 Function Decorators • @instance: most general, multiple yields • @always: single yield, abstracts „while True“ loop • @always_comb: for asynchronous logic, automatically infers sensitivity list • @always_seq: for sequential logic, automatically infers the reset functionality
  30. 30. 21.05.2014 30 MyHDL Signals • Similar to VHDL signals • Signal declaration: s_empty = Signal(0) s_count = Signal(intbv(0)[8:]) s_clk = Signal(bool(0)) • Signal assignment: s_count.next = 0
  31. 31. 21.05.2014 31 MyHDL intbv class • Similiar to standard Python „int“ type with added indexing and slicing capabilities • intbv = „integer with bit-vector flavor“ • Provides access to underlying two‘s complement representation • Range of allowed values can be constrained
  32. 32. 21.05.2014 32 MyHDL intbv creation Create an intbv: intbv([val=None] [, min=None] [, max=None]) Example: >>> a = intbv(24, min=0, max=25) >>> a.min 0 >>> a.max 25 >>> len(a) 5
  33. 33. 21.05.2014 33 MyHDL intbv indexing and slicing Indexing: >>> a = intbv(0x12) >>> bin(a) '10010' >>> a[0] False >>> a[1] True Slicing: >>> a = intbv(0x12) >>> a[4:0] intbv(2L)
  34. 34. 21.05.2014 34 MyHDL intbv creation Create an intbv, specifying its width: >>> a = intbv(24)[5:] >>> a.min 0 >>> a.max 32 >>> len(a) 5
  35. 35. 21.05.2014 35 Modeling hierarchy
  36. 36. 21.05.2014 36 Generated VHDL code
  37. 37. 21.05.2014 37 Verification • Verification is MyHDL´s strongest point • Arguably the hardest part of hardware design • There are no restrictions for verification: can use the full power of Python • Can do „agile“ hardware design • The Foundation is an event-driven simulator in the MyHDL library
  38. 38. 21.05.2014 38 MyHDL Simulator
  39. 39. 21.05.2014 39 A basic MyHDL simulation
  40. 40. 21.05.2014 40 Debugging in MyHDL • Regular Python debugging • Waveform viewer output
  41. 41. 21.05.2014 41 Conversion • A subset of MyHDL can be automatically converted to VHDL and Verilog • The converter maintains the abstraction level • Supports some unique MyHDL features • Creates readable VHDL/Verilog • Convertible subset much broader than synthesizable subset
  42. 42. 21.05.2014 42 Conversion example • MyHDL Code • Conversion to Verilog • Conversion to VHDL • The converter does the casts and resizings automatically
  43. 43. 21.05.2014 43 User-defined code
  44. 44. 21.05.2014 44 Demo
  45. 45. 21.05.2014 45 Caveats • Dynamic nature of Python needs some getting used to • Error messages can be cryptic • Cannot import legacy VHDL/Verilog code – Write own behaviorals models for simulation – Use user-defined code for conversion • Cannot generate parameterizable HDL code
  46. 46. 21.05.2014 46 MyHDL future • Fixed-point support in the converter • Interfaces • Python 3.0 support
  47. 47. 21.05.2014 47 Resources • http://python.org • http://myhdl.org – Manual & examples – Download & installation instructions – Mailing list – Tutorials & publications • @MyHDL on twitter • Development with mercurial on Bitbucket
  48. 48. 21.05.2014 48 Contact Guy Eschemann noasic GmbH Sundheimer Feld 6 77694 Kehl guy@noasic.com http://noasic.com Twitter: @geschema

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