computer architecture

1. Architects Look to Processors of Future
Applications, Instruction Sets, Memory Bandwidth Are Key Issues
Presented By:
Deepika Kamboj
P21CS008

2. OBJECTIVE
In this paper, author has asked several processor architects based on their experience
and also 25 years of history that where they see the microprocessor continuing to
evolve in the future. Their responses discuss several technical barriers to success and
how they might be overcome.

3. GORDON BELL
Chester Gordon Bell (born August 19, 1934) is an American electrical engineer and manager. He spent 23 years
at Digital Equipment Corporation (part of HP) as Vice President of Research and Development. He was the
architect of various mini- and time-sharing computers

4. GORDON BELL
• In 1947: Idea of stored programs and transistors
• In 1960: Interconnecting transistors on silicon substrates
• In 1971: The development of the microprocessor
• It is safe to predict computers in 2047 will be at least 100,000 times more powerful.
• This goal is likely to be reached in half the time.

5. GORDON BELL Moore’s Law

6. Performance Prediction

7. GORDON BELL
• do what I say
• don’t expect computers to interface by taste and smell.
• By 2047, commercial areas, and factories will have useful robots
• New computer classes based on price will continue to be determined with three factors:
hardware platform technology, hardware/software interfaces, and network infrastructures
What Forms Will the Future Computer Take?

8. GORDON BELL
Computer Classes based on three factors

9. GORDON BELL
• Scalable networks and platforms
• underlying parallelism is a challenge
• Will computers interface with humans biologically, rather than in the superficial, mechanical
way they do now?

10. RICHARD SITES
Richard Sites is a computer architect, software engineer, and professor of computer science who is considered to
be one of the fathers of computer architecture and is known for co-architecting the Digital Equipment Corporation
Alpha computers.

11. RICHARD SITES
• In 1988, We estimated relatively modest 32% per year compounded performance
improvement
In 1992,
CPU clock speed: 200 MHz
Issue width: 2
Number of CPUs: 1

12. RICHARD SITES
How we can improve the performance using:
1. CPU clock speed: Chip Designer
2. Instruction-issue width: Chip Designer + Compiler
3. Processors: Multithreaded Operating System

13. RICHARD SITES
What will happen across the industry in the next 4–5 years?
•Next five years to effectively support something beyond six- issue—perhaps 8 or 10 instructions
per cycle
• Growing emphasis in the software industry on multi- threaded programs.
•Place multiple processors on single chip.

14. WILLIAM DALLY
William Dally, PhD, is a computer scientist who invented hardware architectures that provides
parallel computing, modern supercomputers, and artificial intelligence as we know it today.

15. WILLIAM DALLY
• In 2006, Parallel instruction sets
Adding issue slots is advantageous as long as the incremental speedup of the last slot is greater than 0.1%. If we use a
32-issue processor (with a few spare slots for yield) on such a chip then a 32nd issue slot would be worth while even if it
only increases the average issue rate from 9.9 to 10.
• Memory-Centric Computers.
• Processors will be integrated on the same chip as memory.
What will a microprocessor look like in 10 years?

16. DAVID DITZEL
DAVID DITZEL is the president and CEO of ThruChip Communications, a startup company with breakthrough
technology to make semiconductor systems smaller, lower power, and lower cost by stacking chips in 3D using near-
field wireless communication. Previously, he was the vice president of Hybrid Parallel Computing at Intel.

17. DAVID DITZEL
• Upcoming Technical Battles
DRAM vs. Microprocessors
x86 Dominates
Multimedia Accelerators vs. Microprocessors
New Instruction Sets vs. Compatibility (VLIW)
Single-Chip Multiprocessors vs. Uniprocessors
Wires vs. Gates

18. YALE PATT
Yale Nance Patt is an American professor of electrical and computer engineering at The University of Texas at
Austin. In 1965, Patt introduced the WOS module, the first complex logic gate implemented on a single piece of
silicon

19. YALE PATT
• Challenge: Billion Transistors on single chip
• Design issue: Cost or Performance
• If design issue is cost: keep on integrating
• If design issue is performance:
partitioning problem
First, Let’s Get the Uniprocessor Right

20. Thank You