1. Ultra-High-Q Air-Core Slab Inductors for On-Chip Power Conversion
Naigang Wang, David Goren, Eugene O’Sullivan, Xin Zhang, William J. Gallagher, Philipp Herget and
Leland Chang
IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY 10598
E-mail: nwang@us.ibm.com ; Phone: (914) 945-2663
Abstract
Air-core slab inductors with specially designed
current return paths are proposed to achieve the
ultra-high Q required for on-chip power delivery
and management at >90% efficiency. Uniquely op-
timized for buck converter circuits, this CMOS-
compatible structure avoids the challenges of thin-
film magnetics. Q~25-30 at 200-300MHz is exper-
imentally demonstrated.
Introduction
The power efficiency of VLSI products today
strongly depends on the ability to perform on-chip
power conversion at high efficiency. Such integrat-
ed voltage regulation circuits enable fast, fine-grain
dynamic voltage scaling for efficient power man-
agement, high-voltage step-down conversion for
efficient power delivery, and on-chip voltage gen-
eration to contain system supply proliferation. Mi-
croprocessor products today use linear regulators
[1], which can be integrated on chip, but are fun-
damentally inefficient for large conversion ratios,
or buck converters with package-integrated induc-
tors [2], which achieve acceptable efficiency, but
are not fully on-chip. For mainstream applications
that may reach beyond 100W thermal design power
(TDP), it is desirable to achieve >90% efficiency at
~A/mm2 power densities in a fully integrated buck
converter – a goal thus far limited by on-chip in-
ductor Q.
With ~nH on-chip inductances, very high fre-
quencies (VHF) in the ~100MHz range are needed
for on-chip power conversion to balance output
current ripple with FET losses [3]. Traditional air-
core spiral inductors exhibit low Q at these fre-
quencies due to on-chip metal thickness constraints
(~10um), which has limited demonstrated efficien-
cies to ~70% [4]. In recent years, significant re-
search has focused on improving inductor Q~ωL/R
by integrating thin-film magnetics [5]; however, to
date, converter efficiencies with such materials
have still been <80% [6].
In this work, we clarify the power inductor re-
quirements for practical on-chip voltage conversion
circuits and highlight the challenges of thin-film
magnetic-based inductors. We propose and demon-
strate a new air-core slab structure with ultra-high
Q, suitable for chip-scale buck converters at >90%
efficiency.
Inductor Design for High-Efficiency Buck Converters
Fig. 1 shows that with an aggressive 90% tar-
get, MOSFET losses limit switching frequencies to
<500MHz. On the other hand, >10MHz is desir-
able to balance efficient continuous conduction
mode operation, ~A/mm2 output current density,
~ns transient response, and achievable on-chip in-
ductance density. In this frequency regime with nH
inductances, FET-related loss imposes an upper
limit of ~7% inductor loss (an optimistic bound as
interconnects and control circuits contribute addi-
tional losses).
Figure 1. Simulatedefficiency without inductor loss for a 2V-to-1V buck
convertersupplying1A DC loadcurrent using32nmCMOStechnology. (a)
maximum efficiency achieved by optimizing switch sizes; (b) required in-
ductance to enable buck converter operation at the DCM/CCM boundary.

2. In a buck converter, the inductor carries a DC-
biased triangle wave current (Fig. 2). Inductor effi-
ciency as expressed by Eq. (1) is comprised of DC
wire resistance (Rdc), AC skin effect resistance
(Rac), and magnetic loss (Rac_mag), which is zero for
air-core inductors). Equation (5) shows that induc-
tor efficiency strongly depends on r, the ratio be-
tween AC current ripple and DC current, and k, the
fraction of total inductor resistance that is DC re-
sistance. Buck converters achieve optimum effi-
ciency at continuous vs. discontinuous conduction
mode boundary [7], which implies r=2. The high
required Q value is alleviated with smaller k (Fig.
3).
For air-core inductors, Racω0.5 enables contin-
uous Q improvement up to self-resonance, which is
generally beyond the frequency range of interest
(Fig. 4a). For magnetic inductors, Rac_mag often
dominates, such that a peak Q exists due to the
nonlinearity of magnetic eddy current loss (ω2)
and excess loss (ω2 or ω1.5) [8]. For Rac_magω2,
Qpeak occurs when Rac=Rdc at k=0.5 (Fig. 4b).
Normalization of Eq. (1) yields a Qpeak requirement
for magnetic inductors of >17 to achieve ~5% in-
ductor loss (Fig. 5). This is higher than results pub-
lished to date even with new materials and com-
plex lamination layers (Fig. 6). Significant ad-
vancements in magnetics and inductor design are
thus needed.
Figure 2. (a)Buck converter and(b) current in inductor. Inductorefficiency
is definedas the buck converter efficiency considering only inductor loss.
Figure 3. Requiredinductor Q for93% and95% inductorefficiencywhen
D=0.5.
Figure 4. Inductor Q as functionas frequency for (a)air coreinductor,where
Q increases until self-resonance; and (b) magnetic inductor where peak Q
occurs when Rac=Rdc , i.e. k=0.5.

3. Figure 5. Inductor efficiencyas function as Qpeak formagneticinductors and
required magnetic inductor Qpeak for 93% and 95% inductor efficiency
Figure 6. Comparisonof requiredmagnetic Qpeak (consideringswitchlosses
in Fig. 1) with reportedmagnetic inductors peakQ, excludingnon-CMOS-
compatible inductors (e.g. MEMSdimensions,high temperature processing).
It shouldbe notedthat the circledpoint at ~10MHz uses a large number of
wire turns to achieve ~uH inductance,which maybe toohigh for fast transi-
ent response in on-chipapplications [9-24].
Ultra-High-Q Air-Core Slab Inductors
Air-core inductors, however, can be designed
for sufficient Q by minimizing Rdc via use of a
wide (~200um), thick (~10 um) slab, and by spe-
cially designed, low-resistance inductive return
paths on either side of the slab (Fig. 7). With a re-
turn path separation distance of 200-300um, ~nH
inductance can be achieved. This structure main-
tains a similar inductance to traditional spiral in-
ductors due to the return path loop, but Rdc is im-
proved as load current need only flow through the
slab (Fig. 8). To minimize impedance, DC return
current will flow via the least resistive path
(ground near the load), whereas AC return current
will flow through the two designed return paths
(Fig. 9). This structure thus achieves lower k and
higher Q as compared to a spiral inductor.
Figure 7. Basic slab inductor structure with two metal layers
Figure 8. Spiral inductorvs. slabinductorwith inductive return
Figure 9. Schematic of DC and AC return paths
The slab inductor can be built in a CMOS back-
end process (Fig. 10) by designing the structure in
a thick metal layer (or multiple layers tied togeth-
er). The return paths can reside in the same layer as
the slab or in existing layers such as in the chip
power grid. In the latter case, however, openings
must be cut away from the power grid to ensure
that return currents are sufficiently far away in the
desired paths. These openings can take the form of
small slots to minimize power grid disruption (Fig.
11).

4. Figure 10. Fabrication flow for slab inductor
Figure 11. Schematics of slab inductor with slotted ground plane
To experimentally demonstrate the slab struc-
ture, a 10um through-mask electroplated Cu layer
was fabricated above a 5um slotted power grid re-
turn. One end of the slab is shorted to ground with
a via to imitate high capacitive loads for 1-port
characterization. The inductors are 2mm long to
enable high Q, low resistance measurements.
Measured devices demonstrate nearly constant nH-
range inductance and skin-effect-limited resistance
to achieve Q as high as 25-35 at 200-300 MHz
(Fig. 12). Due to high Q (25) and low k (0.25) at
200 MHz, a 96.6% inductor efficiency is achieved
(5). Fig. 12 confirms that a ~200um gap is needed
between the slab and return paths. As compared
with prior work (Table 1), the proposed structure
achieves ultra-high Q at an inductance density suit-
able for this application, and both inductance and Q
can be further improved through coupling.
Using an analytic model of the slab structure
calibrated both to experimental results and FEM
simulation (Fig. 13), simulated buck converter de-
signs in 32nm CMOS demonstrate >90% conver-
sion efficiency for ~2:1 conversion ratios (Fig. 14).
Figure 12.Measured(a)inductance, (b) resistance and (c) Q of slab induc-
tors with 200um and300um gaps between slabandreturnpaths, respective-
ly. As a reference, slab above a no-opening power grid is also shown.
Figure 13. (a)Inductormodel; and FEM simulated, network modeled and
measured (b) inductance and (c) resistance of a slab inductor.

5. Figure 14. Simulated32SOI buck converter design using a calibrated open
slab inductor model demonstrating >90% efficiency for ~2:1 conversion.
Table 1. Comparedwith prior art, the slabinductorcan achieve ultra-high Q
for on-chip power conversion in a simple BEOL process.
Conclusion
We have proposed and demonstrated an air-core
slab structure to achieve ultra-high Q on-chip in-
ductors to enable high-efficiency integrated power
conversion. The device can be incorporated into a
CMOS back-end process and avoids challenges
associated with the integration of magnetic materi-
als.
Acknowledgement
Device fabrication performed at the Microelec-
tronics Research Laboratory in Yorktown Heights,
NY.
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