NXP i.MX 6SoloLite Boot from SD/MMC
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This documentation is about i.MX 6SoloLite GPIO Boot overrides for SD/eMMC Booting.
![System Boot
The boot process begins at Power On Reset (POR) where the hardware reset logic
forces the ARM core to begin execution starting from the on-chip boot ROM.
Boot ROM code uses the state of the internal register BOOT_MODE[1:0] as well as the
state of various eFUSEs and/or GPIO settings to determine the boot flow behavior of
The device.
The main features of the ROM include:
‧ Support for booting from various boot devices
‧ Device configuration data (DCD) and plugin
‧ Digital signature High Assurance Boot (HAB)
‧ Wake-up from low power modes
The boot ROM supports the following boot devices:
‧ NOR Flash
‧ OneNAND Flash
‧ SD/MMC
‧ Serial (I2C/SPI) NOR Flash and EEPROM](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
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NXP i.MX 6SoloLite Boot from SD/MMC
- 1. NXP i.MX 6SoloLite System Boot from SD/ eMMC Devices Daniel Chiu 2017/6/28 Mobile: +886-928-282-503 daniel.chiu@sacsystem.com.tw
- 2. System Boot The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. Boot ROM code uses the state of the internal register BOOT_MODE[1:0] as well as the state of various eFUSEs and/or GPIO settings to determine the boot flow behavior of The device. The main features of the ROM include: ‧ Support for booting from various boot devices ‧ Device configuration data (DCD) and plugin ‧ Digital signature High Assurance Boot (HAB) ‧ Wake-up from low power modes The boot ROM supports the following boot devices: ‧ NOR Flash ‧ OneNAND Flash ‧ SD/MMC ‧ Serial (I2C/SPI) NOR Flash and EEPROM
- 3. Boot MODE Pin Setting BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the rising edge of POR_B. After these inputs are sampled, their subsequent state does not affect the contents of the BOOT_MODE internal register.
- 4. Serial Downloader (BOOT_MODE[1:0] = 0b01) The Serial Downloader provides a means to download a Program Image to the chip over USB serial connection In this mode the ROM programs WDOG1 for a 90-second time-out if DOG_ENABLE eFuse is 1 and continuously polls for USB connection. If no activity is found on USB OTG1 and the watchdog timer expires, the ARM core is reset.
- 5. Internal Boot (BOOT_MODE[1:0] = 0b10) When set to internal boot, the boot flow may be controlled by a combination of eFUSE settings with an option of overriding the fuse settings using General Purpose I/O (GPIO) pins. The GPIO Boot Select FUSE (BT_FUSE_SEL) determines whether the ROM uses GPIO pins for a select number of configuration parameters or eFUSEs in this mode. If BT_FUSE_SEL = 1, all boot options are controlled by the eFUSEs If BT_FUSE_SEL = 0, specific boot configuration parameters may be set Using GPIO pins rather than eFUSEs.
- 7. i.MX 6SoloLite MMC/eMMC and SD/eSD Boot Devices All USDHC ports support eMMC4.3 and eMMC4.4 fast boot.
- 10. BOOT_CFG1[4]: Fast Boot Support
- 11. BOOT_CFG1[3:2]: SD/MMC Speed Mode
- 12. BOOT_CFG1[1]: SD Power Cycle Enable
- 13. BOOT_CFG1[0]: SD Loopback Clock Source Selection
- 14. BOOT_CFG2[7:5]: Bus Width/SD Calibration Step
- 15. BOOT_CFG2[7:5]: Bus Width/SD Calibration Step (cont.)
- 17. BOOT_CFG2[4:3]: Port Selection (cont.)
- 19. BOOT_CFG2[1]: SD2 Voltage Selection
- 20. IOMUX Configuration for SD/MMC
- 21. Boot Devices for i.MX 6SoloLite Evaluation Kit
- 22. Booting from SD on the i.MX 6SoloLite EVK board
- 23. i.MX 6SoloLite MMC/eMMC and SD/eSD Boot Devices All USDHC ports support eMMC4.3 and eMMC4.4 fast boot.