This document discusses strategies to achieve low power dissipation in integrated circuits. It discusses several techniques:
1) Reducing dynamic power by minimizing transistor sizes, lowering supply voltage, and optimizing manufacturing processes.
2) Reducing static power by lowering subthreshold leakage through multiple threshold voltages and separating logic into high and low power groups.
3) Introducing a new logic style called Energy Economized Pass Transistor Logic (EEPL) that provides reductions in power and delay compared to other pass transistor logic styles like CPL and SRPL through regenerative feedback.
4) EEPL has been shown to perform well in combinational and sequential circuits like multipliers and counters with advantages of lower energy consumption.
2. STRATEGIES TO ACHIEVE LOW
POWER DISSIPATION
dynamic power dissipation is directly proportional to
activity factor(α),switching capacitance(c),frequency(f),and
the supply voltage (vdd).
Suitable manufacturing process reduces dynamic power.
Choose minimized transistors with narrow channel widths
Select lower vdd.
Choosing constant field scaling which provides a cubical
improvement in dynamic power for a given function.
Static power dissipation can be reduced by reducing the
subthreshold leakage.
3. CONTD…
A variation on adjusting power supplies is to divide the
logic into high-speed and low-speed power groups run
from separate power supplies.
Choose multiple threshold voltages to operate in critical
and non-critical paths to eliminate the subthreshold
leakage.
Dual-supply rails embedded in each logic cell so that the
fast logic is connected to the high supply and slow is
connected to the low supply.Level converters have to be
inserted between the two styles of logic.For LOW vdd to
HIGH vdd CVSL inverter/buffer circuit can be used.
4. CONTD….
Good floor planning reduces the number of long
wires in a system which reduces the parasitic
capacitance and resistances.
ACTIVITY FACTOR: CMOS- typically 0.1 ,
dynamic logic - 0.5, clock- 1.
Pass transistors are used in lower power
applications.where as dynamic and pseudo-nMOS
gates appear attractive because they eliminate the
bulky pMOS transistors tha account for 2/3 of the
gate width in CMOS logic.
5. EEPL[ENERGY ECONOMIZED PASS
TRANSISTOR LOGIC]
The pass transistor logic has become commonplace in
high speed and low power digital systems.
A new method for digital circuits EEPL is proposed by
adopting the principle of regenerative positive
feedback with pMOS switches.
Reduction in power and delay products when
compared with CPL and SRPL.
To restore the output level,however, level restoration
blocks(LRB) are used.
7. Contd….
EEPL structure is composed of “two inverters and two
minimum-size pMOS switches”.
As one of the input of LRB is always ‘low’one of the
pMOS switch turn on,and then the level of the other is
restored into the full range.
Because of “regenerative positive feedback, the average
delay is shorter than that of CPL”. (fig a)
The energy is smaller than that of both CPL and SRPL
independent of the W/L ratio of FB. (fig b)
10. Contd….
The area of the SRPL is larger than that of EEPL from
the fig 4…
Shows the energy variation of each logic according to
the change of load capacitance and W/L ratio of FB.
Thus the EEPL has the minimum value, when the load
capacitance are the same. Thus it is called “energy
economized pass transistor logic(EEPL)”
In combinational and sequential circuits the EEPL
performed by the usage of higher –bit data compressor
without using the modified booth’s logical designs.
11. Contd….
Comparison of the full-adder performance in each
pass transistor logic. For m=1 or 3 the table is given
with respect to the fundamental parameters as….
15. Advantages:
» consumes less energy compared to CPL & SRPL.
» usefull for high speed and low power digital circuits.
Applications:
» combinational circuits & sequencial circuit.
