Ch05

CSC 3650 Introduction to Computer Architecture
Time: 3:30 to 6:30 Meeting Days: W Location: Oxendine 1237B
Textbook: Essentials of Computer Architecture, Author: Douglas E. Comer, 2005, Pearson Prentice Hall
Spring 2011
Chapter Five
Processor Types and Instruction Sets

Instruction Set
• Set of operations the hardware recognizes
• Representation the hardware uses for each
operation
• The set of operations a processor provides
represents a tradeoff among the copst of the
hardware, the convenience for a
programmer, and engineering
considerations such as power consumption

Flowchart to execute assembly language program

Variable-Length vs Fixed-Length Instructions
• Variable-Length
– Makes optimal use of memory
– Requires complex hardware to decode
• Fixed-Length
– Requires less complex hardware
– Processor can operate at higher speeds
• Can fetch and decode instruction without examining
opcode

Registers
• General Purpose
– Fixed size
– Supports fetch and store
– Acts as temporary storage facility
– Small number of registers, < 100
– Usually large enough to hold an integer
• Processor does 32 bit arithmetic, registers have 32
bits
– Numbered from 0 to N-1

Registers
• Programming with Registers
– Operands stored in general purpose registers
– Place results in general purpose registers
– Must move value to registers and from registers
• load a copy of X into register 3
• Load a copyh of Y into register 6
• Add the value in register 3 to the value in register 6
and place the result in register 7
• Store a copy of the value in register 7 in Z

From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
• Operands from an instruction must come from different banks

• Since operands must come from different banks, this
presents a problem
• X and Y must be in separate banks
• Z and X must be in different banks
• So either Y or Z will have to be moved to complete T

Complex and Reduced Instruction Sets
• Complex Instruction Set Computer (CISC)
– Includes many instructions (hundreds)
– Each instruction can perform an arbitrarily
complex computation
– Intel’s Pentium is CISC
• Provides hundreds of instructions
• Complex instructions that require a long time to
complete
• Instructions that manipulate graphics in memory,
instructions to compute sine and cosine functions

Complex and Reduced Instruction Sets
• Reduced Instruction Set Computer (RISC)
– Minimum set of instructions sufficient for all
computations, around 32
– Each instruction performs a basic computation
– Instructions are fixed size
– Execute instruction in one clock cycle
– Motorola’s MIPS processor, had 32 instructions
and each takes only one clock cycle

Although a RISC processor cannot perform all steps of the
fetch-execute in a single clock cycle, an instruction pipeline
with parallel hardware provides approximately the same
performance once the pipeline is full, one instruction
completes on every clock cycle
Fetch
instruction
Examine
opcode
Fetch
operands
Perform
operations
Store
results

Fetch
instruction
Examine
opcode
Fetch
operands
Perform
operations
Store
results

Other Causes of Stalls
• Any instruction that delays processing or
disrupts the normal flow
– Accesses external storage
– Invokes a coprocessor
– Branches to a new location
– Calls a subroutine

Delay D  subtract E C until C is available

Add a feature to the processor to detect the stall
Sends the output from Instruction K directly to Instruction K + 1

Types of Operations
• Instructions are divided into basic
categories
– Arithmetic instructions (integer arithmetic)
– Logical instructions (also called Boolean)
– Data access and transfer instructions
– Conditional and unconditional branch
instructions
– Floating point instructions
– Processor control instructions

Data movement instructions for
the 8085 microprocessor

Data Operation instructions for
the 8085 microprocessor

Program Control instructions
for the 8085 microprocessor

Program Counter, Fetch-Execute, and Branching
• Program counter: used to store the location
of the next instruction in memory
• Start the fetch-execute cycle by getting the
address of the next instruction in memory
from the program counter
• Once the instruction is fetched, update
program counter

Algorithm used to move through the fetch-
execute cycle
Assign the program counter an intial program address. Repeat forever {
Fetch: access the next step of the program from the location given by
the program counter.
Set an internal address register, A, to the address beyond the
instruction that was just fetched
Execute: Perform the step of the program
Copy the contents of address register A to the program counter

Subroutine Calls, Arguments, and Register Windows
• Two basic methods to pass parameters
– Store them in memory, eg, put on a stack
• Could be slow
– Use registers
• Faster, but limited number which may cause conflict
with operands
• Could use a register window
– Subset of registers used to pass parameters

• Registers are numbered from 0 through the window size – 1
• Program places the parameters in registers 4 – 7
• Subroutine gets the parameters from its registers 0 – 3
• xi only available to main program, In only to subroutine

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