8086 instruction set (with simulator)

8086
Addressing Modes
Instruction Format
Instruction Set
Interrupts
D. Aswini
Assistant Professor

Introduction
4
Program
A set of instructions written to solve a problem.
Instruction
Directions which a microprocessor
follows to execute a task or part of a
task.
Computer language
High Level Low Level
Machine Language Assembly Language
 Binary bits
 English Alphabets
 ‘Mnemonics’
 Assembler Mnemonics 
Machine Language

Addressing Modes
Every instruction of a program has to operate on a data.
The different ways in which a operand is denoted in an
instruction are known as addressing modes.

Opcode and Operand in 8086
An opcode is a short of “operation code”
An opcede is a singe instruction can be executed by the CPU.
In machine language it is a binary or hexadecimal value such as B7
loaded into the instruction register.
In assembly language mnemonic form an opcode is a command such as
MOV or ADD or JMP.
Example:
• MOV AX, 1000H ; MOV is the opcode.
AX- Destination operand
1000H- source operand

Addressing modes in 8086
Register Addressing
Immediate Addressing
Direct Addressing
Register Indirect Addressing
Based Index Addressing
Register Relative Addressing
Relative based Index Addressing

Register Addressing
• The instruction will specify the name of the register which
holds the data to be operated by the instruction.
Example:
• MOV CL, DH
• The content of 8-bit register DH is moved to another 8-bit
register CL
• (CL)  (DH)
• MOV BX, DX ; copy the contents of DX into BX
• MOV ES, AX ; copy the contents of AX into ES
• ADD AL, BH ; add the contents of BH to contents of AL
Note:
• Source and destination registers must have the same size

Immediate addressing
• In immediate addressing mode, an 8-bit or 16-bit data is specified as
part of the instruction
• The operand comes immediately after the opcode
• For this reason, this addressing mode executes quickly
• Immediate addressing mode can be used to load information into any
of the registers except the segment registers and flag registers.
Example:
1. MOV DL, 08H
• The 8-bit data (08H) given in the instruction is moved to DL
• (DL)  08H
2. MOV AX, 0A9FH
• The 16-bit data (0A9FH) given in the instruction is moved to AX register
• (AX)  0A9FH

Memory Addressing Mode
EFFECTIVE ADDRESS (EA)
The offset of a memory operand is called the operand’s effective address (EA).
Is an 16 bit no. That expresses the operands distance in byte from the beginning
of the segment
8086 has Base register and Index register
So EU calculates EA by summing a Displacement, Content of Base register and
Content of Index register.

Physical Address Calculation
11
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Effective Addreee (Offset Value) (16 bits)
89AB : F012  89AB  89AB0 (89AB x 10 = 89AB0)
F012  F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address/physical address)
Physical Address :
Actual address of a
byte in memory. i.e.
the value which goes
out onto the address
bus.
Memory Address
represented in the
form Seg : Offset
(Eg - 89AB:F012)

Direct Addressing
Here, the effective address of the memory
location at which the data operand is stored
is given in the instruction.
The effective address is just a 16-bit
number written directly in the instruction.
Example:
MOV AX, [2400H]
• The square brackets around the 2400H
denotes the contents of the memory
location. When executed, this instruction
will copy the contents of the memory
location into AX register.
• This addressing mode is called direct
because the displacement of the operand
from the segment base is specified
directly in the instruction.
Address Calculation:
MOV AX, [2400]
move contents of DS:2400H
into AX
The physical address is
calculated by combining the
contents of offset location
2400 with DS

Direct Addressing: Example
MOV CL, [4321H]
• This instruction moves data from location 4321H in the data segment into
CL.
• The physical address is calculated as, Assume DS = 5000H
DS * 10H + 4321
Physical Address = 50000 + 4321 = 54321H
• CL ← [54321H]

Register Indirect Addressing
In Register indirect addressing, name of the
register which holds the effective address (EA)
will be specified in the instruction.
Registers used to hold EA are any of the
following registers:
BX, DI and SI.
Content of the DS register is used for address
calculation.
Example:
MOV AX, [BX]
moves into AX the contents of the memory
location pointed to by DS:BX.
The same rules apply when using register SI or
DI.
Example:
MOV CL, [SI] ; move contents of DS:SI into CL
MOV [DI], AH ; move contents of AH into DS:DI
Example:
MOV AX, [BX]
Assume BX:1234, DS: 1000
DS:BX -> 1000:1234
This instruction moves a
word from the address
pointed by BX and BX + 1 in
data segment into AL and
AH respectively.
calculated as
1000x10+1234=11234H
AL <- [11234h]
AH <- [11235h]

Register Relative Addressing
• In Register relative addressing, the effective address (EA) is the sum of an 8
or 16 bit displacement and the contents of a base register or an Index
register
• Registers used here are BX,BP, DI and SI.
• Content of the DS register is used for address calculation.
• MOV AH, [BX+4]
move contents of DS:BX+4 into AX
Physical Address = DSx10 + BX+4
• MOV CH, [SI+5]
move contents of the DS:SI+5 into CH
Physical Address = DSx10 +SI+5
Example:
MOV AH, [BX+4]
Assume BX:1234, DS: 5000
calculated as
5000x10+1234+4=51238H
AH <- [51238H]
Note: If BP appears in the instruction operand
field, segment register SS is used in address
calculation

Based Indexed Addressing
• In Based Index Addressing, the effective address is computed from the sum of a
base register (BX or BP) and an index register (SI or DI)
• Example:
MOV CH, [BX+SI]
move contents of the DS:BX+SI into CH
Physical Address = DSx10 + BX+SI
Example:
MOV CH, [BX+SI]
Assume BX:1234H,
DS: 5000H SI:0008H
calculated as
50000 (DS:5000*10)
1234
0008
----------
5123C
----------
CH <- [5123CH]

Relative Based Indexed Addressing
• In Register based indexed addressing, the effective address is
computed from the sum of a base register (BX or BP), an index
register (SI or DI) and a displacement.
• Example:
MOV CX, [BX + SI + 0AH]

Relative Based Indexed Addressing

Try it out?
Assume, BX=0158 , DI=10A5, Displacement = 1B57 DS=
2100
Find the effective address and Physical address for the
following:
• MOV AX, [1B57H]
• MOV CL,[BX]
• MOV AH,[BX+1B57H]
• MOV CH,[BX+DI]
• MOV AX, [BX+DI+1B57H]

Branch related addressing modes
• Intrasegment direct
Address is specified directly in the instruction as an 8-bit (or 16-bit)
displacement. The effective address is thus calculated by adding the displacement to
current value of IP. As it is intra-segment, only IP changes, CS does not change. If the
displacement is 8-bit it is called as a Short Branch. This addressing mode is also called as
relative addressing mode.
• Intrasegment indirect
• Address is specified indirectly through a register or a memory
location (in DS only). The value in the IP is replaced with the
new value. As it is intra-segment, ONLY IP changes, CS does
not change.
• Intersegment direct
• The new Branch location is specified directly in the instruction
Both CS and IP get new values, as this is an inter-segment
branch.
• Intersegment Indirect
• The new Branch location is specified indirectly through a
register or a memory location (in DS only). Both CS and IP get
new values, as this is an inter-segment branch.

Introduction
• Instructions are operations performed by the CPU
• An instruction is a statement that is executed at runtime. An x86 instruction statement can
consist of four parts:
• Label (optional)
• Mnemonic- (required)
• Operands (instruction specific)
• Comment (optional)
• Label : is an identifier that is assigned the address of first byte of instruction in which it
appears. It provides symbolic name that can be used in branch instruction.
• Mnemonics: These are the symbolic codes . It specifies the type of operation to be performed
by CPU.
• E.g. MOV, ADD, SUB etc
• Operand: are entities operated upon by the instruction. We can also say it as data on which
operation should act. operands may be register values or memory values. The CPU executes
the instructions using information present in this field.
• It may be 8-bit data or 16- bit data. Ex ADD AX,1000H
• Comment: for commenting the program and may contain any combination of characters
Assembler: it converts the instruction into sequence of binary bits, so that this bits can be read
by the processor.
Label: Mnemonic Operand, Operand ; Comment

Operand - Constants
• Number
• Base is indicated by a suffix
• B- Binary
• D- Decimal
• O- Octal
• H- Hexadecimal
• The default is decimal
• The first digit is Hexadecimal number must be 0 through 9. If most significant
digit is letter A-F, then it should be prefixed with 0.
• Example
• 10012  1011B
• 15010  150D
• 84AF16  84AFH
• FF0016  0FF00H
String
enclosed in single quote(‘)
Ex: ‘welcome’

Instruction Format
For every instruction that is executed in the 8086 microprocessor,
an instruction format is available that is the binary representation of that
instruction.
This instruction format can be coded from 1 to 6 bytes depending upon the
addressing modes used for instructions.

• The general Instruction format that most of the instructions of the 8086 microprocessor
follow is:
• The Opcode stands for Operation Code. Every Instruction has a unique 6-bit opcode. For
example, the opcode for MOV is 100010.
• D stands for direction
If D=0, then the direction is from the register (source)
If D=1, then the direction is to the register(destination)
• W stands for word
If W=0, then only a byte is being transferred, i.e. 8 bits
If W=1, them a whole word is being transferred, i.e. 16 bits
Instruction Format

Mode
R/M
0 0
(Memory Mode
with no
displacement)
0 1
(Memory mode
with 8 bit
displacement)
1 0
(Memory Mode
with 16 bit
displacement)
1 1
(Register Mode)
000 [BX] + [SI] [BX] + [SI] + d8 [BX] + [SI] + d16 AL AX
001 [BX] + [DI] [BX] + [DI] + d8 [BX] + [DI] + d16 CL CX
010 [BP] + [SI] [BP] + [SI] + d8 [BP] + [SI] + d16 DL DX
011 [BP] + [DI] [BP] + [DI] + d8 [BP] + [DI] + d16 BL BX
100 [SI] [SI] + d8 [SI] + d16 AH SP
101 [DI] [DI] + d8 [DI] + d16 CH BP
110 d16 (direct) [BP] + d8 [BP] + d16 DH SI
111 [BX] [BX] + d8 [BX] + d16 BH DI
•The MOD and R/M together is calculated based upon the addressing
mode and register being used in it. This is calculated as follows:
Instruction Format

REG Code Register Selected
0 0 0 AL AX
0 0 1 CL CX
0 1 0 DL DX
0 1 1 BL BX
1 0 0 AH SP
1 0 1 CH BP
1 1 0 DH SI
1 1 1 BH DI
REG stands for register selected. It is a 3-bit code which is calculated as
follows
Instruction Format

Introduction
• The entire group of instructions that a microprocessor
supports is called Instruction Set.
• Classification of instructions
• Data transfer instructions
• Arithmetic instructions
• logical instructions syllabus
• Branch Instructions
• Loop Instructions
• Shift / rotate instructions
• String instructions
• Machine Control Instructions
• Flag manipulation instructions

Data Transfer Instructions
Instruction Description
MOV Moves (Copies) data from register to register, register to memory, memory to
register, memory to accumulator, accumulator to memory, etc.
LDS Loads a word from the specified memory locations into specified register. It also
loads a word from the next two memory locations into DS register.
LES Loads a word from the specified memory locations into the specified register. It
also loads a word from next two memory locations into ES register.
LEA Loads offset address into the specified register.
LAHF Loads low order 8-bits of the flag register into AH register.
SAHF Stores the content of AH register into low order bits of the flags register.
XLAT Reads a byte from the lookup table.
XCHG Exchanges the contents of the 16-bit or 8-bit specified register with the contents
of AX register, specified register or memory locations.
PUSH Pushes (sends, writes or moves) the content of a specified register or memory
location(s) onto the top of the stack.
POP Pops (reads) two bytes from the top of the stack and keeps them in a specified
register, or memory location(s).
POPF Pops (reads) two bytes from the top of the stack and keeps them in the flag
register.
PUSHF Used to copy the flag register at the top of the stack.
IN Transfers data from a port to the accumulator or AX, DX or AL register.
OUT Transfers data from accumulator or AL or AX register to an I/O port identified by
the second byte of the instruction.

MOV Destination, Source
• Copies a word or byte of data from a specified source to a specified destination.
• The destination can be a register or a memory location.
• The source can be a register, a memory location or an immediate number.
• The source and destination cannot both be memory locations.
• They must both be of the same type (bytes or words).
• It does not affect any flag.
Example

Example
AX AH
20
AL
00
BX BH BL
CX CH CL
DX DH DL
MOV BX,AX
AX AH
20
AL
00
BX BH
20
BL
00
CX CH CL
DX DH DL

Example
AX AH AL
BX BH BL
CX CH CL
DX DH DL
50
MOV BL,[5000H]
AX AH AL
BX BH BL
50
CX CH CL
DX DH DL
DS:5000

XCHG Destination, Source
• This instruction exchanges the content of a register with the content of another register
or with the content of memory location(s).
• It cannot directly exchange the content of two memory locations.
• The source and destination must both be of the same type (bytes or words).
• The segment registers cannot be used in this instruction.
• This instruction does not affect any flag.
Example:
• XCHG AX, DX ;Exchange word in AX with word in DX
• XCHG BL, CH ;Exchange byte in BL with byte in CH
• XCHG AL, [5000h] ; Exchange byte in displacement 5000 with the byte in AL

LEA Register, Source
• This instruction determines the offset of the variable or memory location named as the
source and puts this offset in the indicated 16-bit register.
• LEA does not affect any flag.
Example:
• LEA CX, [BX][DI] Load CX with EA = [BX] + [DI]
LDS – LDS Register, Memory address of the first word
• loads new values into the specified register and into the DS register from four successive
memory locations.
• The word from two memory locations is copied into the specified register and the word from
the next two memory locations is copied into the DS registers.
• LDS does not affect any flag.
Example
• LDS BX, [4326] Copy content of memory at displacement 4326H in DS to BL,
content of 4327H to BH. Copy content at displacement of 4328H and
4329H in DS to DS register.

LES – LES Register, Memory address of the first word
• loads new values into the specified register and into the ES register from four successive
memory locations.
• The word from the first two memory locations is copied into the specified register, and
the word from the next two memory locations is copied into the ES register.
• LES does not affect any flag.
Example
• LES BX, [789AH] Copy content of memory at displacement 789AH in DS to BL,
content of 789BH to BH, content of memory at displacement 789CH
and 789DH in DS is copied to ES register.
• LES DI, [BX] Copy content of memory at offset [BX] and offset [BX] + 1 in
DS to DI register. Copy content of memory at offset [BX] + 2 and [BX] + 3
to ES register.

XLAT
• Also known as translate instruction.
• No operand instruction
• The instruction loads AL with the contents of a 20 bit physical address computed from DS, BX
and AL.
• This instruction can be used to read the elements in a table where BX can be loaded with a
16 bit value to point to the starting address (offset from DS) and AL can be loaded with the
element number
• It is used to find out codes in case of code conversion. i.e. it translates code of the key
pressed to the corresponding 7-segment code.
• After execution this instruction contents of AL register always gets replaced.
• No flags are affected.
Example
• Assume DS =0300H, BX =0100H and AL=0DH
After executing XLAT instruction
PA=DS*10+BX+AL
03000+0100+0D= 0310DH
AL [0310D]

LAHF (COPY LOW BYTE OF FLAG REGISTER TO AH REGISTER)
• The LAHF instruction copies the low-byte of the 8086 flag register to AH register.
• This command is used to observe the status of the all conditional flags of flag
register.
• It can then be pushed onto the stack along with AL by a PUSH AX instruction.
• LAHF does not affect any flag.
Example:
LAHF
SAHF (COPY AH REGISTER TO LOW BYTE OF FLAG REGISTER)
• The SAHF instruction replaces the low-byte of the 8086 flag register with a byte from
the AH register.
• SAHF changes the flags in lower byte of the flag register.
Example:
SAHF

IN – IN Accumulator, Port
• The IN instruction copies data from a port to the AL or AX register.
• If an 8-bit port is read, the data will go to AL.
• If a 16-bit port is read, the data will go to AX.
• The IN instruction has two possible formats, fixed port and variable port.
• For fixed port type, the 8-bit address of a port is specified directly in the instruction.
With this form, any one of 256 possible ports can be addressed.
Example
• IN AL, OC8H Input a byte from port OC8H to AL
• IN AX, 34H Input a word from port 34H to AX
OUT – OUT Port, Accumulator
• The OUT instruction copies a byte from AL or a word from AX to the specified port.
• The OUT instruction has two possible forms, fixed port and variable port.
• For the fixed port form, the 8-bit port address is specified directly in the instruction.
• With this form, any one of 256 possible ports can be addressed.
Example
• OUT 3BH, AL Copy the content of AL to port 3BH
• OUT 2CH, AX Copy the content of AX to port 2CH
Data Transfer Instructions - INPUT-OUTPUT INSTRUCTIONS

Data Transfer Instructions : Stack related Instructions
• The stack is a block of memory that may be used for temporarily storing the contents of
the registers inside the CPU.
• It is a top-down data structure whose elements are accessed using the stack pointer (SP)
which gets decremented by two as we store a data word into the stack and gets
incremented by two as we retrieve a data word from the stack back to the CPU register.
• By default, the stack grows downward in memory, so newer values are placed at
lower memory addresses
• The stack is essentially Last-In-First-Out (LIFO) segment
• Stack operation includes , [SP contains the address of the data item currently on top of the
stack]
• Push – writing data on stack – SP is decremented
• Pop – Reading from stack – SP is incremented
• SP contains the offset address of the
memory location in the stack segment.
• Stack Segment register (SS) contains the
base address of the stack segment in the memory.
Stack concept:
https://www.youtube.com/watch?v=1SWr7q121gc

• Push source
• copies a word from a specified source to the location in the stack segment to which the
stack pointer points.
• The source of the word can be register, segment register, or memory.
• The SS and SP must be initialized before this instruction can be used.
• PUSH can be used to save data on the stack.
Example:
• PUSH BX ;Decrement SP by 2, copy BX to stack. (Sp-1 –> BH, SP-1 -> BL)
• PUSH DS ;Decrement SP by 2, copy DS to stack.
• PUSH BL ; Illegal- must push a word

AX AH
20
AL
00
BX BH BL
CX CH CL
DX DH DL
SP 2008
BP
SI
DI XX
XX
SS:2008
SP
00
20
XX
XX
PUSH AX
SS:2008SP
SP -1
SS:2006
SS:2007
AX AH
20
AL
00
BX BH BL
CX CH CL
DX DH DL
SP 2006
BP
SI
DI

Pop destination
• The POP instruction copies a word from the stack location pointed to by the stack
pointer to a destination specified in the instruction.
• The destination can be a register, a segment register or a memory location.
• The data in the stack is not changed.
• After the word is copied to the specified destination, the stack pointer is automatically
incremented by 2 to point to the next word on the stack.
• The POP instruction does not affect any flag.
Example:
• POP DX ;Copy a word from top of stack to DX; increment SP by 2
• POP DS ;Copy a word from top of stack to DS; increment SP by 2

AX AH AL
BX BH BL
CX CH CL
DX DH DL
SP 2006
BP
SI
DI
00
20
XX
XX
SS:2006
SP
00
20
XX
XX
POP BX
SS:2008SP + 2
SP
SP + 1
SS:2006
SS:2007
AX AH AL
BX BH
20
BL
00
CX CH CL
DX DH DL
SP 2008
BP
SI
DI

PUSHF
• The PUSHF instruction decrements the stack pointer by 2 and copies a word in the flag
register to two memory locations in stack pointed to by the stack pointer.
• The stack segment register is not affected.
• This instruction does to affect any flag.
POPF
• The POPF instruction copies a word from two memory locations at the top of the stack
to the flag register and increments the stack pointer by 2.
• The stack segment register and word on the stack are not affected.
• This instruction does to affect any flag.

Arithmetic Instructions
• Instructions of this group perform addition, subtraction, multiplication,
division, increment, decrement, comparison, ASCII and decimal
adjustment etc.

ADD Adds data to the accumulator i.e. AL or AX register or memory locations.
ADC Adds specified operands and the carry status (i.e. carry of the previous stage).
SUB Subtract immediate data from accumulator, memory or register.
SBB Subtract immediate data with borrow from accumulator, memory or register.
MUL Unsigned 8-bit or 16-bit multiplication.
IMUL Signed 8-bit or 16-bit multiplication.
DIV Unsigned 8-bit or 16-bit division.
IDIV Signed 8-bit or 16-bit division.
INC Increment Register or memory by 1.
DEC Decrement register or memory by 1.

NEG Obtains 2's complement (i.e. negative) of the content of an 8-bit or 16-bit
specified register or memory location(s).
CMP Compare Immediate data, register or memory with accumulator, register or
memory location(s).
DAA Decimal Adjust after BCD Addition: When two BCD numbers are added, the DAA is used after
ADD or ADC instruction to get correct answer in BCD.
DAS Decimal Adjust after BCD Subtraction: When two BCD numbers are added, the DAS is used
after SUB or SBB instruction to get correct answer in BCD.
AAA ASCII Adjust for Addition: When ASCII codes of two decimal digits are added, the AAA is used
after addition to get correct answer in unpacked BCD.
AAD Adjust AX Register for Division: It converts two unpacked BCD digits in AX to the equivalent
binary number. This adjustment is done before dividing two unpacked BCD digits in AX by an
unpacked BCD byte.
AAM Adjust result of BCD Multiplication: This instruction is used after the multiplication of two
unpacked BCD.
AAS ASCII Adjust for Subtraction: This instruction is used to get the correct result in unpacked BCD
after the subtraction of the ASCII code of a number from ASCII code another number.
CBW Convert signed Byte to signed Word.
CWD Convert signed Word to signed Doubleword.

• ADD – ADD Destination, Source
• ADC – ADC Destination, Source
• ADD instruction adds the contents of source operand with the contents of
destination operand.
• ADC instruction adds the contents of source operand with the contents of
destination operand with carry flag bit.
• The source may be immediate data, memory location or register.
• The destination may be memory location or register.
• The result is stored in destination operand.
• The source and the destination in an instruction cannot both be memory locations
• The source and the destination must be of the same type (bytes or words).
• Flags affected: AF, CF, OF, SF, ZF.
Example
• ADD AL, 74H Add immediate number 74H to content of AL. Result in AL
• ADC CL, BL Add content of BL plus carry status to content of CL
• ADD DX, BX Add content of BX to content of DX
• ADD DX, [SI] Add word from memory at offset [SI] in DS to content of DX
• ADD AX,[4000H] Add word from memory at displacement 4000h in DS to content of AX

ADD- EXAMPLE
ADD AL,BL
1
AL  E2
BL  2E
-----------------------
CY1, AL 10
------------------------
ADC CL,AL
CL  F1
AL  10
CY 01
-----------------------
CY1 , CL02
------------------------
ADD AL,BL
1
AL  E2
BL  2E
-----------------------
CY1, AL 10
------------------------
ADD CL,AL
CL  F1
AL  10
-----------------------
CY1 , CL01
------------------------

Addition example
Note:
0000H – FFFFH for unsigned value
0000H – 7FFFH for positive value
8000H – FFFFH for negative value

SUB destination, source
SBB destination, source
• SUB instruction subtracts the contents of source operand from contents of destination.
• SBB is also known as Subtract with Borrow.(Carry flag)
• SBB instruction subtracts the contents of source operand & carry flag from contents of
destination operand.
• The source may be immediate data, memory location or register.
• The destination may be memory location or register.
• The result is stored in the destination.
• The source and the destination in an instruction cannot both be memory locations
• The source and the destination must be of the same type (bytes or words).
• Flags affected: AF, CF, OF, SF, ZF.
Example
 SUB CX, BX ;CX – BX; Result in CX
 SBB CH, AL ;Subtract content of AL and content of CF from content of CH. Result
in CH
 SUB AX, 2323H Subtract immediate number 2323H from AX
 SBB BX, [3427H] Subtract word at displacement 3427H in DS and content of
CF

SUB- EXAMPLE
SUB AL,BL
1 (BORROW) F 11
AL  01
BL  02
-----------------------
CY1, AL FF
BORROW
------------------------

SUB/SBB -EXAMPLE
SUB AL,BL
1 F 11
AL  0 1
BL  0 2
-----------------------
CY1, AL F F
------------------------
SBB CL,AL
1 F 11
CL  0 1
AL  F F
----------------------
0 2
CY 0 1
-----------------------
CY1 , CL0 1
SUB AL,BL
1
AL  01
BL  02
-----------------------
CY1, AL FF
------------------------
SUB CL,AL
1 F 11
CL  01
AL  FF
----------------------
CY1 , CL02
----------------------

MUL source
• Unsigned Multiplication
• Source may be general purpose register or memory location.
• If source is byte, then it is multiplied with contents of AL. (Result is stored in AX)
• If source is word, then it is multiplied with contents of AX. (Result is stored in DX & AX)
• If the most significant byte of a 16-bit result or the most significant word of a 32-bit
result is 0, CF and OF will both be 0’s
• AF, PF, SF and ZF are undefined after a MUL instruction
Example:
• MUL BH Multiply AL with BH; result in AX
• MUL CX Multiply AX with CX; result high word in DX, low word in AX

1008H * 1005H
--------------------
5028
0000
0000
1008
-----------------------
100D028
-----------------------
01 00 D0 28
DH DL AH AL
DX AX

IMUL source
• Signed Multiplication
• Source operand may be general purpose register or memory location.
• If source is byte, then it is multiplied with contents of AL. (Result is stored in AX)
• If source is word, then it is multiplied with contents of AX. (Result is stored in DX & AX)
• If the magnitude of the product does not require all the bits of the destination, the
unused byte / word will be filled with copies of the sign bit.
• If the upper byte of a 16-bit result or the upper word of a 32-bit result contains only
copies of the sign bit (all 0’s or all 1’s), then CF and the OF will both be 0; If it contains a
part of the product, CF and OF will both be 1
• AF, PF, SF and ZF are undefined after a IMUL instruction
Example
• IMUL BH ;Multiply signed byte in AL with signed byte in BH; result in AX

• DIV Source(divisor)
• This instruction is used to divide an unsigned word by a byte or to divide an unsigned
double word (32 bits) by a word.
• When a word is divided by a byte, the word must be in the AX register.
• The divisor can be in a register or a memory location.
• After the division, AL will contain the 8-bit quotient, and AH will contain the 8-bit
remainder.
• When a double word is divided by a word, the most significant word of the double word
must be in DX, and the least significant word of the double word must be in AX.
• After the division, AX will contain the 16-bit quotient and DX will contain the 16-bit
remainder.
• If an attempt is made to divide by 0 or if the quotient is too large to fit in the destination
(greater than FFH / FFFFH), the 8086 will generate a type 0 interrupt.
• All flags are undefined after a DIV instruction.
Example
• DIV BL Divide word in AX by byte in BL; Quotient in AL, remainder in AH
• DIV CX Divide word in DX and AX by word in CX; Quotient in AX, and
remainder in DX.

DIV-Example
Remainder Quotient

Quotient
Remainder
DIV-Example

• IDIV Source(divisor)
• Divide a signed word by a signed byte, or to divide a signed double word by a signed
word.
• When dividing a signed word by a signed byte, the word must be in the AX register.
• The divisor can be in an 8-bit register or a memory location.
• After the division, AL will contain the signed quotient, and AH will contain the signed
remainder.
• The sign of the remainder will be the same as the sign of the dividend. If an attempt is
made to divide by 0, the quotient is greater than 127 (7FH) or less than –127 (81H),
the 8086 will automatically generate a type 0 interrupt.
• When dividing a signed double word by a signed word, the most significant word of
the dividend (numerator) must be in the DX register, and the least significant word of
the dividend must be in the AX register.
• The divisor can be in any other 16-bit register or memory location. After the division,
AX will contain a signed 16-bit quotient, and DX will contain a signed 16-bit remainder.
• All flags are undefined after an IDIV.
Example
• IDIV BL Signed word in AX/signed byte in BL
• IDIV BP Signed double word in DX and AX/signed word in BP

• INC destination
• The INC instruction adds 1 (Increments) to a specified operand
• Operand can be a register or memory location
• The result is updated on the same operand
• AF, OF, PF, SF, and ZF are updated, but CF is not affected.
• This means that if an 8-bit destination containing FFH or a 16-bit destination
containing FFFFH is incremented, the result will be all 0’s with no carry.
Example:
• INC BL Add 1 to content of BL register; result is stored in BL
• INC CX Add 1 to content of CX register
• INC [5000h] Add 1 to the content at displacement 5000h in DS

DEC destination
• This instruction subtracts (decreases) the contents of source operand by 1.
• The operand may be memory location or register.
• The result is updated on the same operand
• AF, OF, SF, PF, and ZF are updated, but CF is not affected.
• This means that if an 8-bit destination containing 00H or a 16-bit destination
containing 0000H is decremented, the result will be FFH or FFFFH with no carry
(borrow).
Example
• DEC CL Subtract 1 from content of CL register; result is stored in CL
• DEC BP Subtract 1 from content of BP register
• DEC [5000h] Subtract 1 from the content at displacement 5000h in DS

• NEG Destination
• This instruction replaces the number in a destination with its 2’s complement.
• The destination can be a register or a memory location
• The NEG instruction updates AF, PF, ZF, and OF.
Example
NEG AL ;Replace number in AL with its 2’s complement
NEG BX ;Replace number in BX with its 2’s complement

CMP Destination, Source
• This instruction compares a byte / word in the specified source with a byte / word in the
specified destination.
• The source can be an immediate number, a register, or a memory location.
• However, the source and the destination cannot both be memory locations
• The comparison is actually done by subtracting the source byte or word from the
destination byte or word.
• The source and the destination are not changed, but the flags are set to indicate the
results of the comparison.
• AF, OF, SF, ZF, PF, and CF are updated by the CMP instruction.
• For the instruction CMP CX, BX, the values of CF, ZF, and SF will be as follows:
Example:
CMP AL, 01H Compare immediate number 01H with byte in AL
CMP BH, CL Compare byte in CL with byte in BH

• DAA(DECIMAL ADJUST AFTER BCD ADDITION )
• It is used after addition to make sure the result of adding two packed BCD numbers is
adjusted to be a legal BCD number
• It works on AL register. After addition,
• If lower nibble of AL>9 or AY flag=1, then add 06 to AL
• If higher nibble of AL>9 or CY flag=1, then add 60 to AL
• The DAA instruction updates AF, CF, SF, PF, and ZF; but OF is undefined.
• Example:
MOV AL,59H BEFORE DAA AFTER DAA
MOV BL,35H
ADD AL,BL
DAA

• DAS (DECIMAL ADJUST AFTER BCD SUBTRACTION)
• It is used after subtraction to make sure the result is correct packed BCD.
• It works on AL register. After subtraction,
• If lower nibble of AL>9 or AY flag=1, then subtract 06 from AL
• If higher nibble of AL>9 or CY flag=1, then subtract 60 from AL
• The DS instruction updates AF, CF, SF, PF, and ZF; but OF is undefined.
Example before DAS after DAS
MOV AL,49H
MOV BL,72H
SUB AL,BL
DAS

AAA (ASCII adjust after addition or unpacked BCD adjust for addition)
• After the addition, the AAA instruction is used to make sure the result is the correct unpacked BCD.
• It is also used to add the ASCII codes for two decimal digits (Numerical data coming into a computer from
a terminal is usually in ASCII code. numbers 0 to 9 are represented by the ASCII codes 30H to 39H )
• It works on AL register.
• IF lower bits of AL<=09 then
• Higher bits of AL should loaded with zeroes.
• AH also must be cleared (AH=0000 0000).
IF lower bits of AL>09 then,
Add 06 to AL
Add 01 to AH
Higher nibble of AL must be cleared
• AAA instruction updates AF and CF; but OF, PF, SF and ZF are left undefined.
Example: Let AL = 0011 0101 (39H or ASCII 9), and BL = 0011 1001 (35H or ASCII 5)
ADD AL, BL AL = 0110 1110 (6EH, which is incorrect BCD)
AAA AL = 0000 0100 (unpacked BCD 4)
CF = 1 indicates answer is 14 decimal.

BEFORE AAA
AFTER AAA

AAS (ASCII adjust after subtraction or unpacked BCD adjust for subtraction)
• After the subtraction, the AAS instruction is used to make sure the result is the correct
unpacked BCD.
• It is also used to add the ASCII codes for two decimal digits (Numerical data coming into a
computer from a terminal is usually in ASCII code. numbers 0 to 9 are represented by the
ASCII codes 30H to 39H )
• It works on AL register.
• IF lower bits of AL<=09 then
• Higher bits of AL should loaded with zeroes.
• AH also must be cleared (AH=0000 0000).
IF lower bits of AL>09 then,
Subtract 06 from AL.
Subtract 01 From AH
Higher nibble of AL must be cleared
• AAA instruction updates AF and CF; but OF, PF, SF and ZF are left undefined.
• Example:
• Let AL = 00111001 (39H or ASCII 9), and BL = 00110101 (35H or ASCII 5)
• SUB AL, BL AL = 00000100 (BCD 04), and CF = 0
• AAS AL = 00000100 (BCD 04), and CF = 0 (no borrow required)

AAM (Unpacked BCD ADJUST AFTER Multiplication )
• Before you can multiply two ASCII digits, you must first mask the upper 4 bit of
each. This leaves unpacked BCD (one BCD digit per byte) in each byte.
• AAM instruction is used to adjust the product to two unpacked BCD digits in AX.
• AAM works only after the multiplication of two unpacked BCD bytes, and it
works only the operand in AL.
• AAM updates PF, SF and ZF but AF; CF and OF are left undefined.
Example
• Let AL = 00000101 (unpacked BCD 5), and BH = 00001001 (unpacked BCD 9)
MUL BH ;AL x BH: AX = 00000000 00101101 = 002DH
AAM ;AX = 00000100 00000101 = 0405H (unpacked BCD for 45)

AAD (UNPACKED BCD ADJUST BEFORE DIVISION)
• AAD converts two unpacked BCD digits in AH and AL to the equivalent binary
number in AL.
• This adjustment must be made before dividing the two unpacked BCD digits in
AX by an unpacked BCD byte.
• After the BCD division, AL will contain the unpacked BCD quotient and AH will
contain the unpacked BCD remainder.
• AAD updates PF, SF and ZF; AF, CF and OF are left undefined.
Example
• Let AX = 0607 (unpacked BCD for 67 decimal), and CH = 09H
AAD AX = 0043 (43H = 67 decimal)
DIV CH AL = 07; AH = 04; Flags undefined after DIV

Arithmetic instructions
CBW (CONVERT SIGNED BYTE TO SIGNED WORD)
• This instruction copies the sign bit of the byte in AL to all the bits in AH. AH is then said to
be the sign extension of AL.
• CBW does not affect any flag.
Example
• Let AX = 00000000 10011011 (–155 decimal)
CBW Convert signed byte in AL to signed word in AX
AX = 11111111 10011011 (–155 decimal)
CWD (CONVERT SIGNED WORD TO SIGNED DOUBLE WORD)
• This instruction copies the sign bit of a word in AX to all the bits of the DX register. In other
words, it extends the sign of AX into all of DX.
• CWD affects no flags.
Example
• Let DX = 00000000 00000000, and AX = 11110000 11000111 (–3897 decimal)
CWD Convert signed word in AX to signed double word in DX:AX
DX = 11111111 11111111
AX = 11110000 11000111 (–3897 decimal)

Logical Instructions
• Instruction of this group perform logical AND, OR,
XOR, NOT and TEST operations.

AND Performs bit by bit logical AND operation of two operands and places the
result in the specified destination.
OR Performs bit by bit logical OR operation of two operands and places the
XOR Performs bit by bit logical XOR operation of two operands and places the
NOT Takes one's complement of the content of a specified register or memory
location(s).
TEST Perform logical AND operation of a specified operand with another specified
operand.

• AND destination, source
• It perform logical AND on each bit in a source byte or word with the same numbered bit in
a destination byte or word. The result is stored in the specified destination
• The source can be an immediate number, register, or memory location.
• The source and the destination cannot both be memory locations.
• CF and OF are both 0 after AND. PF, SF, and ZF are updated by the AND instruction. AF is
undefined.
Example
• AND CX, [SI] ;AND word in DS at offset [SI] with word in CX register; Result in CX
• AND BH, CL ;AND byte in CL with byte in BH; Result in BH
• AND BX, 00FFH ;00FFH Masks upper byte, leaves lower byte unchanged.

• OR destination, source
• It performs logical OR on each bit in a source byte or word with the same numbered bit in
a destination byte or word. The result is stored in the specified destination
• CF and OF are both 0 after AND. PF, SF, and ZF are updated by the OR instruction. AF is
undefined.
Example
• OR AH, CL ;CL ORed with AH, result in AH, CL not changed
• OR BP, SI ;SI ORed with BP, result in BP, SI not changed

• XOR destination, source
• It performs logical XOR on each bit in a source byte or word with the same numbered bit
in a destination byte or word. The result is stored in the specified destination
• CF and OF are both 0 after AND. PF, SF, and ZF are updated by the OR instruction. AF is
undefined.
Example
• XOR CL, BH Byte in BH exclusive-ORed with byte in CL. Result in CL. BH not changed.
• XOR BP, DI Word in DI exclusive-ORed with word in BP. Result in BP. DI not changed.

• NOT destination
• The NOT instruction inverts each bit (forms the 1’s complement) of a byte or
word in the specified destination.
Example
NOT BX ;Complement content or BX register

TEST destination, source
• This instruction ANDs the byte / word in the specified source with the byte / word in the
specified destination.
• Flags are updated, but neither operand is changed.
• The test instruction is often used to set flags before a Conditional jump instruction.
• The source can be an immediate number, register, memory location.
• CF and OF are both 0’s after TEST. PF, SF and ZF will be updated to show the results of
the destination. AF is be undefined.
Example
• TEST AL, BH ;AND BH with AL. No result stored; Update PF, SF, ZF.
• TEST CX, 0001H ;AND CX with immediate number 0001H;

• It is also called program execution transfer instruction.
• Instructions of this group transfer program execution from the normal
sequence of instructions to the specified destination or target.
• Unconditional branch
• Conditional branch
Branch Instructions

Unconditional Branch
84
Transfer the control to a specific destination or target instruction
Do not affect flags
Mnemonics Explanation
JMP label/reg/ mem/ disp16 <target address> Unconditional jump
CALL proce_name/reg/ mem/ disp16 <target address> Call subroutine
RET Return from subroutine
Branch Instructions
• JMP: fetches the next instruction from the location
specified in the instruction.
• If the destination is in the same code segment as the
JMP instruction, then only the instruction pointer
will be changed to get the destination location. This
is referred to as a near jump.
• If the destination for the jump instruction is in a
segment with a name different from that of the
segment containing the JMP instruction, then both
the instruction pointer and the code segment
register content will be changed to get the
destination location. This referred to as a far jump.
• The JMP instruction does not affect any flag.
Example:
JMP CONTINUE
This instruction fetches the next instruction
from address at label CONTINUE

callA near call is a call to a procedure, which is in the same code segment as the CALL instruction.
• When the 8086 executes a near CALL instruction, it decrements the stack pointer by 2 and copies
the offset of the next instruction after the CALL into the stack.
• This offset saved in the stack is referred to as the return address,
• A near CALL instruction will also load the instruction pointer with the offset of the first instruction
in the procedure.
• A RET instruction at the end of the procedure will return execution to the offset saved on the stack
which is copied back to IP.
A far call is a call to a procedure, which is in a different segment from the one that contains the CALL
instruction.
• When the 8086 executes a far call, it decrements the stack pointer by 2 and copies the content of the
CS register to the stack. It then decrements the stack pointer by 2 again and copies the offset of the
instruction after the CALL instruction to the stack.
• Finally, it loads CS with the segment base of the segment that contains the procedure, and loads IP
with the offset of the first instruction of the procedure in that segment.
• A RET instruction at the end of the procedure will return execution to the next instruction after the
CALL by restoring the saved values of CS and IP from the stack.
Example
CALL MULT
This is a direct within segment (near or intra segment) call.
MULT is the name of the procedure

Procedure
• Procedure is a part of code/subroutine that can be called from main program in order
to make some specific task.
• Procedures make program more structural and easier to understand.
syntax for procedure declaration:
name PROC
…………. ; BODY OF PROC
…………. ;
RET
name ENDP
Syntax for calling a procedure
• CALL procedure_name

Conditional Branch
87
Name Alternate name
JE
Jump if equal
JZ
Jump if result is 0
JNE
Jump if not equal
JNZ
Jump if not zero
JG
Jump if greater
JNLE
Jump if not less or
equal
JGE
Jump if greater than or
equal
JNL
Jump if not less
JL
Jump if less than
JNGE
Jump if not greater
than or equal
JLE
Jump if less than or
equal
JNG
Jump if not greater
 8086 signed conditional branch instructions
 Comparison - Greater and Lesser
 Mnemonic <target address>
 8086 unsigned conditional branch instructions
 Comparison - Above and below
Name Alternate name
JE
Jump if equal
JZ
Jump if result is 0
JNE
Jump if not equal
JNZ
Jump if not zero
JA
Jump if above
JNBE
Jump if not below or
equal
JAE
Jump if above or
equal
JNB
Jump if not below
JB
Jump if below
JNAE
Jump if not above or
equal
JBE
Jump if below or
equal
JNA
Jump if not above
Branch Instructions

88
JC Jump if CF = 1
JNC Jump if CF = 0
JP Jump if PF = 1
JNP Jump if PF = 0
JO Jump if OF = 1
JNO Jump if OF = 0
JS Jump if SF = 1
JNS Jump if SF = 0
JZ Jump if result is zero, i.e, Z = 1
JNZ Jump if result is not zero, i.e, Z = 1
 8086 conditional branch instructions affecting individual flags
Branch Instructions

Example Program –
Sum of N numbers

Example Program –
Sum of N numbers – USING ARRAY VAR

Loop Instructions
LOOP Jump to defined label until CX = 0.
LOOPZ/LOOPE Decrement CX register and jump if CX ≠ 0 and ZF = 1.
LOOPNZ/LOOPNE Decrement CX register and jump if CX ≠ 0 and ZF = 0.

LOOP LABEL
• This instruction is used to repeat a series of instructions some number of times.
• The number of times the instruction sequence is to be repeated is loaded into CX.
• Each time the LOOP instruction executes, CX is automatically decremented by 1.
• If CX is not 0, execution will jump to a destination specified by a label in the instruction.
• If CX = 0 after the auto decrement, execution will simply go on to the next instruction
after LOOP.
EXAMPLE:
FIND SUM OF N NUMBERS
Loop Instructions

Interrupts
• An interrupt is a condition that causes the microprocessor to
temporarily work on a different task, and then later return to its
previous task. Interrupts can be internal or external.
Interrupt is the method of
creating a temporary halt during
program execution and allows
peripheral devices to access
the microprocessor.
The microprocessor responds
to that interrupt with
an ISR (Interrupt Service
Routine), which is a short
program to instruct the
microprocessor on how to
handle the interrupt.

HardwareInterrupts
• Hardware interrupt is caused by any peripheral device by sending a signal
through a specified pin to the microprocessor.
• NMI - non-maskable interrupt
• INTR is a maskable interrupt
NMI
• It is a single non-maskable interrupt pin (NMI) having higher priority
than the maskable interrupt request pin (INTR) and it is of type 2
interrupt.
• When this interrupt is activated, the following actions takes place
• Completes the current instruction that is in progress.
• Pushes the Flag register values on to the stack.
• Pushes the CS (code segment) value and IP (instruction pointer) value of
the return address on to the stack.
• IP is loaded from the contents of the word location 00008H.
• CS is loaded from the contents of the next word location 0000AH.
• Interrupt flag and trap flag are reset to 0.

HardwareInterruptsINTR
• The INTR is a maskable interrupt because the microprocessor will be interrupted
only if interrupts are enabled using set interrupt flag instruction. It should not be
enabled using clear interrupt Flag instruction.
• The INTR interrupt is activated by an I/O port
These actions are taken by the microprocessor−
• First completes the current instruction.
• Activates INTA output and receives the interrupt type, say N.
• Flag register value, CS value of the return address and IP value of the return
address are pushed on to the stack.
• IP value is loaded from the contents of word location N × 4
• CS is loaded from the contents of the next word location.
• Interrupt flag and trap flag is reset to 0

SoftwareInterrupts
• The software interrupts are program instructions.
• These instructions are inserted at desired locations in a program.
• While running a program, if software interrupt instruction is encountered
then the processor initiates an interrupt.
• The 8086 processor has 256 types of software interrupts.
• The software interrupt instruction is INT n, where n is the type number
in the range 0 to 255.

SoftwareInterrupts
INT- Interrupt instruction with type number
• It is 2-byte instruction. First byte provides the op-code and the
second byte provides the interrupt type number.
• Its execution includes the following steps−
• Flag register value is pushed on to the stack.
• CS value of the return address and IP value of the return
address are pushed on to the stack.
• IPis loaded from the contents of the word location ‘type number’ × 4
• CS is loaded from the contents of the next word location.
• Interrupt Flag and Trap Flag are reset to 0
• The starting address for type0 interrupt is 000000H, for type1
interrupt is
00004H similarly for type2 is 00008H and ……soon

• TYPE 0 TO TYPE 4 INTERRUPTS
• These are used for fixed operations and hence are
called
dedicated interrupts
• TYPE 5 TO TYPE 31 INTERRUPTS
• Not used by 8086,reserved for higher
processors like 80286, 80386 etc
• TYPE 32 TO 255 INTERRUPTS
• Available for user, called user defined interrupts
these can be h/w interrupts and activated through
intr line or can be s/w interrupts.

• Type – 0 Divide Error Interrupt
• Quotient is large cant be fit in al/ax or divide by zero
• Type –1 Single Step Interrupt
• Used for executing the program in single step mode by setting
trap flag
• Type – 2 Non Maskable Interrupt
• This interrupt is used for execution of NMI pin.
• Type – 3 Break Point Interrupt
• Used for providing break points in the program
• Type – 4 Over Flow Interrupt
• used to handle any overflow error.

Other Instructions – Beyond Syllabus

Rotate Instructions
RCL Rotate all bits of the operand left by specified number of
bits through carry flag.
RCR Rotate all bits of the operand right by specified number of
bits through carry flag.
ROL Rotate all bits of the operand left by specified number of
bits.
ROR Rotate all bits of the operand right by specified number of
bits.

Shift Instructions
SAL or SHL Shifts each bit of operand left by specified number of bits
and put zero in LSB position.
SAR Shift each bit of any operand right by specified number
of bits. Copy old MSB into new MSB.
SHR Shift each bit of operand right by specified number of
bits and put zero in MSB position.

String Manipulation Instructions
Instruction Set
109
 String : Sequence of bytes or words
 8086 instruction set includes instruction for string movement, comparison,
scan, load and store.
 REP instruction prefix : used to repeat execution of string instructions
 String instructions end with S or SB or SW.
S represents string, SB string byte and SW string word.
 Offset or effective address of the source operand is stored in SI register and
that of the destination operand is stored in DI register.
 Depending on the status of DF, SI and DI registers are automatically
updated.
 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.
 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

110
MOVS/MOVSB/MOVSW Moves 8-bit or 16-bit data from the memory location(s) addressed
by SI register to the memory location addressed by DI register.
CMPS/CMPSB/CMPSW Compares the content of memory location addressed by DI register
with the content of memory location addressed by SI register.
SCAS/SCASB/SCASW Compares the content of accumulator with the content of memory
location addressed by DI register in the extra segment ES.
LODS/LODSB/LODSW Loads 8-bit or 16-bit data from memory location addressed by SI
register into AL or AX register.
STOS/STOSB/STOSW Stores 8-bit or 16-bit data from AL or AX register in the memory
location addressed by DI register.
REP Repeats the given instruction until CX ≠ 0
REPE/ REPZ Repeats the given instruction till CX ≠ 0 and ZF = 1
REPNE/REPNZ Repeats the given instruction till CX ≠ 0 and ZF = 0

String Manipulation Instructions
Instruction Set
111
8086 Microprocessor
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
REP
REPZ/ REPE
(Repeat CMPS or SCAS until
ZF = 0)
REPNZ/ REPNE
(Repeat CMPS or SCAS until
ZF = 1)
While CX  0 and ZF = 1, repeat execution of
string instruction and
(CX)  (CX) – 1
While CX  0 and ZF = 0, repeat execution of
string instruction and
(CX)  (CX) - 1

4. String Manipulation Instructions
Instruction Set
112
8086 Microprocessor
MOVS
MOVSB
MOVSW
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)
(MAE)  (MA)
If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)
(MAE ; MAE + 1)  (MA; MA + 1)
Moves 8-bit or 16-bit data from the memory location(s) addressed by SI register to the
memory location addressed by DI register.

Instruction Set
113
8086 Microprocessor
CMPS
CMPSB
CMPSW
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)
Modify flags  (MA) - (MAE)
If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0
If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0
For byte operation
For word operation
Compare two string byte or string word

Instruction Set
114
8086 Microprocessor
SCAS
SCASB
SCASW
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)
If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0
If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI)  (DI) + 1
If DF = 1, then (DI)  (DI) – 1
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)
If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0
If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI)  (DI) + 2
If DF = 1, then (DI)  (DI) – 2
Scan (compare) a string byte or word with accumulator

Instruction Set
115
8086 Microprocessor
LODS
LODSB
LODSW
MA = (DS) x 1610 + (SI)
(AL)  (MA)
If DF = 0, then (SI)  (SI) + 1
If DF = 1, then (SI)  (SI) – 1
MA = (DS) x 1610 + (SI)
(AX)  (MA ; MA + 1)
If DF = 0, then (SI)  (SI) + 2
If DF = 1, then (SI)  (SI) – 2
Load string byte in to AL or string word in to AX

Instruction Set
116
8086 Microprocessor
STOS
STOSB
STOSW
MAE = (ES) x 1610 + (DI)
(MAE)  (AL)
If DF = 0, then (DI)  (DI) + 1
If DF = 1, then (DI)  (DI) – 1
MAE = (ES) x 1610 + (DI)
(MAE ; MAE + 1 )  (AX)
If DF = 0, then (DI)  (DI) + 2
If DF = 1, then (DI)  (DI) – 2
Store byte from AL or word from AX in to string

STC Set CF  1
CLC Clear CF  0
CMC Complement carry CF  CF/
STD Set direction flag DF  1
CLD Clear direction flag DF  0
STI Set interrupt enable flag IF  1
CLI Clear interrupt enable flag IF  0
NOP No operation
HLT Halt after interrupt is set
WAIT Wait for TEST pin active
ESC opcode mem/ reg Used to pass instruction to a coprocessor
which shares the address and data bus
with the 8086
LOCK Lock bus during next instruction
5. Flag Manipulation and Processor Control Instructions
Instruction Set
117
8086 Microprocessor

Assembler directives - Beyond Syllabus

Assemble Directives
119
8086 Microrocessor
Instructions to the Assembler regarding the program being
executed.
Control the generation of machine codes and organization of
the program; but no machine codes are generated for
assembler directives.
Also called ‘pseudo instructions’
Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..

Assemble Directives
120
8086 Microprocessor
Define Byte
Define a byte type (8-bit) variable
Reserves specific amount of memory
locations to each variable
Range : 00H – FFH for unsigned value;
00H – 7FH for positive value and
80H – FFH for negative value
General form : variable DB value/ values
Example:
LIST DB 7FH, 42H, 35H
Three consecutive memory locations are reserved for
the variable LIST and each data specified in the
instruction are stored as initial value in the reserved
memory location
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
FAR
NEAR
ENDP
SHORT
MACRO
ENDM

Assemble Directives
121
8086 Microprocessor
Define Word
Define a word type (16-bit) variable
Reserves two consecutive memory locations
to each variable
Range : 0000H – FFFFH for unsigned value;
0000H – 7FFFH for positive value and
8000H – FFFFH for negative value
General form : variable DW value/ values
Example:
ALIST DW 6512H, 0F251H, 0CDE2H
Six consecutive memory locations are reserved for
the variable ALIST and each 16-bit data specified in
the instruction is stored in two consecutive memory
location.
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
FAR
NEAR
ENDP
SHORT
MACRO
ENDM

Assemble Directives
122
8086 Microprocessor
SEGMENT : Used to indicate the beginning of
a code/ data/ stack segment
ENDS : Used to indicate the end of a code/
data/ stack segment
General form:
Segnam SEGMENT
…
…
…
…
…
…
Segnam ENDS
Program code
or
Data Defining Statements
User defined name of
the segment
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
FAR
NEAR
ENDP
SHORT
MACRO
ENDM

Assemble Directives
123
8086 Microprocessor
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
FAR
NEAR
ENDP
SHORT
MACRO
ENDM
Informs the assembler the name of the
program/ data segment that should be used
for a specific segment.
General form:
Segment Register
ASSUME segreg : segnam, .. , segreg : segnam
the segment
ASSUME CS: ACODE, DS:ADATA Tells the compiler that the
instructions of the program are
stored in the segment ACODE and
data are stored in the segment
ADATA
Example:

Assemble Directives
124
8086 Microprocessor
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
FAR
NEAR
ENDP
SHORT
MACRO
ENDM
ORG (Origin) is used to assign the starting address
(Effective address) for a program/ data segment
END is used to terminate a program; statements
after END will be ignored
EVEN : Informs the assembler to store program/
data segment starting from an even address
EQU (Equate) is used to attach a value to a variable
ORG 1000H Informs the assembler that the statements
following ORG 1000H should be stored in
memory starting with effective address
1000H
LOOP EQU 10FEH Value of variable LOOP is 10FEH
_SDATA SEGMENT
ORG 1200H
A DB 4CH
EVEN
B DW 1052H
_SDATA ENDS
In this data segment, effective address of
memory location assigned to A will be 1200H
and that of B will be 1202H and 1203H.
Examples:

Assemble Directives
125
8086 Microprocessor
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM
PROC Indicates the beginning of a procedure
ENDP End of procedure
FAR Intersegment call
NEAR Intrasegment call
General form
procname PROC[NEAR/ FAR]
…
…
…
RET
procname ENDP
Program statements of the
procedure
Last statement of the
procedure
the procedure

Assemble Directives
126
8086 Microprocessor
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM
ADD64 PROC NEAR
…
…
…
RET
ADD64 ENDP
The subroutine/ procedure named ADD64 is
declared as NEAR and so the assembler will
code the CALL and RET instructions involved
in this procedure as near call and return
CONVERT PROC FAR
…
…
…
RET
CONVERT ENDP
The subroutine/ procedure named CONVERT
is declared as FAR and so the assembler will
code the CALL and RET instructions involved
in this procedure as far call and return
Examples:

Assemble Directives
127
8086 Microprocessor
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM
Reserves one memory location for 8-bit
signed displacement in jump instructions
JMP SHORT
AHEAD
The directive will reserve one
memory location for 8-bit
displacement named AHEAD
Example:

Assemble Directives
128
8086 Microprocessor
DB
DW
SEGMENT
ENDS
ASSUME
ORG
END
EVEN
EQU
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM
MACRO Indicate the beginning of a macro
ENDM End of a macro
General form:
macroname MACRO[Arg1, Arg2 ...]
…
…
…
macroname ENDM
Program
statements in
the macro
the macro

8086 instruction set (with simulator)

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