Tarun Purohit is seeking a role as an IC layout engineer with experience designing analog and mixed signal layouts. He has over 5 years of experience working at Cadence Design Systems as a Layout Design Engineer and Analog Layout Consultant. He has extensive knowledge of designing layouts using CMOS standard processes and Cadence Virtuoso tool. He is proficient in deep sub-micron process technologies and has experience designing critical blocks such as transmitters, BG's, driver circuits, LDO, and sampler circuits.

1. Curriculum Vitae
Tarun Purohit
Kanchan Tea Company tarunkpurohit@gmail.com
Neharu Market tarunkpurohit@outlook.com
Jhunjhunu Mobile No. +91-8147763978
Rajasthan India 333001 +91-8088996078
Career Objective:
A candidate with a bachelor's degree in electronics engineering and sound
knowledge about working for Analog IC design layouts, seeks a challenging role as
an IC layout engineer which allow me to grow with the company both personally and
professionally and effectively contribute towards the goals of the organization.
Summary of Skills:
 Comprehensive knowledge of designing analog and mixed signal layout, IO
circuits, and verification tools
 Extensive knowledge of designing various layouts by using CMOS standard
processes
 Sound knowledge of matching resistors, debugging DRC, and managing
layout design
 Familiar with Cadence Virtuoso tool
 Has the ability to work independently
 basic knowledge of Skill language
Work Experience:
Organization: Cadence Design Systems, Inc.
12th January – 2015 till date
Designation: Layout Design Engineer
 Handle the tasks of designing custom layout of transistor by following the
standard procedures of IC layout
 Perform responsibilities of developing design specifications of electrical
constraints and electro-migration layout
 Hands on experience in deep sub-micron Process technologies (16nm, 28nm)
in TSMC, UMC, SAMSUNG and FDSOI.
 Layout Design for various critical blocks like (Transmitter, BG’s and Driver
Circuits)

2.  Responsible for coordinating with design engineers to ensure that the
designed layout of electrical chips meets the standard guidelines
 Handle responsibilities of updating IC design to the senior engineer for
verification
 Responsible for developing custom IC layout by utilizing Cadence layout tools
Organization: Cadence Design Systems, Inc.
30 April 2014 – 11 Jan 2015
Designation: Analog layout Consultant
 Hands on experience in deep sub-micron Process technologies (16nm, 28nm)
in TSMC, UMC, SAMSUNG and FDSOI.
 Layout Design for various critical blocks like (LDO and Sampler Circuits)
 Assigned the tasks of assisting senior IC layout engineer in generating quality
layouts following by following the standard methods
 Performed the tasks of developing IC layout from scratch as well as verified
IC by using CAD tools
 Performed the task of developing custom layouts under the guidelines of
senior IC layout engineer
Organization: Cadence Design Systems, Inc.
30 Sept 2013 – 29 April 2014
Designation: Analog Layout Design Trainee
 Undergone Seven months of Analog and Mixed signal Layout Design training.
 Learned about Physical verification flow (DRC, LVS and QRC) in PVS.
 Worked on Simulations for small circuits and verified the results.
Educational Qualifications:
 Bachelor of Technology in Electronics and Communication Engineering
Rajasthan Technical University in the year 2013
Declaration:
I hereby certify that all the information provided above is true to the best of my
knowledge.
Date:

3. Place: Bangalore Tarun Purohit