The document describes an Engineering Incubation Centre (EIC) program for recent college graduates. The 16-week program helps graduates transition to become productive VLSI design and verification professionals. It covers topics like digital design, HDLs, verification, and SystemVerilog through phases of induction, building basics, RTL design, verification methodology, and domain-specific case studies. The goal is to assess skills, provide tailored training, and guide graduates to dream jobs in the field.

1. CVC Confidential, www.cvcblr.com

2. Anubhūti - a powerful word found in many Indian languages Means profound experience leading to self-realization In our context – it is beyond simple trainings, a complete Experiential Learning CVC Confidential, www.cvcblr.com VLSI Design & Verification Incubation Transforming Graduates to VLSI Professionals

3. CVC Confidential, www.cvcblr.com

4. CVC Confidential, www.cvcblr.com RCG – Recent College Graduate

6. What is EIC? Engineering Incubation Centre Formalization of our time-tested internal process Bringing up fresh graduates to be productive in VLSI Design & Verification PRAGMATIC PROCESS - ALARM Assess - Skill level Learn - Bridge the gaps Adopt - Deploy what you learnt Review - Measure the skill set Master - Build the confidence CVC Confidential, www.cvcblr.com

7. Unique Features Tailor made to suit individual strengths & weakness; Not a “one size fit all” offering Create production quality IPs Graduate can choose a dream job, we will guide you on what’s needed to get there. Most up-to date content—including what the Design teams require few years down the line Covers SystemVerilog 2009 features Opportunity to share your ideas/experience through our newsletter CVC Confidential, www.cvcblr.com

8. Our Team Several ASICs designed & verified Industry icons; Experienced from spec-to-chips-to-boards Active contributor to newer technologies Experienced , World Class trainers Timelines 16 weeks (480 hours) 8 weeks of INDUCTION 8 weeks of PERFECTION Buffer: 2 weeks As the strengths of individuals differ! CVC Confidential, www.cvcblr.com

9. Phase1 : Introduction Recap of Digital System Design VLSI Introduction VLSI flow Phase2 : Building the basics UNIX Simulation Verification Synthesis Phase3: HDLs Verilog HDL Simulation wheel VHDL CVC Confidential, www.cvcblr.com

10. Phase4: Art of RTL Design Spec —> Micro arch Arch —> HDL code DIY—1 Phase5 : Art of Verification Comprehensive Functional Verification Toolsmith DIY—2 Debug, Regressions Phase6 : DV Projects DVClosure DVAuthoring SysImplement CVC Confidential, www.cvcblr.com

11. Phase7 : HDL Synthesis Process Optimization: area/timing HDL Coding Guidelines for Synthesis Understanding HDL to HW Mapping Phase8: SystemVerilog Introduction SV-Design CVC Confidential, www.cvcblr.com

12. Phase9: Assertion Based Verification: ABV introduction SystemVerilog Assertions Formal Verification Phase12 : FPGA Prototyping Phase16: Domain specific case study Networking—Ethernet Switch/Router Processor design Image processing CVC Confidential, www.cvcblr.com

13. Phase8: SystemVerilog Introduction SV-Design Phase9: Assertion Based Verification: ABV introduction SystemVerilog Assertions Formal Verification Phase10: Verification with SystemVerilog Class, OOP Coverage, constraints CVC Confidential, www.cvcblr.com

14. Phase11: Verification Methodology Open Verification Methodology (OVM) Verification Methodology Manual (VMM) Elective: Phase13 : Property Specification Language Phase14 : SystemC Phase15: Essential e — IEEE 1647 Phase16: Domain specific case study Networking—Ethernet Switch/Router Processor design Image processing CVC Confidential, www.cvcblr.com