The document discusses using a UART (Universal Asynchronous Receiver/Transmitter) as a state machine. The UART top module contains receiver and transmitter modules. The baud rate is 1200 Hz, so the transmitter clock is 1200 Hz while the receiver clock is 16 times faster at 19200 Hz to allow for 8 samples per received bit to reduce errors. The UART implements the transmitter and receiver functions as state machines.

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Finite State MachinesFinite State Machines
ASIC DESIGN USING
FPGA
BEIT VII
KICSIT
May 10 2012 Lecture 31

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UART as State Machine
• UART top module consists of two modules, instanciated as
uar_top (Receiver module)and uat_top ( Transmitter
module).
• The Baud rate of the UART is 1200.
• Hence the transmitter clock is generated as 1200 Hz.
• And the Receiver clock is generated as 19200 Hz (1200 x
16), 16 times faster than Transmitter clock.
• This is due to the fact that the Receiver module uses
sampling of the received bit stream of data from pc.
• 8 samples of each bit are compared in order to ensure the
bit and hence reduce the error.

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UART as State Machine
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State Machine Hardware
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