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Dt25720726
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Dt25720726

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IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com

IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com

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  • 1. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726 Fault Detection By Using Random And Deterministic Test Pattern Techniques In A Mixed-Mode BIST Environment C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, & P.Venkata Gopikumar PG Scholar Department of Electronics & Communication Engineering Jawaharlal Nehru Technological University Anantapur, IndiaAbstract A method for testing embedded core pseudorandom pattern generation (PRPG) are calledbased system chips is to use a built-in-self-test random-pattern-resistant (RPR) faults. To increase(BIST). A mixed-mode (Partial pattern matching the probability of detecting the RPR faults byand multi-control-sequence) built-in-self-test following the three categories. But these three(BIST) that brings two new techniques. They are categories have drawbackspartial pattern matching and multi control  The modification of circuit under testsequence. Partial pattern matching allows the  The use of weighted random patternreduction of the number of patterns used for generation.detecting random-pattern-resistant faults without  The mixed mode approach.using the fault simulation. A multi controlsequence is used to guide the linear feedback shift The first category improves fault coverageregister (LFSR) to generate these patterns at by redesigning or inserting test points. It is notapplication time. The main advantages of this always possible because of performance restrictionmethod are reduction of the test data volume, or intellectual property (IP) reasons. The secondrequire less time to test the application and its category is also to increase the probability for testreusability for logic cores on a system-on-chip patterns to detect RPR faults, but it is not efficient(SOC). the third category consists of two phases: In the first phase, PR patterns are applied to detect the faultsIndex Terms—-Built in self-test (BIST), Linear here fault coverage is done by 60% to 80% only. Infeedback shift register (LFSR), random-pattern- the second phase, deterministic test patterns areresistant (RPR) faults, system-on-chips (SOCs). injected to find the remaining faults. The deterministic patterns are generated by the LFSR[1]1. Introduction by reseeding are Appling a control signal that Design integration can be increased by matches the output of the LFSR to the desiredmaking the ICs small size and power should be low. deterministic patterns.The requirements for small size and low-power ICs A new technique for the generation of thehave caused a significant increase in design test patterns for RPR faults by controlling the LFSRintegration. the integration several designs (cores) at the time of test application. This technique isinto a single monolithic IC which results in a system- called partial pattern matching. Select a BIST[2]on-chip (SOC). The number of cores integrated in a using a controllable LFSR with multiple scan chainsSOC is rapidly increasing, resulting in large amount to generate deterministic patterns. In this approach,of test data. To achieve the good test quality for the the system integrator is able to develop the core’scomplex SOC by using the finite number of I/Os is a tests without knowing the actual implementation ofvery difficult task. The amount of time required for the core because providing deterministic test patternsthis type of test application is high, it is also a big and the S-matrix by the core provider. Hence, theproblem to overcome all these drawbacks and for method promotes design and test reuse withouttesting embedded core based system chips is to use a changing or revealing IP information.built-in self-test (BIST). The advantages of built-in Partial-matching technique along withcell-test (BIST) are simplicity, flexibility and low multiple scan chains the BIST greater using aoverhead. The test pattern generator for the BIST is controllable LFSR, the goals such arepseudorandom (PR) test pattern generator for its on-  To reduce the test data volumechip test pattern generation.  To shorten the test application time Pseudorandom test pattern generation  Reusability for logic cores(PRPG) can be implemented by using a linear These three major goals can be achieved byfeedback shift register. LFSR has several advantages. mixed mode BIST. When comparing this methodThey are low overhead, scalability and reuse mixed-mode BIST environment to other mixed-modecapability. Faults that are difficult to detect by approaches. In 720 | P a g e
  • 2. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726Most mixed modes, the test flow is outlined in Fig.1(a). Our methodology is shown in Fig. 1(b):First, a deterministic ATPG is used. The patterns arethen partially matched. The remaining patterns are Cgenerated by applying a control sequence to theLFSR[1]. In our architecture shown in Fig. 2: It Uconsists of controllable LFSR and phase shifter and Tscan chains and it is connected to the multi inputsignature register(MISR) from this it is connected to Toembedded memory from this it is connected to LFSRBIST[2] controller. Design Design Fault Simulation with ATPG T1 PRPG Deterministic RPR Faults patterns PRPG ATPG Partial Matching Phase shifter Deterministic Controllable patterns Remaining PRPG patterns Tm-1 MISR Second Phase of Mixed- Control sequences Mode (a) (b) Improved test Improved test Quality Quality (a) (b)Fig. 1. Mixed-mode flow Combinational In many of the mixed modes, first the test logicflow is done by using a PR pattern, fault simulationis performed, and the RPR faults are identified. Then,a deterministic automatic test pattern generation(ATPG) is used to generate patterns for RPR faults. Embedded BIST Memory Controller Fig. 2. Proposed testing architecture. The second phase of the mixed-mode approach is then applied that is deterministic patterns are applied to target remaining faults. In our methodology first, a deterministic ATPG is used. The patterns are then partially matched. The remaining patterns are generated by applying control sequence to the LFSR. In our proposed method there are many advantages. First, fault simulation is eliminated but it is not in the case of other mixed modes. Second, the 721 | P a g e
  • 3. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726partial pattern matching increases the number of hits Fig. 3 (b) S-graph of a design.and hence leaves a fewer number of RPR patterns torequire LFSR control signals. The shorter the control asequence, the smaller the storage needed on the chip. 1 aIn section II, we describe the partial matching 1 Ascheme. In section III, we describe the multiple- 7control sequence(MCS). Simulation results are g apresented in section IV, synthesis results are o apresented in section V, and in section VI, we present 1 Cour results. 0 a2. PARTIAL MATCHING a To maximize the fault coverage, all g 2 5specified bits of the deterministic test patterns have 1to be fully matched by the PR patterns being aproduced by the LFSR. If there are many specifiedbits in the test pattern of a long scan chain, but it is 3difficult for PR pattern to hit any deterministic a g apatterns with a full pattern match. This will result in 4huge number of test patterns that are not covered, 2 a B 1this drawback can be eliminated in our new partial 0 6matching technique which analyzes the binary S-matrix. This binary S-matrix and utilizes the atopology of the logic cones. This approach increases 9the possibility of patterns matching and hencereduces the size of the required control sequence. gCircuit Modeling 3 The binary S-matrix can be constructedfrom the S-graph [6] that is G = (V, E), where V isthe set of vertices representing the scan cells in the acircuit, E is the set of edges representing connectivity Fig. 3. (a) ISCAS benchmark circuit S27. 8between the scan cells. The first step of the testpreparation is to generate the binary S-matrix [6] for Using Logic Cones to Partitionthe cores. An entry S (i, j) =1 indicates that scan cell A single deterministic test pattern generatedi is feeding into scan cell j. And S (I, j) =0 indicates by an ATPG usually detects more than one fault inthat scan cell i is not feeding into scan the desire. When the pattern is captured by the flip-cell j. Using the S-matrix confirms our approach with flops, the new input of any flip flop represents therespect to testing without revealing IP information response of pattern for faults within thebecause the S-matrix is represented by the combinational circuit cone converging at this flipconnectivity of scan cells without giving structure of flop. Logic cones are nothing but logic gates orthe logic circuits. simply combinational circuits each sub pattern In the similar way the scan chains can also be corresponds to a logic cone of the design, which mayconstricted, in such way that the scan cells in the contain multiple faults of the logic gates. Forsame scan chain are independent of each other. The example deterministic test pattern expanded intoaim was to make the set of linear equations, which three sub patterns each sub pattern detects faults inare necessary for the reseeding of an LFSR. In other the corresponding logic cone sub patterns have morewords all the inputs of any logic cone are always in ”don’t care” bits than the original pattern. Hence,one scan chain but in our approach where the inputs they are easier to match with the PR patterns then theof a logic cone can be in any scan chain. original deterministic test pattern. Now a partial A B C pattern matching technique is to be applied to the sub patterns as an enhancement to the full pattern A 1 0 0 matching technique, which has been applied to the A 1 1 0 original deterministic test patterns. B The partial matching technique consists of the C following three steps. C 1 0 1  Form sub patterns for each deterministic B (c). Binary S-matrix of a pattern using a cone-masking approach.design  Generate the PR test patterns by simulating the LFSR and match them to sub patterns. 722 | P a g e
  • 4. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726  Combine the remaining unmatched sub pattern counter counts the number of capture cycles patterns that are related to the each original that occur during each test execution phase. deterministic test pattern and update the final set of deterministic test patterns.U0 M M0 X15 T0 S0 U1 Phase shifter z M1 X14 T1 S1 X13 Um-1 X12 Mm-1 Tm-1 Sm-1 X0 Fig. 4. Controlling the LFSR TABLE I The original deterministic test patterns are split in to sub patterns for each deterministic test Sub patterns for deterministic pattern pattern the number of sub patterns is equal to the number of columns of the S-matrix that have at least Deterministic Sub-Patterns Logic one entry of a “1” . The value of bit i of sub pattern j Pattern cone A B C is the same as the value of bit i of the deterministic A B C test pattern if and only if S [i, j] is 1 otherwise it is unspecified bit(x). 0 1 1 0 x x 1 In this method, there existing a phase x 1 x 2 shifter [4] and multiple scan chains. There are two test execution phases. During the first test phase, the x x 1 3 LFSR is freely ran for a user specified number of N cycles to generate PR test patterns for easily The circuit shown in Fig. 3(a) is the ISCAS detectable faults. The number of PR test patterns is (International standard circuit and system) the same as the used in all cores but with less test benchmark circuit S27. It can be represented by the application time because of multiple scan chains. In S-graph shown in Fig. 3(b). The corresponding the second test phase MCSs are used to direct the binary S-matrix is shown in Fig. 3(c). As per our LFSR to generate the remaining patterns to detect the methodology first Deterministic ATPG is used and it RPR faults. is found that as 011.This deterministic pattern is then Along with the phase shifter [4] and multiple scan split into three sub-patterns. Each sub pattern chains there existing also a BIST controller. A corresponds to a logic cone of the design. Number of pattern counter and a bit counter are part of the BIST logic for the circuit in Fig. 3(a), Table I shown controller. The bit counter keeps track of the number deterministic test pattern (column 1) expanded into of test data bits being shifted into scan chains. The three sub patterns. In the circuit fault was injected at 723 | P a g e
  • 5. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726the a3 this fault is not identified by the random the body field Si, and Si is equal to one the advantagepattern and it is detected by deterministic pattern at of MCS is to control any number of scan chain.the 011.once after finding the deterministic patternand again the faults are injected at the a3, a4 and 4. Simulation resultsthese faults are determined by random pattern andthose faults which are not covered by random patternare identified by deterministic pattern test generation.Thus all the faults will be determined by this method,by applying both random pattern test generation anddeterministic pattern test generation, when s=0 thecontrollable LFSR [3] generate random test patternsand when s=1 it will generate the deterministic testpatterns.3. MULTICONTROL SEQUENCES BIST controller allows the LFSR to freelyrun for a user defined number of capture cycles N itbegins to control the LFSR.The method ofdeterministic bits presented a PRPG register to feedthe LFSR seeds for generating the desired patterns ina multiple scan chain design For controlling theLFSR, using an MCS to direct it and to generate andapply the desired deterministic patterns in a multiplescan design. The MCS consists of two vectors U=(U0, U1, U2…..Um-1) and S= (S0, S1, S2……Sm-1). TheU vector was directly injected through multiplexersto scan chains. All multiplexers have been moved tothe front of LFSR to improve both the test time andtest data volume. Phase shifters structure is based on the STUMPSarchitecture, one of the scan chains [5] is directly fed Fig. 5. Random pattern test generation.from the left most tap of the LFSR while other chainsare fed from the phase shifter all the patternssupplied to each scan chains can be controlled. Forexample assume that four scan chain being controlledby four taps from the phase shifter deterministic testpatterns indicated on These scan chains are (T0, T1,T2, T3) respectively. There are more advantages inusing multi control to guide the LFSR to feed thetarget test data to the scan chains. In most of thecases only a few control sequences in some scanchains have to be specified while the remainingcontents in the scan change are automaticallymatched to deterministic patterns. Therefore the restof control sequences do not need to be specified.This further reduces the test data storagerequirement. The data format for the MCS consists of twoand fields: a header and a body. The header specifiesthe logic values for the multiplexer selectors, bodyholds the MCSs U0, U1………Um-1. If thedeterministic pattern for the ith scans chain consistsof only unspecified bits then the corresponding ithcontrol sequence Ui is not needed to create thedesires values of deterministic patterns. Therefore, Siis equal to zero, Ui can be skipped from the bodyfield. However even If there is only one specified bitto be controlled in a deterministic pattern the Fig. 6. Deterministic test pattern generation.corresponding control sequence Ui must be include in 724 | P a g e
  • 6. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726 Fig.10.S-matrix and deterministic test pattern generation.Fig. 7. S-graph and S-matrix.Fig. 8. ISCAS benchmark circuit S27. Fig. 11. ISCAS benchmark circuit S27. 5. Synthesis result 6. Conclusion In conclusion, a new approach that is mixed-mode BIST that makes use of a partial- matching technique to facilitate the generation of patterns for RPR faults. The test application mode uses a controllable LFSR for a multiple-scan-chain configuration. We have analyzed the design through the creation of a binary S-matrix and the identification of logic cones. Then, we have applied the partial pattern matching to filter the RPR faults. In addition, we have generated an MCS to guide the LFSR to generate the desired patterns instead of applying the whole deterministic test. the fault coverage as high as intended by the deterministic test, we have succeeded in reducing both the test data volume and the test application time. Moreover, in comparison with [22], both the test sequence length and the hardware overhead are much lower.Fig. 9. Random pattern test generation 7. Acknowledgment P.Venkata GopiKumar would like to thank C .Ravishankar Reddy, who had been guiding through out to complete the work successfully, and 725 | P a g e
  • 7. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726would also like to thank the HOD, ECE Departmentand other Professors for extending their help &support in giving technical ideas about the paper andmotivating to complete the work effectively &successfullyReferences [1] B. Koenemann, “LFSR-coded test patterns for scan designs,” in Proc. Eur.Test Conf., 1991, pp. 237–242. [2] E. Kalligeros, X. Kavousianos, and D. Nikolos, “Multiphase BIST:A new reseeding technique for high test-data compression,” IEEETrans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 10,pp. 1429–1446, Oct. 2004 [3] D. Kay and S. Mourad, “Controllable LFSR for built-in self-test,” in Proc.IMTC, 2000, pp. 223–229 [4] J. Rajski and J. Tyszer, “Design of phase shifters for BIST applications,”in Proc. VTS, 1998, pp. 218–224. [5] T. Reungpeerakul, D. Kay, and S. Mourad, “Interactive BIST for embeddedcore in SOC: Partial matching and control sequences technique,” inProc. IMTC, 2006, pp. 365–369. [6] B. Greene and S. Mourad, “Partial scan testing on the register-transferlevel,” in J. Electron. Test., Theory Appl., Dec. 2002, vol. 18, no. 6,pp. 613–626. 726 | P a g e

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