Data security using advanced encryption standard aes in reconfigurable hardware for sdr based wireless systems

1. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print),
ISSN 0976 - 6375(Online), Volume 6, Issue 1, January (2015), pp. 95-100 © IAEME
95
DATA SECURITY USING ADVANCED ENCRYPTION
STANDARD (AES) IN RECONFIGURABLE HARDWARE
FOR SDR BASED WIRELESS SYSTEMS
Sharanagouda N Patil1
, R.M.Vani2
, P.V.Hunagund3
1
Dept. of Applied Electronics, Gulbarga University, India
2
Dept. of USIC, Gulbarga University, India
3
Dept. of Applied Electronics, Gulbarga University, India
ABSTRACT
A software defined radio (SDR) is a radio transmitter/receiver that uses reconfigurable
hardware and software for encoding/decoding, modulation/demodulation, and encrypting/decrypting.
This allows much more power and flexibility when designing any radio system. The AES algorithm
is a block cipher that can encrypt and decrypt digital information. The AES algorithm is capable of
using cryptographic keys of 128, 192, and 256 bits. The Rijndael cipher has been selected as the
official Advanced Encryption Standard (AES) as it is well suited for reconfigurable hardware. The
Advanced Encryption Standard can be programmed in software or built with hardware. However
Field Programmable Gate Arrays (FPGAs) offer a more customized solution. This paper talks of
AES 128 bit block and 128 bit cipher key and is implemented using VHDL as the hardware
description language. Here a new FPGA-based implementation scheme of the AES-128 (Advanced
Encryption Standard, with 128-bit key) encryption algorithm is proposed for software defined radio
applications. This system aims at reduced hardware structure and high throughput. Xilinx - Project
Navigator, ISE 9.1i suite is used for simulation and synthesis.
Keywords: AES, Cipher text, FPGA, SDR, VHDL
I. INTRODUCTION
With ever increasing demand for mobile communication and emergence of many new
systems and standards like 3G and 4G and even many researches are going to develop new wireless
standards. It has become imperative to implement and design a flexible architecture of radio system
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2. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print),
ISSN 0976 - 6375(Online), Volume 6, Issue 1, January (2015), pp. 95-100 © IAEME
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which accommodates the feature of interoperability and multi functionality and operation of the
devices in heterogeneous, variable operating conditions. Different standards of Mobile
communication use different type of hardware circuitry. The existing mobile communication
standards are primarily designed along national standards and not using a common global standard.
So efforts are going on to develop systems which can support multiple mobile communication
standards using same hardware but changing the software / firmware or a combination of both. This
gave rise to Software Defined Radio which is a new technology being developed.
A SDR refers to any reconfigurable or reprogrammable radio system that can show different
functionality with the same hardware. A Software Defined Radio can simply be defined as “ Radio in
which some or all of the physical layer functions are software defined”. The encryption/decryption
functions of the system are defined using higher abstraction levels of HDLs. Today software defined
technology offers advantages such as improvements or enhancements without altering the radio
hardware, terminals that can cope with the unpredictable dynamic characteristics of highly variable
wireless links, efficient use of radio spectrum and power, and many others. The users can use
relatively generic reprogrammable hardware and customize it to their needs by choosing only the
software implementation that fits their specific application [1,2]. The difference between a digital
radio and an SDR is that a digital radio is not reconfigurable. Although a Digital radio has software
running on it; the functionality of the components cannot be changed on air. New technology
insertion is not available.
II. BACKGROUND OF SOFTWARE DEFINED RADIO
One of the first software radios was the US Air Force’s Integrated Communications
Navigation and Identification Avionics (ICNIA) system, which was developed in the late 1970’s.
The system used a DSP based modem that is reprogrammable for different platforms. ICNIA’s
technology has been the foundation for many other military radios. SDR is a radio communication
technology which is capable of being re-programmed or reconfigured. SPEAKeasy is a joint
Department of Defense and industry program initiated to develop a software programmable radio
operating in the range from 2 MHz to 2 GHz, employing waveforms selected from memory or
downloaded from disk or reprogrammed over the air [3]. The improvements in DSP and ADC
technologies facilitated the shift to software defined radios. Modern functions can be implemented in
software with today’s high DSPs and General Purpose Processors (GPPs). The low power
requirements of the processors enable them to be used in hand terminals. The increased dynamic
operating ranges and higher conversion rates of modern ADCs enables digital processing at higher
bands. The improvements in middleware technologies permit software functionality to be
independent of the underlying hardware [4].The General structure of SDR are given below Figure 1.
Figure 1: General Block Diagram of a SDR

3. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print),
ISSN 0976 - 6375(Online), Volume 6, Issue 1, January (2015), pp. 95-100 © IAEME
97
III. BACKGROUND OF AES
The AES algorithm is a symmetric block cipher that can encrypt and decrypt information.
Encryption converts data to an unintelligible form called cipher-text [5]. Decryption of the cipher-
text converts the data back into its original form, which
is called plain-text.
3.1 AES encryption
The AES algorithm operates on a 128-bit block of data and executed Nr - 1 loop times. A
loop is called a round and the number of iterations of a loop, Nr, can be 10, 12 or 14 depending on
the key length. The key length is 128, 192 or 256 bits in length respectively. The first and last rounds
differ from other rounds in that there is an additional AddRoundKey transformation at the beginning
of the first round and no MixCoulmns transformation is performed in the last round. In this paper, we
use the key length of 128 bits (AES-128) as a model for general explanation
3.1.1 SubBytes Transformation
The SubBytes transformation is a non-linear byte substitution, operating on each of the state
bytes independently. The SubBytes transformation is done using a once-pre-calculated substitution
table called S-box. That S-box table contains 256 numbers (from 0 to 255) and their corresponding
resulting values. More details of the method of calculating the S-box table refers to [4]. In this
design, we use a look-up table as shown in Table 1.
This approach avoids complexity of hardware implementation and has the significant
advantage of performing the S-box computation in a single clock cycle, thus reducing the latency.
3.1.2 ShiftRows Transformation
In ShiftRows transformation, the rows of the state are cyclically left shifted over different
offsets. Row 0 is not shifted, row 1 is shifted one byte to the left, row 2 is shifted two bytes to the left
and row 3 is shifted three bytes to the left.

4. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print),
ISSN 0976 - 6375(Online), Volume 6, Issue 1, January (2015), pp. 95-100 © IAEME
98
3.1.3 MixColumns Transformation
In MixColumns transformation, the columns of the state are considered as polynomials over
GF (28
) and multiplied by modulo x4
+ 1 with a fixed polynomialc(x), given by: c(x)={03}x3
+
{01}x2
+ {01}x + {02}.
3.1.4 AddRoundKey Transformation
In the AddRoundKey transformation, a Round Key is added to the State - resulted from the
operation of the MixColumns transformation - by a simple bitwise XOR operation. The RoundKey
of each round is derived from the main key using the Key Expansion algorithm [1]. The
encryption/decryption algorithm needs eleven 128-bit RoundKey, which are denoted RoundKey[0]
RoundKey[10] (the first RoundKey [0] is the main key).
3.2 AES decryption
Decryption is a reverse of encryption which inverse round transformations to computes out
the original plaintext of an encrypted cipher-text in reverse order. The round transformation of
decryption uses the functions AddRoundKey, InvMixColumns, InvShiftRows, and InvSubBytes
successively.
3.2.1 AddRoundKey
AddRoundKey is its own inverse function because the XOR function is its own inverse. The
round keys have to be selected in reverse order. The description of the other transformations will be
given as follows.
3.2.2 InvShiftRows Transformation
InvShiftRows exactly functions the same as ShiftRows, only in the opposite direction. The
first row is not shifted, while the second, third and fourth rows are shifted right by one, two and three
bytes respectively.
3.2.3 InvSubBytes transformation
The InvSubBytes transformation is done using a once-pre- calculated substitution table called InvS-
box. That InvS-box table contains 256 numbers (from 0 to 255) and their corresponding values.
InvS-box is presented in Table II.

5. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print),
ISSN 0976 - 6375(Online), Volume 6, Issue 1, January (2015), pp. 95-100 © IAEME
99
3.2.4 InvMixColumns Transformation
In the InvMixColumns transformation, the polynomials of degree less than 4 over GF(28
),
which coefficients are the elements in the columns of the state, are multiplied modulo (x4
+ 1) by a
fixed polynomial d(x) = {0B}x3
+ {0D}x2
+ {09}x + {0E}, where {0B}, {0D}; {09}, {0E} denote
hexadecimal values.The implementation of the AES is carried out using VHDL.
IV.AES IMPLEMENTATION USING VHDL
The Figure 2 shows the AES core architecture implemented for Software Defined radio framework.
Figure 2: Architecture of AES core
V. RESULTS
The following results were obtained for individual steps on AES encryption method. The
design has been coded by VHDL. All the results are simulated using Xilinx ISE simulator. The
results of simulating the encryption algorithm from the ISE simulator are shown in Figure.3
a)
b)

6. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print),
ISSN 0976 - 6375(Online), Volume 6, Issue 1, January (2015), pp. 95-100 © IAEME
100
c)
d)
Figure 3: Simulation waveforms on Xilinx ISE simulator for different steps of encryption. a) S Box
transformation b) Shift row c) Top byte substitution d) Shift row transformation:
VI. CONCLUSIONS
The Advanced Encryption Standard algorithm is a symmetric block cipher that can process
data blocks of 128 bits through the use of cipher keys with lengths of 128, 192, and 256 bits. An
efficient FPGA implementation of 128 bit block and 128 bit key AES algorithm has been presented
in this paper. This can be used for secure data transmission in various wireless communication
standards without changing the hardware. The proposed design is implemented based on the
iterative approach for cryptographic algorithms. There is a lot of potential applications of SDRs and
in future we will see that a wide array of radio applications like Blue- tooth, WLAN, GPRS, Radar,
WCDMA etc. being implemented by using SDR technology [6].
VII. REFERENCES
1. J. Mitola III. Software Radio Architecture. Wiley-Interscience, 2000
2. B. Bing and N. Jayant. A Cell phone for all Standards.IEEE Spectrum, May 2002.
3. SPEAKeasy web page, http://www.if.afrl.af.mil/div/IFB/techtrans/datasheets/Speakeasy
.html
4. M. W. Oliphant. Radio Interfaces Make the Difference in 3G Cellular Systems. IEEE
Spectrum Magazine, Vol. 37,No. 10, October 2000
5. FIPS 197, “Advanced Encryption Standard (AES)”, November 26, 2001.
6. Online reference, Available: http://www.broadcastpapers.com.
7. Anubhav Gupta and Harish Bansal, “Design of Area Optimized AES Encryption Core Using
Pipelining Technology” International journal of Electronics and Communication Engineering
&Technology (IJECET), Volume 4, Issue 2, 2012, pp. 308 - 314, ISSN Print: 0976- 6464,
ISSN Online: 0976 –6472.