24. PEAR LAB Utsunomiya Univ.
参考)シーケンサの回路記述
2016/8/25 IPSJ SIGEMB8月研究会(SWEST18共催)@下呂温泉 26
// Process for state transition
always @(posedge CLK)
begin
if(RESET) begin state <= 0; end
else begin
case(state)
0: if(BTN[0]) state <= 1;
1: state <= 2;
2: if(length != 0) state <= 3; else state <= 8;
3: if(length == 0) state <= 4; else state <= 3;
4: state <= 5;
5: state <= 1;
8: state <= 5;
default: state <= 0;
endcase
end
end