1. Operational Transconductance Amplifier (OTA)
in 45nm CMOS
Jie Wang
Ming Hsieh Department of Electrical Engineering
University of Southern California, Los Angeles, CA 90089
December 3, 2014

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Your Name EE 536a Final Project Presentation December 3, 2014
 Statement of the problem: High Performance OTA
 Main challenges:
Large Range of Vin,
100GHz 𝑓𝑢
5000V/us Slew Rate
 General approach:
Two Amplifiers + MUX
Pole Cancelling
Large Current, Smaller Cc
Introduction

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Your Name EE 536a Final Project Presentation December 3, 2014
Block Diagram

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 Step1: Fix current
 Step 2: Fix gain
 Step 3: Calculate required 𝑔𝑚
 Step 4: Test u𝐶 𝑜𝑥
 Find
𝑊
𝐿
General Design Strategy
gm= 2𝑢𝐶 𝑜𝑥
𝑊
𝐿
𝐼 𝑑
𝑟𝑜 =
1
𝜆𝐼 𝑑
Gain = gm(𝑟𝑜𝑝//𝑟𝑜𝑛)

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Your Name EE 536a Final Project Presentation December 3, 2014
How to Find u𝐶 𝑜𝑥
Betaeff =u𝐶 𝑜𝑥
𝑊
𝐿

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Your Name EE 536a Final Project Presentation December 3, 2014
NMOS Based Input Stage Amplifier
𝑝1 ≈
1
𝑔𝑚2 𝐶𝑐 𝑅1 𝑅2
𝑝2 ≈
𝑔𝑚2 𝐶 𝐶
𝐶 𝐶 𝐶2
=
𝑔𝑚2
𝐶2
𝐴 𝐷𝐶 = 𝑔𝑚1 𝑔𝑚2 𝑅1 𝑅2
𝑧 =
1
𝐶𝑐(
1
𝑔𝑚2
− 𝑅 𝑧)
𝑓𝑢 =
𝑔𝑚1
𝐶 𝐶
𝑉𝑜𝑢𝑡
𝑡
=
𝐼
𝐶 𝐶

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Your Name EE 536a Final Project Presentation December 3, 2014
NMOS Based Input Stage Amplifier[1]
First Stage Gain:
𝑔𝑚7(𝑟𝑜7//𝑟𝑜41)
Second Stage Gain:
𝑔𝑚43(𝑟𝑜43//𝑟𝑜42)
gm= 2𝑢𝐶 𝑜𝑥
𝑊
𝐿
𝐼 𝑑
𝑟𝑜 =
1
𝜆𝐼 𝑑

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Your Name EE 536a Final Project Presentation December 3, 2014
First Stage Performance
I=110uA
Gain= 30dB
𝑟𝑜𝑛//𝑟𝑜𝑝= 26.67K Ω
gm=1.2mΩ−1
𝑢 𝑛 𝐶 𝑜𝑥 = 500u
𝑊
𝐿
= 12

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Second Stage Performance
𝐼 𝑑= 8mA,
Gain= 30dB
𝑟𝑜𝑛//𝑟𝑜𝑝 =417.7Ω
𝑔 𝑚𝑝 = 75m Ω−1
𝑢 𝑝 𝐶 𝑜𝑥 = 15u
𝑊
𝐿
= 24580

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Overall Performance
When Input at 800mV

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PMOS Based Input Stage Amplifier

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Your Name EE 536a Final Project Presentation December 3, 2014
First Stage Performance

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Second Stage Performance

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Overall Performance

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MUX
Vin as a select signal

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Overall Performance
Almost the same as before

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Band-gap Reference Motivation
Generate Vgs for NMOS
carrying tail current

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Band-gap Reference[2]
𝑉𝐺𝑆 𝑇 ≈ 𝑉𝐺𝑆 𝑇0 + [𝐾 𝑇 + 𝑉𝐺𝑆 𝑇0 − 𝑉𝑇𝐻 𝑇0 − 𝑉𝑂𝐹𝐹](
𝑇
𝑇0
− 1)
𝑉𝐺𝑆0 − 𝑉𝐺𝑆1 = 𝑛𝑉𝑡 𝑙𝑛𝑁
𝑉𝑟𝑒𝑓 =
𝑉𝐺𝑆0 + 𝑉𝑅1 + 𝑉𝑅3 =
𝑉𝐺𝑆 𝑇0
+ 𝐾 𝑇 + 𝑉𝐺𝑆 𝑇0 − 𝑉𝑇𝐻 𝑇0 − 𝑉𝑂𝐹𝐹
𝑇
𝑇0
− 1
+
𝑅1 + 𝑅3
𝑅0
𝑛𝑉𝑡 𝑙𝑛𝑁

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Band-gap Reference
Name After Tuning
𝑊
𝐿 M0
5
𝑊
𝐿 M1
11.5
𝑊
𝐿 M3,4
0.8
𝑊
𝐿 M5,6
8
𝑊
𝐿 M7
32
𝑅0 30kΩ
𝑅1 150kΩ
𝑅2 50kΩ
𝑅3 100kΩ
𝑅4 100kΩ

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Vref
Add a voltage dividor to
get desired votlage
reference

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Your Name EE 536a Final Project Presentation December 3, 2014
OTA Schematic

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Your Name EE 536a Final Project Presentation December 3, 2014
Unity-Gain Closed-Loop Small-Signal Response
𝐴
1 + 𝐴
≈ 1
3dB BW increase from 6KHz to 26MHz
A = 74dB = 5000
Input at 800mV

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Your Name EE 536a Final Project Presentation December 3, 2014
Unity-Gain Closed-Loop Small-Signal Transient

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Unity-Gain Closed-Loop Large-Signal Transient

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Open-Loop Input-Referred Voltage Noise
Corner frequency
100 Hz
Vn,in=
𝐾
𝐶 𝑜𝑥 𝑊𝐿𝑓
=0.013
𝑓1
𝑓
=
3𝑔 𝑚 𝐾
8𝑘𝑇𝑊𝐿𝐶 𝑜𝑥
=141.65KHz

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CMRR
80dB at 1Hz
38dB at 10MHz

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Your Name EE 536a Final Project Presentation December 3, 2014
PSRR
67dB at 1 Hz
32 dB at 10MHz

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Your Name EE 536a Final Project Presentation December 3, 2014
Open-Loop Small-Signal Response at Corners
0.9V -20 𝑜
@200mV of Input
Gain: 68dB
PM:680

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Your Name EE 536a Final Project Presentation December 3, 2014
Open-Loop Small-Signal Response at Corners
0.9V +20 𝑜
@200mV of Input
Gain: 64dB
PM:760

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Your Name EE 536a Final Project Presentation December 3, 2014
0.9V 85 𝑜 @200mV of Input
Gain: 61dB
PM:800
T goes up
Gain goes
down
Open-Loop Small-Signal Response at Corners

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Your Name EE 536a Final Project Presentation December 3, 2014
Open-Loop Small-Signal Response at Corners
1V -20 𝑜
@200mV of Input
Gain: 74dB
PM:670

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Your Name EE 536a Final Project Presentation December 3, 2014
Open-Loop Small-Signal Response at Corners
1V 20 𝑜
@200mV of Input
Gain: 66dB
PM:700

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Your Name EE 536a Final Project Presentation December 3, 2014
Open-Loop Small-Signal Response at Corners
1V 85 𝑜
@200mV of Input
Gain: 64dB
PM:710

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Your Name EE 536a Final Project Presentation December 3, 2014
Open-Loop Small-Signal Response at Corners
1.1V -20 𝑜
@200mV of Input
Gain: 64dB
PM:700

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Your Name EE 536a Final Project Presentation December 3, 2014
Open-Loop Small-Signal Response at Corners
1.1V 20 𝑜
@200mV of Input
Gain: 61dB
PM:770

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Your Name EE 536a Final Project Presentation December 3, 2014
Open-Loop Small-Signal Response at Corners
1.1V 85 𝑜
@200mV of Input
Gain: 55 dB
PM:820

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Your Name EE 536a Final Project Presentation December 3, 2014
Large-Signal Output Spectrum
Output swing:0.7V

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Your Name EE 536a Final Project Presentation December 3, 2014
Performance Summary
＊exception for input at 400mV-500mV
Name Target Analytical Estimation Simulated Result
Avd ≥60dB 60dB ＊≥60dB Best:75dB
fu ≥100GHz 300MHz 20MHz
SR ≥5000V/US 62.5V/us ~13000V/s
ts ≤50ps 10000ps 81.63n
Vn,in ≤1nV/sqrt(Hz) 0.013 0.14nV/sqrt(Hz)
f1/f ≤10KHz 141.65KHz 100Hz
THD 0.001% 0 0
CMRR ≥80dB at DC
≥60dB at 10MHz
≥80dB at DC
≥60dB at 10MHz
80dB at DC
40dB at 10MHz
PSRR ≥60dB at DC
≥40dB at 10MHz
≥60dB at DC
≥40dB at 10MHz
67dB at DC
32dB at 10MHz
Vdd 1V 1V 1V
Vin,rr ≥0.9V ≥0.9V ≥0.9V
Vin,CM 0.1-0.9V 0.1-0.9 0.1-0.9
Vout,rr ≥0.9V ≥0.9V 0.7V
IDC ≤25mA ≤25mA ≤25mA
CL 100fF 100fF 100fF
PM ≥60o 60o ＊≥60o Best 80o
GM ≥10dB ≥10dB ≥20dB

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Your Name EE 536a Final Project Presentation December 3, 2014
 Highlights of the design:
Mixed Signal Design
 Improvement suggestions:
Increase current to increase the Slew Rate.
Pole cancellation to Increase unity-gain cut-off frequency
 Lessons learned
Start the project early
Conclusions

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Your Name EE 536a Final Project Presentation December 3, 2014
 [1] K.T. Hafeez. ‘’Design of Two Stage Operational Amplifier’’, IIT.
Web:
https://www.youtube.com/channel/UCEXcqylc45jam5xa6vvEG7A
 [2]H.L. Wang, X.X. Zhang, Y.J. Dai, et al. ‘’A Low-Voltage Low-Power
CMOS Voltage Reference Based on Subthreshold MOSFET’’ Journal of
Semiconductors, Vol.32, No.8, Aug 2011
References