M.Tech and B.Tech final year projects list

1. VLSI Domain Projects based on IEEE 2013 & 2014
CODE
MSR01
MSR02
TITLE
Implementation of RNG in FPGA using Efficient Resource Utilization
Low Latency Systolic Montgomery Multiplier for Finite Field Based on
YEAR
2013
2013
MSR03
MSR04
MSR05
MSR06
Pentanomials.
Multi operand Redundant Adders on FPGAs.
16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder.
CORDIC Designs for Fixed Angle of Rotation.
A High Speed Binary Floating Point Multiplier Using Dadda
2013
2013
2013
2013
MSR07
Algorithm.
An FPGA Based High Speed Ieee-754 Double Precision Floating Point
2013
MSR08
MSR09
Multiplier Using Verilog HDL.
Design A DSP Operations Using Vedic Mathematics.
Design And Implementation Of 32 Bit Unsigned Multiplier Using CLA
2013
2013
MSR10
And CSLA.
Design And Implementation Of Truncated Multipliers For Precision
2013
MSR11
Improvement.
VLSI Implementation Of Fast Addition Using Quaternary Signed Digit
2013
MSR12
Number System
Design of High Speed Low Power Multiplier Using Reversible Logic:
2013
MSR13
MSR14
MSR15
A Vedic Mathematical Approach.
Design Of high Performance 64 Bit MAC Unit.
Efficient Approaches To Design A Reversible Floating Point Divider
High Performance Hardware Implementation Of AES Using Minimal
2013
2013
2013
MSR16
Resources.
Implementation And Comparison Of Effective Area Efficient
2013
MSR17
MSR18
Architectures For CSLA.
Implementation Of Binary To Floating Point Converter Using HDL
Least Complex S-Box And Its Fault Detection For Robust Advanced
2013
2013
MSR19
MSR20
Encryption Standard Algorithm.
Novel High Speed Vedic Mathematics Multiplier Using Compressors.
2013
Novel Method Of Digital Clock Frequency Multiplication And Division 2013
MSR21
Using Floating Point Arithmetic.
FPGA Implementation of 16-Point Radix-4 Complex FFT Core Using 2013
NEDA
M.S.R.PROJECTS
www.facebook.com/ M.S.R.Projects
cell no:+91 9581464142
ADDRESS: 2nd floor, above mannapuram gold loan, beside sha theater, ganesh nagar, balanagar, hyd.

2. VLSI Domain Projects based on IEEE 2013 & 2014
MSR22
VLSI Implementation Of A High Speed Single Precision Floating Point
2013
MSR23
Unit Using Verilog.
A Novel Approach For Parallel CRC Generation For High Speed
2012
Application.
MSR24
Design And Implementation Of Automated Wave Pipeline
2012
Circuit Using ASIC
MSR25
Design And Implementation Of A High Performance Multiplier Using
2012
MSR26
HDL.
Design and Implementation of High-Performance High-Valency Ling
2012
MSR27
Adders.
High Speed Modified Booth Encoder Multiplier For Signed And
2012
Unsigned Numbers.
MSR28
FPGA Implementation Of 16 Bit BBS And LFSR PN
2012
Sequence Generator
MSR29
MSR30
High-Speed Low-Power Viterbi Decoder Design For TCM Decoders.
Design And Implementation Of Carry Select Adder Without Using
2012
2012
MSR31
MSR32
MSR33
MSR34
Multiplexers.
Implementation Of Power Efficient Vedic Multiplier.
Low-Power And Area-Efficient Carry Select Adder.
A Parallel-Serial Decimal Multiplier Architecture.
A High Speed And Area Efficient Booth Recoded Wallace Tree
2012
2012
2012
2012
MSR35
MSR36
MSR37
MSR38
MSR39
MSR40
Multiplier For Fast Arithmetic Circuits.
An Improved BCD Adder Using 6-Lut FPGAS.
Design And Implementation Of TPG-LFSR
Design And Implementation Of High Performance Barrel Integer Adder
FPGA Implementation Of Chaotic Pseudo Random Bit Generators
An Efficient Implementation Of Floating Point Multiplier
High Speed ASIC Design Of Complex Multiplier Using Vedic
2012
2012
2012
2012
2011
2011
MSR41
MSR42
Mathematics
Design Of Low Power And High Speed Configurable Booth Multiplier
Design Of Automatic Washing Machine Based On Verilog HDL
MSR43
MSR44
MSR45
Language
Design And Characterization Of Parallel Prefix Adders Using FPGAs
Simulation Of UART Using Verilog HDL
Design Of FPGA Based Traffic Light Controller System
M.S.R.PROJECTS
www.facebook.com/ M.S.R.Projects
cell no:+91 9581464142
ADDRESS: 2nd floor, above mannapuram gold loan, beside sha theater, ganesh nagar, balanagar, hyd.
2011
2011
2011
2011