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8086 Architecture.pptx
- 1. Unit 1 by Prof. Vishalsinh Bais 8086 Architecture
- 2. Syllabus 8086 architecture and pin configuration, Memory addresses space and data organization. Data types. Segment registers, memory segmentation. Software model of 8086 microprocessor. IP & Data registers, Pointer, Index registers. Memory addresses generation.
- 3. Introduction 8086 Microprocessor is an enhanced version of 8085 Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and 16 data lines that provides up to 1MB storage. It consists of powerful instruction set, which provides operations like multiplication and division easily. It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable for system having multiple processors and Minimum mode is suitable for system having a single processor.
- 4. Features of 8086 It has an instruction queue, which is capable of storing six instruction bytes from the memory resulting in faster processing. It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit external data bus resulting in faster processing. It is available in 3 versions based on the frequency of operation − 8086 → 5MHz 8086-2 → 8MHz (c)8086-1 → 10 MHz It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance. Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue. Execute stage executes these instructions. It has 256 vectored interrupts. It consists of 29,000 transistors.
- 5. Comparison between 8085 & 8086 Microprocessor Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor. Address Bus − 8085 has 16-bit address bus while 8086 has 20- bit address bus. Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory. Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an instruction queue. Pipelining − 8085 doesn’t support a pipelined architecture while 8086 supports a pipelined architecture. I/O − 8085 can address 28 = 256 I/O's, whereas 8086 can access 216 = 65,536 I/O's. Cost − The cost of 8085 is low whereas that of 8086 is high.
- 7. Working of 8086 Microprocessor
- 8. 8086 pin configuration Pin No. Name Description 1, 20 Vss (GND) Ground Pin or Negative Pin of Battery 2 39 -16 and 35- AD0 to A19/S6 Multiplexed Address and Data Bus - 17 NMI Non maskable interrupt 18 INTR Interrupt Acknowledge Pin 19 CLK Clock Signal 21 RESET Reset Signal 22 READY Ready Status Signal 23 Wait Signal , 24,25 QS1/ QS0/ALE Multiplexed Pin for Address Latch Enable, Interrupt Acknowledge Pin and Queue Status. 26, 27, 28 Multiple Interrupt Handling pins 29 Lock resources being used , 30, 31 Request Signals 32 Read 33 Minimum mode or Maximum mode 34 Bus High Enable 40 Vcc (5P) Supply Pin
- 10. Segments and Registers ES CS SS DS IP AH BH CH DH AL BL CL DL SP BP SI DI FLAGS AX BX CX DX Extra Segment Code Segment Stack Segment Data Segment Instruction Pointer Accumulator Base Register Count Register Data Register Stack Pointer Base Pointer Source Index Register Destination Index Register BIU registers (20 bit adder) EU registers
- 11. Memory addresses space and data organization
- 13. Flag Register in 8086 Microprocessor Carry Flag (CF): The carry flag will be set only if a carry is generated from the MSB of the result after doing any operation in 8086 Microprocessor. Parity Flag (PF): Parity is related to the number of 1’s contained in the binary data. There exist two types of parity: Even Parity: When the number of 1’s in the binary data are even. Odd Parity: When the number of 1’s in the binary data are odd. For the flag, the PF is set if there exists an even parity in data after the execution of the instruction. Else the flag is reset. Auxiliary-Carry Flag (AF): This flag is set if there is a generation of carrying from a nibble, i.e. 4 bits of data. Zero Flag (ZF): If the result after performing the required operation (Arithmetic or Logical) on the instructions is zero, in that case, the zero flags are set to 1. Else, it remains reset. Sign Flag (SF): If the result after performing any arithmetic or logic operation in the given instruction is negative, then the sign flag is set to 1. Else, for a positive result, the sign flag remains reset. Overflow Flag (OF): This Flag will be set if the register gets overflowed with data after any arithmetic or logic operation. This happens in cases when the carry is getting in in MSB, but there is no space in the register to store the carried out bit. Trap Flag (TF): This flag is used of we need single-step debugging in our code. If the TF is set, then the execution will be done step by step. Otherwise, the free-running operation will be done. Interrupt Flag (IF): This flag is used to enable the Interrupt. The microprocessor is capable of handling interrupts only if this flag is in the set mode. Otherwise, any interrupt raised while the execution of the instructions will not be handled by the microprocessor. Direction Flag (DF): This flag is used for string operations. If this flag is set, the string will be read from higher-order bits to lower order bits and vice versa.
- 14. MCQ On Unit 1 1. A microprocessor is a _________ chip integrating all the functions of a CPU of a computer. A. Multiple B. Single C. Double D. Triple Answer: B. Single 2. The intel 8086 microprocessor is a ________ processor A. 8 bit B. 16 bit C. 32 bit D. 4 bit Answer: B. 16 bit 3. The microprocessor can read/write 16 bit data from or to ______. A. Memory B. I/O Device C. Processor D. register Answer: A. Memory
- 15. 4. In 8086 microprocessor , the address bus is ______ bit wide. A. 12 bit B. 10 bit C. 16 bit D. 20 bit Answer: D. 20 Bit 5. The 16 bit flag of 8086 microprocessor is responsible to indicate __________. A. the condition of result of ALU operation B. the condition of memory C. the result of addition D. the result of subtraction Answer: A. the condition of result of ALU operation 6. The SF is called as ______. A. Service flag B. sign flag C. single flag D. condition flag Answer: B. sign flag 7. The IF is called as ______ . A. initial flag B. indicate flag C. interrupt flag D. inter flag Answer: C. interrupt flag
- 16. 8. The BP is indicated by __________. A. base pointer B. binary pointer C. bit pointer D. digital pointer Answer: A. base pointer 9. The SS is called as ________. A. single stack B. stack segment C. sequence stack D. random stack Answer: B. Stack Segment 10. The index register are used to hold ______. A. Memory register B. offset address C. segment memory D. offset memory Answer: A. memory register 11. The BIU contains FIFO register of size ______ bytes. A. 8 B. 6 C. 4 D. 5 Answer: B. 6
- 18. Extras
- 19. Ground Clock Duty cycle: 33% Power Supply 5V 10% Reset Registers, seg regs, flags CS: FFFFH, IP: 0000H If high for minimum 4 clks
- 20. Address Latch Enable: When high, multiplexed address/data bus contains address information. Address/Data Bus: Contains address bits A15-A0 when ALE is 1 & data bits D15 – D0 when ALE is 0.
- 21. INTEL 8086 - Pin Details 21 INTERRUPT Non - maskable interrupt Interrupt request Interrupt acknowledge
- 22. INTEL 8086 - Pin Details 22 Direct Memory Access Hold acknowledge Hold
- 23. INTEL 8086 - Pin Details 23 Address/Status Bus Address bits A19 – A16 & Status bits S6 – S3
- 24. INTEL 8086 - Pin Details 24 Bus High Enable/S7 Enables most significant data bits D15 – D8 during read or write operation. S7: Always 1. BHE#, A0: 0,0: Whole word (16-bits) 0,1: High byte to/from odd address 1,0: Low byte to/from even address 1,1: No selection
- 25. INTEL 8086 - Pin Details 25 Min/Max mode Minimum Mode: +5V Maximum Mode: 0V Minimum Mode Pins Maximum Mode Pins
- 26. Minimum Mode- Pin Details 26 Read Signal Write Signal Memory or I/0 Data Bus Enable Data Transmit/Rece ive
- 27. Maximum Mode - Pin Details 27 Status Signal Inputs to 8288 to generate eliminated signals due to max mode. S2 S1 S0 000: INTA 001: read I/O port 010: write I/O port 011: halt 100: code access 101: read memory 110: write memory 111: none - passive
- 28. Maximum Mode - Pin Details 28 DMA Request/Grant Lock Output Lock Output Used to lock peripherals off the system Activated by using the LOCK: prefix on any instruction
- 29. Maximum Mode - Pin Details 29 Queue Status Used by numeric coprocessor (8087) QS1 QS0 00: Queue is idle 01: First byte of opcode 10: Queue is empty 11: Subsequent byte of opcode
- 30. References:
Editor's Notes
- Bus Interface Unit (BIU) 1) Bus Interface Unit (BIU) The Instruction Queue contains the set of instruction which is to be executed. To make the processing faster, the 8086 pre-fetches up to 6 instructions in advance and stores them in the Instruction queue. So, whenever one instruction completes its execution, the control unit need not wait for the next instruction to be fetched and then brought for execution because this job is already done and the next instruction that is to be executed is ready in the Instruction queue. 2) Segment Registers Each Segment register can work with 16 bits of binary data. There are 4 types of segment registers: CS: Code Segment Register DS: Data Segment Register SS: Stack Segment Register ES: Extra Segment Register 3) Instruction Pointer The Instruction pointer contains the address of the next instruction that is to be executed. Execution Unit (EU) 1) Control Unit (CU) All the Instructions are executed inside the Control Unit. It is the main component which is responsible for the processing of any processor. 2) Arithmetic Logic Unit (ALU) All the Mathematical and Logical Operations are performed inside the ALU. So, if any instruction needs to perform such operation, the Control Unit handovers it to the ALU. 3) Flag Register The flag Register is of 16-bit length which consists of 9 flags, and the rest 7 bits are of don't care cases. 4) General Purpose Registers The General Purpose Registers are used as containers for storing the values which may be required for executing the instructions. Each General Purpose Register consists of 16 bits. There are 4 types of General Purpose Registers: AX = [AH:AL] BX = [BH:BL] CX = [CH:CL] DX = [DH:DL] 5) Pointers and Index Registers The 8086 contains following Pointers and Index Registers. (Here, IP is not mentioned because it is a part of the BIU) BP: Base Pointer SP: Stack Pointer SI: Source Index DI: Destination Index 6) Operands These may be used within the instructions.
- In the previous section, we have discussed the operation of various sections of the BIU and EU. Now in this section, we will have a look at the overall processing cycle of 8086 microprocessor. So, basically, when an instruction is to be fetched from the memory, then firstly its physical address must be calculated and this is done at the BIU. The physical address of an instruction is given as: PA = Segment address Χ 10 + Offset For example: Suppose the segment address is 2000 H and the offset address is 4356 H. So, the generated physical address is 24356 H. Here, the code segment register provides the base address of the code segment which is combined with the offset address. The code segment contains the instructions. Each time an instruction is fetched the offset address inside the code segment gets incremented. So, once the physical address of an instruction is calculated by the BIU of the processor, it sends the memory location by the address bus to the memory. Further, the desired instruction at that memory location which is present in the form of the opcode is fetched by the microprocessor through the data bus. Suppose the instruction is ADD BL, CL. But, inside the memory, it will be in the form of an opcode. So, this opcode is sent to the control unit. The control unit decodes the opcode and generates control signals that inform the BL and CL register to release the value stored in it. Also, it signals the ALU to perform the ADD operation on that particular data. It is noteworthy that in any instruction, like ADD BL, CL. BL denotes the destination of the result of the add operation. This clearly shows that whatever, the operation is performed its result must be stored in the first register i.e., BL for this particular example. Let us take another example: Consider an instruction, ADD CL, 05H. This means that the operand which is 05H is to be added with the data present in the CL register and is stored in that particular register i.e., CL. In such condition, the operand is not provided to the control unit as only the opcode is required to be decoded by the CU. Hence the operand is directly provided to the ALU. Also, the status of this result is stored in the flag register. So, whenever, ALU carries out an operation, it simultaneously generates the result as well as its status. It is to be noteworthy that in BIU, pipelining fails whenever there is branching in the instruction. This is because generally instructions are present in a sequential manner. But, sometimes the instructions are required to be executed unsequentially. However, in the queue, the instructions are stored sequentially. So, in case there exist a need for any random instruction to be decoded. The opcode stored in the queue will become invalid and must be cleared at that particular time. So, this is all about the block diagram and working of 8086 microprocessor.
- Pin description of 8086 Microprocessor VCC – Pin number 40 – At this pin, the external power supply of + 5V is provided to the processor. VSS – Pin number 1 and 20 – These two pins acts as the ground. This pin directs the extra current of the microprocessor to ground. AD0 – AD15 – Pin number 2 to 16 and 39 – These are the multiplexed address and data bus. We know that the 8086 microprocessor has 20-bit address bus and 16-bit data bus. So, the 16 lines of the address and data bus are multiplexed together so as to reduce the number of lines inside the IC. We are aware of the fact that at a time either address or data will be transmitted by the bus. So, at a particular time only either the address or the data bus will be enabled from the multiplexed buses. A16/S3, A17/S4, A18/S5 and A19S6 – Pin number 35 to 38 – Out of 20 address bits, 4 are present in the multiplexed form with the status signals. In the case of memory operations, these pins act as an address bus and contain the memory address of any particular instruction or data. However, from I/O operations these pins are low that shows the status of the processor. Basically, the signal at S3 and S4 show that which segment is currently accessed by the microprocessor among the four segments present in it. The table below will show the encoding of S3 and S4: Also, S5, when enabled, shows the presence of an interrupts in the microprocessor. So, basically, it serves as an interrupt flag. The signal at S6 shows the status of the bus master for the current operation. More simply we can say, whether the 8086 is the bus master or any other proficient device is acting as the bus master. When 0 is present as the signal at this pin then it indicates the 8086 is holding the access of the bus otherwise it is high i.e., 1. BHE’ / S7 – Pin number 34 – BHE is an acronym for Bus High Enable. The combination of the BHE signal and S7 status informs about the existence of the data on the bus. Also, different combinations show whether the bus is containing overall 16 bit, upper byte or lower byte of the data. The table below represents the status for the signal at this pin: MN/MX’ – Pin number 33 –The status at this particular pin shows whether the processor is operating in the minimum mode or maximum mode. A signal 0 at this pin informs that the 8086 is operating in maximum mode i.e., multiple processors. While signal 1 shows the operation under minimum mode i.e., single processor. RD’ – Pin number 32 – An active low signal at this pin shows that the microprocessor is performing read operation with either memory or I/O devices. CLK – Pin number 19 – A signal at this pin provides the timing to the internal operations that are being executed inside the microprocessor. NMI – Pin number 17 – NMI is Non-maskable interrupt. These are basically uncontrollable interrupts generated inside the processor. When an NMI occurs, then an interrupt service routine is generated by the interrupt vector table. TEST – Pin number 23 – This pin basically shows the wait instruction. Whenever a low signal at this pin occurs then the processing inside the processor continues. As against, in case of the high signal, the processor has to wait for the disabling of this pin. INTR – Pin number 18 – INTR stands for an interrupt request. The processor after each clock cycle samples the INTR and if the signal at this pin is found to be high then the processor controls that interrupt internally. READY – Pin number 22 – This signal is used by the peripherals and memory devices in order to show the readiness for the next operation. RESET – Pin number 21 – Whenever this pin is enabled then it resets the processor and other devices connected to the system by immediately terminating the recent task. Pins in Minimum mode INTA’ – Pin number 24 – It is an interrupt acknowledge pin. Whenever an INTR signal is generated, then the microprocessor generates INTA signal, as a response to that interrupt. ALE – Pin number 25 – ALE is an abbreviation for address latch enable. Whenever an address is present in the multiplexed address and data bus, then the microprocessor enables this pin. This is done to inform the peripherals and memory devices about fetching of the data or instruction at that memory location. DEN’ – Pin number 26 – DEN is used for data enable. This is an active low pin that means whenever a 0 is present at this pin then the transceiver gets enabled and it separates the data from the multiplexed address and data bus. DT/R’ – Pin number 27 – This pin is used to show whether the data is getting transmitted or is received. A high signal at this pin provides the information regarding the transmission of data. While a low indicates reception of data. M/IO’ – Pin number 28 – This pin indicates whether the processor is performing an operation with memory or I/O devices. Whenever a high is present at this pin then it shows the operation is carried out through the memory. While a low signal shows operation through I/O devices. WR’ – Pin number 29 – An active low signal at this pin indicates that the processor is performing write operation from either memory or I/O devices. HOLD – Pin number 31 – When an external device enables this pin then the processor stops accessing the buses immediately after the recent task gets over. HLDA – Pin number 30 – This pin is used as a response pin for the hold request. Once request for accessing the buses is produced by an external entity. Then the microprocessor acknowledges the device that its request will be considered once it gets over by the current operation. Pins in Maximum mode S0‘, S1‘ and S2‘ – Pin number 26 to 28 – These are basically 3 status pins and are active low. This means that if the status at all the 3 pins is 0 then it shows that multiple interrupts are to be handled in maximum mode. The table below is representing the status of the processor in different combinations: QS0 and QS1 – Pin number 24 and 25 – These two pins indicate the status of the 6-byte pre-fetch queue present in the architecture of 8086. LOCK’ – Pin number 29 –This pin is involved in maximum mode operation. So, basically, when a single processor is accessing the buses and peripherals then it locks the resources being used by it. So, that no other entity can access it until the recent processor frees it. RQ’/ GT0‘ and RQ’/ GT1‘ – Pin number 30 and 31 – Due to the involvement of multiple processors, these pins indicate the request and grant permission for accessing the buses, memory and peripherals. This is all about the pin diagram and description of the 8086 microprocessor.
- The size of address bus of 8086 is 20 and is able to address 1 Mbytes ( ) of physical memory, but all this memory is not active at one time. Actually, this 1Mbytes of memory are partitioned into 16 parts named as segments. Size of the each segment is 64Kbytes (65,536). Only four of these segments are active at a time: Code segment holds the program instruction codes Stack segment is used to store interrupt and subroutine return addresses Data segment stores data for the program Extra segment is an extra data segment (often used for shared data) Each of these segments are addressed by an address stored in corresponding segment registers: CS(code segment), SS(stack segment), DS(data segment), and ES(extra segment). These registers contain a 16-bit base address that points to the lowest addressed byte of the segment. Because the segment registers cannot store 20 bits, they only store the upper 16 bits. The BIU takes care of this problem by appending four 0's to the low-order bits of the segment register. In effect, this multiplies the segment register contents by 16. The segment registers are user accessible, which means that the programmer can change the content of segment registers through software.
- Memory segmentation: To increase execution speed and fetching speed, 8086 segments the memory. It’s 20 bit address bus can address 1MB of memory, it segments it into 4 64kB segments. 8086 works only with four 64KB segments within the whole 1MB memory. The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit (BIU), and The Execution Unit (EU). These are explained as following below. 1. The Bus Interface Unit (BIU): It provides the interface of 8086 to external memory and I/O devices via the System Bus. It performs various machine cycles such as memory read, I/O read etc. to transfer data between memory and I/O devices. BIU performs the following functions- It generates the 20 bit physical address for memory access. It fetches instructions from the memory. It transfers data to and from the memory and I/O. Maintains the 6 byte prefetch instruction queue(supports pipelining). BIU mainly contains the 4 Segment registers, the Instruction Pointer, a prefetch queue and an Address Generation Circuit. Instruction Pointer (IP): It is a 16 bit register. It holds offset of the next instructions in the Code Segment. IP is incremented after every instruction byte is fetched. IP gets a new value whenever a branch instruction occurs. CS is multiplied by 10H to give the 20 bit physical address of the Code Segment. Address of the next instruction is calculated as CS x 10H + IP. Example: CS = 4321H IP = 1000H then CS x 10H = 43210H + offset = 44210H This is the address of the instruction. Code Segment register: CS holds the base address for the Code Segment. All programs are stored in the Code Segment and accessed via the IP. Data Segment register: DS holds the base address for the Data Segment. Stack Segment register: SS holds the base address for the Stack Segment. Extra Segment register: ES holds the base address for the Extra Segment. Address Generation Circuit: The BIU has a Physical Address Generation Circuit. It generates the 20 bit physical address using Segment and Offset addresses using the formula:Physical Address = Segment Address x 10H + Offset Address 6 Byte Pre-fetch Queue: It is a 6 byte queue (FIFO). Fetching the next instruction (by BIU from CS) while executing the current instruction is called pipelining. Gets flushed whenever a branch instruction occurs. 2. The Execution Unit (EU): The main components of the EU are General purpose registers, the ALU, Special purpose registers, Instruction Register and Instruction Decoder and the Flag/Status Register. Fetches instructions from the Queue in BIU, decodes and executes arithmetic and logic operations using the ALU. Sends control signals for internal data transfer operations within the microprocessor. Sends request signals to the BIU to access the external module. It operates with respect to T-states (clock cycles) and not machine cycles. 8086 has four 16 bit general purpose registers AX, BX, CX and DX. Store intermediate values during execution. Each of these have two 8 bit parts (higher and lower). AX register: It holds operands and results during multiplication and division operations. Also an accumulator during String operations. BX register: It holds the memory address (offset address) in indirect addressing modes. CX register: It holds count for instructions like loop, rotate, shift and string operations. DX register: It is used with AX to hold 32 bit values during multiplication and division. Arithmetic Logic Unit (16 bit): Performs 8 and 16 bit arithmetic and logic operations. Special purpose registers (16-bit): Stack Pointer: Points to Stack top. Stack is in Stack Segment, used during instructions like PUSH, POP, CALL, RET etc. Base Pointer: BP can hold offset address of any location in the stack segment. It is used to access random locations of the stack. Source Index: It holds offset address in Data Segment during string operations. Destination Index: It holds offset address in Extra Segment during string operations. Instruction Register and Instruction Decoder: The EU fetches an opcode from the queue into the instruction register. The instruction decoder decodes it and sends the information to the control circuit for execution. Flag/Status register (16 bits): It has 9 flags that help change or recognize the state of the microprocessor. 6 Status flags: carry flag(CF) parity flag(PF) auxiliary carry flag(AF) zero flag(Z) sign flag(S) overflow flag (O) Status flags are updated after every arithmetic and logic operation. 3 Control flags: trap flag(TF) interrupt flag(IF) direction flag(DF) These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI, STI, etc.
- Segmentation is the process in which the main memory of the computer is logically divided into different segments and each segment has its own base address. It is basically used to enhance the speed of execution of the computer system, so that the processor is able to fetch and execute the data from the memory easily and fast. Need for Segmentation – The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below) called as Segment Registers. Code segment register (CS): is used for addressing memory location in the code segment of the memory, where the executable program is stored. Data segment register (DS): points to the data segment of the memory where the data is stored. Extra Segment Register (ES): also refers to a segment in the memory which is another data segment in the memory. Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment is that segment of memory which is used to store stack data. The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one of the 1MB memory locations. The four segment registers actually contain the upper 16 bits of the starting addresses of the four memory segments of 64 KB each with which the 8086 is working at that instant of time. A segment is a logical unit of memory that may be up to 64 kilobytes long. Each segment is made up of contiguous memory locations. It is an independent, separately addressable unit. Starting address will always be changing. It will not be fixed. Note that the 8086 does not work the whole 1MB memory at any given time. However, it works only with four 64KB segments within the whole 1MB memory. Types Of Segmentation – Overlapping Segment – A segment starts at a particular address and its maximum size can go up to 64kilobytes. But if another segment starts along with this 64kilobytes location of the first segment, then the two are said to be Overlapping Segment. Non-Overlapped Segment – A segment starts at a particular address and its maximum size can go up to 64kilobytes. But if another segment starts before this 64kilobytes location of the first segment, then the two segments are said to be Non-Overlapped Segment.
- How can a 20-bit address be obtained, if there are only 16-bit registers? However, the largest register is only 16 bits (64k); so physical addresses have to be calculated. These calculations are done in hardware within the microprocessor. The 16-bit contents of segment register gives the starting/ base address of particular segment. To address a specific memory location within a segment we need an offset address. The offset address is also 16-bit wide and it is provided by one of the associated pointer or index register. To be able to program a microprocessor, one does not need to know all of its hardware architectural features. What is important to the programmer is being aware of the various registers within the device and to understand their purpose, functions, operating capabilities, and limitations. The above figure illustrates the software architecture of the 8086 microprocessor. From this diagram, we see that it includes fourteenl6-bit internal registers: the instruction pointer (IP), four data registers (AX, BX, CX, and DX), two pointer registers (BP and SP), two index registers (SI and DI), four segment registers (CS, DS, SS, and ES) and status register (SR), with nine of its bits implemented as status and control flags. The point to note is that the beginning segment address must begin at an address divisible by 16.Also note that the four segments need not be defined separately. It is allowable for all four segments to completely overlap (CS = DS = ES = SS).
- There are two categories of flag register: Condition flags Control flags 1) Condition flags The conditional flags are set or reset after any arithmetic or logical operation is performed on an 8 bit or 16-bit number. This category consists of the following 6 flags: Carry Flag (CF): The carry flag will be set only if a carry is generated from the MSB of the result after doing any operation in 8086 Microprocessor. Parity Flag (PF): Parity is related to the number of 1’s contained in the binary data. There exist two types of parity: Even Parity: When the number of 1’s in the binary data are even. Odd Parity: When the number of 1’s in the binary data are odd. For the flag, the PF is set if there exists an even parity in data after the execution of the instruction. Else the flag is reset. Auxiliary-Carry Flag (AF): This flag is set if there is a generation of carrying from a nibble, i.e. 4 bits of data. Zero Flag (ZF): If the result after performing the required operation (Arithmetic or Logical) on the instructions is zero, in that case, the zero flags are set to 1. Else, it remains reset. Sign Flag (SF): If the result after performing any arithmetic or logic operation in the given instruction is negative, then the sign flag is set to 1. Else, for a positive result, the sign flag remains reset. Overflow Flag (OF): This Flag will be set if the register gets overflowed with data after any arithmetic or logic operation. This happens in cases when the carry is getting in in MSB, but there is no space in the register to store the carried out bit. 2) Control flags The control flags are used to navigate the microprocessor for certain operations. There are 3 types of control flags: Trap Flag (TF): This flag is used of we need single-step debugging in our code. If the TF is set, then the execution will be done step by step. Otherwise, the free-running operation will be done. Interrupt Flag (IF): This flag is used to enable the Interrupt. The microprocessor is capable of handling interrupts only if this flag is in the set mode. Otherwise, any interrupt raised while the execution of the instructions will not be handled by the microprocessor. Direction Flag (DF): This flag is used for string operations. If this flag is set, the string will be read from higher-order bits to lower order bits and vice versa.