1-Introduction and Crystal Structure of Solids-已解鎖.pdf
1. Ch1-1
半導體元件物理
Prof. Hsin-Hui Hu
Lecture: Tue 18:30-21:10
Textbook:
[1] Donald Neamen, “Semiconductor Physics and Devices,” 4th Edition,
McGraw-Hill, 2011.
[2] S. M. Sze, M. K. Lee, “Semiconductor Devices: Physics and Technology,”
3nd Edition, Wiley, 2002
Reference:
[1] Donald Neamen, 楊賜麟譯, “半導體物理與元件”第四版
[2] S. M. Sze,曾俊元譯, “半導體元件物理與製作技術”第三版, 交大出版社
[3] Ben G. Streetman, “Solid State Electronic Devices,” 6rd Edition, Prentice
Hall, 2006
[4] S. M. Sze, “Physics of Semiconductor Devices,” 3rd Edition, Wiley, 2007
13. Ch1-13
2017F Major Capital Spenders Source: IC Insights.
723.05億
100億
20億
Samsung has ended Intel's 25-year run as the world's biggest seller of chipsets after it
posted its 2017 end of year financials.
38. Ch1-38
From: Hossain M. Fahad et. al. “Are Nanotube Architectures More Advantageous Than Nanowire Architectures For Field Effect Transistors?” 2012
The single gate classical planar transistor topology dominated logic and memory applications till the 32 nm
technology node. With increasing gate and off-state leakage currents as well as other effects associated with
ultra short channel devices, the classical transistor suffered from massive amounts of heat dissipation. High-
Κ dielectric and metal gate stacks helped alleviate the gate leakage problem beyond the 45 nm technology
node but it was evident a dramatic change in the device architecture was needed beyond the 32 nm
technology node. This lead to the evolution of multiple gate topology in ultra-thin bodies.
45. Ch1-45
N7
TSMC considers their 7-nanometer node (N7) the most advanced logic technology currently
shipping. Other than a handful of key lead customers, most TSMC customers are said to go directly
from their N16 to N7. Their N10 node is considered to be a short-lived node, largely intended to
serve as yield-learning. When going from N16 to N7, N7 provides 3.3x routed gate density as well as
around 35-40% speed improvement or 65% lower power.
TSMC Logic Nodes
Source from: xfastest, 2019-07-29
N7:第一代 7 nm
N7P: (2019/07) 第二代7 nm。第一代的改良版，仍然採用DUV，相同的設計準則，且和N7是完全IP相容。
N7+: 7 nm 強效版， Q2 2019 量產，導入EUV。
N5 => N5P => N4 => N4P
N4P
效能: 較N5快11%，較N4快6%。
相較N5，功耗效率22%↑，電晶體
密度6% ↑ 。
減少光罩層數 => 晶片生產週期↓
。
2021/10/26
52. I/O
SOC
GPU
CPU
3D Foveros Base Die
Ch1-52
Intel’s 14th Gen Meteor Lake (TBA)
CPU Tile Intel 4
3D Foveros Base Die 22FFL/Intel 16
GPU Tile TSMC 5nm (N5)
SoC Tile TSMC 6nm (N6)
I/O Tile TSMC 6nm (N6)
• First tile-based CPU. i.e. first disaggregated CPU, with different tiles
built on differing processes. From monolithic and hybrid designs to tiles.
• Intel 4 and 3 are Intel’s first nodes deploying EUV.
Intel原本
晶片自己設計
自己生產
Intel 4
五個不同晶片
合一
55. Ch1-55
Samsung - The evolution of FET transistors
Samsung uses the MBCFET design for
its 3nm chips
(Multi-Bridge Channel)
56. Ch1-56
Samsung Technology Roadmap
• On its FinFET technologies, both 5LPP and 4LPP nodes are new to the roadmap,
and set for high-volume manufacturing (HVM) in 2021 and 2022, respectively.
multi-bridge channel field-
effect transistors (MBCFETs)
LPE (Low-Power Early)、LPP (Low-Power Plus)、
LPC (Low-Power Compact)、LPU (Low-Power ultimate)
61. Ch1-61
Source: Semiconductor Devices, 2/E by S. M. Sze
(LED)
(BJT)
(HBT)
(TED)
(NVSM)
(CCD)
bDenotes a two-terminal device, otherwise it is a three- or four-terminal device.
64. Ch1-64
Band Gap and Resistivity
Eg = 1.1 eV Eg = 8 eV
Aluminum
2.7 mWcm
Sodium
4.7 mWcm
Silicon
~ 1010 mWcm
Silicon dioxide
> 1020 mWcm
Conductors Semiconductor Insulator
• Conductivity of Semiconductor can be controlled by dopant
concentration and applied voltage
65. Ch1-65
Source: Introduction to Semiconductor Physics By: Holger T. Grahn
What is Semiconductor
• A semiconductor is a solid with a finite energy gap (EG) below 4 eV,
which results in a moderate conductivity and carrier density at room
temperature.
1 eV = 1.610-19焦耳(joule)
電子通過一伏特電壓差所獲得的能量
Table. Classification of solids according to their energy gap EG and
carrier density N at room temperature.
66. Ch1-66
Crystal Structure of Solids
• Single crystal: One repeated structure
• Polycrystalline: Some repeated structures
• Amorphous: No repeated structure at all
Grain Boundary
Single crystal Polycrystalline Amorphous
69. Ch1-69
Crystal Directions and Planes
x y z
1. The intercepts: 3 2 2
2. Reciprocals: 1/3 1/2 1/2
3. Multiply by 6: 2 3 3
=> Miller indices: (233)
Miller indices
70. Ch1-70
Surface Density
Q: To calculate the surface density of atoms on a particular plane in a crystal.
surface density
72. Ch1-72
Diamond Crystal Structure
Diamond lattice
(ex. C, Si, Ge, ect)
Zincblende lattice
(ex. GaAs, InP, GaP, ZnS ect)
Zincblende lattice: Similar to diamond lattice, except that the
lattice contains two different type of atoms.
![Ch1-1
半導體元件物理
Prof. Hsin-Hui Hu
Lecture: Tue 18:30-21:10
Textbook:
[1] Donald Neamen, “Semiconductor Physics and Devices,” 4th Edition,
McGraw-Hill, 2011.
[2] S. M. Sze, M. K. Lee, “Semiconductor Devices: Physics and Technology,”
3nd Edition, Wiley, 2002
Reference:
[1] Donald Neamen, 楊賜麟譯, “半導體物理與元件”第四版
[2] S. M. Sze,曾俊元譯, “半導體元件物理與製作技術”第三版, 交大出版社
[3] Ben G. Streetman, “Solid State Electronic Devices,” 6rd Edition, Prentice
Hall, 2006
[4] S. M. Sze, “Physics of Semiconductor Devices,” 3rd Edition, Wiley, 2007](https://image.slidesharecdn.com/1-introductionandcrystalstructureofsolids-230307113220-2eb5e7b6/85/1introduction-and-crystal-structure-of-solidspdf-1-320.jpg)
