1. Study of Modified Noise-Shaper Architectures
for Oversampled Sigma-Delta DACs
Nadeem Afzal J Jacob Wikner
Department of Electrical Engineering, Department of Electrical Engineering,
Link¨ ping University, SE-581 83 Link¨ ping, Sweden
o o Link¨ ping University, SE-581 83 Link¨ ping, Sweden
o o
E-mail: nadeem@isy.liu.se E-mail: Jacob.Wikner@liu.se
Abstract—In this paper, modified low-complex, hybrid archi- results are found in Section IV. Finally, we conclude the results
tectures for digital, oversampled sigma-delta digital-to-analog and elaborate on some future extensions to the work.
converters (Σ∆DACs) are explored in terms of signal-to-noise In this paper, further exploration and modification of the
ratio (SNR) and subDAC complexity. The studied techniques
illustrate the trade-off in terms of noise-shaper and DAC im- work in [3] is done and some novel results are presented.
plementation complexity and loss in SNR. It is found that a fair
amount of improvement in SNR is achieved by maintaining low- II. S IGMA D ELTA M ODULATOR
complexity of noise shaper. The complexity of the subDAC is yet A simplified interpolation chain for digital-to-analog con-
a parameter, directly related to the number of output bits from version including a noise-shaping Σ∆ modulator is shown in
the noise shaper.
Two different architectures are investigated with respect to Fig. 1. We use a slightly unorthodox starting point to describe
subDAC complexity and noise shaper complexity. It is shown the theoretically achievable SNR in the signal path if the the
that the required number of DAC unit elements (DUE) can be noise-shaping module is omitted:
reduced to half.
Index Terms—Sigma-Delta-Modulator, Noise Shaper, DAC- SNR = log2 (DUE), (1)
Complexity, Modulator’s Complexity, Hybrid architecture.
where DUE is the required number of unit elements in the
I. I NTRODUCTION DAC [7]. For the “standard” Nyquist converter, i.e., interpo-
lation factor is 1 in the signal chain), DUE would simply be
The sigma-delta modulator (Σ∆), among many other mod- given by
ulators, attracts remarkable appreciation mainly due to the po- DUE = 2N , (2)
tential to reach high accuracy, i.e., high resolution. It achieves
high signal-to-noise ratio (SNR) by utilizing a high oversam- and the obtainable (theoretically) SNR at the input of the DAC
pling ratio (OSR), where OSR is defined as the ratio between would be
the sampling frequency and the baseband signal bandwidth. SNR = 6.02 · N + 1.76 dB. (3)
To keep OSR constant for high bandwidths applications, the
sampling frequency naturally has to be increased. An increased So, in short: for a Nyquist rate converter, to achieve high
sampling frequency is restricted, not only by the mismatches SNR, a high number of bits, N , is required implying a very
because of the process technologies but also by the increase complex DAC for high-speed applications. In the case of a
in complexity of hardware circuitry. limited bandwidth compared to the Nyquist frequency, i.e.,
In cases of wideband signals and/or lower OSR applications, oversampling is possible, the SNR can be increased by a factor
the SNR can be improved by increasing the number of output 10 · log10 (OSR) [8] implying that
bits of the noise shaper, i.e., the number of quantizer bits. SNR = 6.02 · N + 1.67 + 10 · log10 (OSR) dB. (4)
This is done at the expense of precision component mismatch
in the output digital-to-analog converter (DAC) [1]. One However, just utilizing a high OSR is not always possible
can also increase the order of the Σ∆ to further achieve since, still, high-speed architectures are required. Therefore the
better performance, but the increment in the order makes the number of bits fed to the DAC is reduced by employing the
large domain of parameters difficult to be optimized. Hence, noise shaper. It can effectively be used to maintain the same
a higher-order Σ∆ is more difficult to design in terms of SNR within the signal band eventhough the number of bits
stability [2]. Conclusively, in the low-OSR scenario, high is lower. The number of bits is reduced by re-quantization at
resolution is difficult to reach with a single-bit quantizer - coarser levels while the additional quantization noise is shifted
even with the high-order Σ∆ [4]. to frequencies outside the effective signal band. Using an ideal
Σ∆ the in-band SNR would be formulated as [9]
In Section II we describe some of the mathematical theory (2L + 1)(OSR)2L+1
behind the obtainable Σ∆ modulators. The hybrid noise- SNR = 6.02 · NQ + 10 · log10 + 1.76 dB,
π 2L
shaper architecture is described in Section III and simulation (5)
978-1-4244-8971-8/10$26.00 c 2010 IEEE

2. part XM from the input XN . In other words, XM consists
the of MSBs of XN , whereas, XL consists of the LSBs of
Digital Analog XN . The output of the modulator is multiplied by a constant
coefficient, a, and then added to the XM which was passed
↑
N NQ through unaffected. The output bits of this adder can now be
OSR ∑ DAC fed to the DAC. The second-order Σ∆, in this architecture
A1, is a so-called signal feed-back architecture with uniform
quantization, as given in [8]. Since the LSBs are processed
through the modulator, a right-shift register is employed at its
output to match the bit positions of XM and XQ . The relation
between the input and the output is given as [3]
+ + z-1 + +
- - z-1 Y = XM + aXQ , (6)
where, XM is the signal fed forward at the final adder, a has
the scalar value a ≤ 1. XQ is the output of the modulator,
Fig. 1. A simplified interpolation chain from digital to analog domain. which in the z domain can be expressed as
2 qn
XQ = XL · z −1 + 1 − z −1 · , (7)
2XM
where NQ is the number of bits in the coarse quantizer
and L is the order of the Σ∆. The gradient of shift in where qn /2XM is the new quantization noise being pushed
quantization noise with respect to frequency is dependent upon towards higher frequencies [3]. Now, from the relations given
the modulator order such that the higher the order the steeper in (6) and (7), the signal at the output is
the slope [10]. Now, we can utilize the L and NQ parameters to
achieve an SNR from (5) matching that of (4) where NQ < N . XB = (XM + a · XL ) · z −1 . (8)
However, we must also be careful to not increase the com-
From (7) it is concluded that coefficient a reduces the am-
plexity of the Σ∆ too much. For very high-speed applications
plitude of XL and qn /2XM , whereas the XM is unaffected.
the power consumption will be very high and obtainable
For very small values of XL (compared to those of XM ),
maximum speed of the modulator might be limited by word-
the quantization noise is further reduced by a while the
length, etc.
signal power mainly is preserved by XM . This signal power
In short, the output number of bits needs to be low, the
preservation combined with the reduction of quantization noise
order should be low and also the word-length in adders and
thus increases SNR. In the case when XM is not sufficiently
multipliers must be kept at a minimum. Naturally, there is
larger than XL , coefficient a not only reduces the quantization
a delicate relation between all these parameters such that
noise but also the major part of the signal power. We can
a reasonably high SNR can be obtained at reasonably high
conclude that coefficient a must be selected according to the
hardware and power costs.
following relation:
III. H YBRID A RCHITECTURE
1 if NL ≥ k
a=
A hybrid Σ∆ modulator architecture, as presented in for 1/2NM if NL < k,
example [3], reduces the number of bits in the path to the
actual noise shaper, but still achieves fairly good performance. where, NL and NM are the word lengths of XL and XM ,
There is no impact on the stability analysis, since the structure respectively. The factor k, is chosen dependent on the strength
introduces a feed-forward path rather then feed-back path. of XL and the number of quantizer bits XQ .
In this architecture, the number of input bits to the noise
shaper is reduced at the cost of some additional in-band
quantization noise. In this way the architecture in [3] decreases Input XN XM Y DAC Output
the complexity of the modulator, adders and multipliers be-
truncator + E
come smaller. However, more bits must be allocated to the -
mixed-signal DAC at the output. We simply trade the digital + a
complexity against the analog complexity. By investigating the XL XQ
modified architecture a nice set of trade-off curves is obtained
∑
illustrating these complexity trade-offs, both in terms of SNR
and DAC complexity.
The modified architecture, denoted in this report as the A1
architecture, is illustrated in Fig. 2. The modulator takes XL Fig. 2. The A1 architecture, as in [3] with reduced complexity of modulator.
as input which is obtained by subtracting the LSBs truncated

3. A. Sub DAC empirically selected as

At the output of the interpolation chain, the bits from the 11 if XQ = 1

noise shaper are fed to the DAC. For high-speed applications k = 9 if XQ = 2
the current-steering DAC architecture is chosen since it pro- 
7 if XQ = 3.

vide high efficiency and can be implemented for high speed.
Typically, the current-steering DACs are composed of unit The simulation results show that for less complex modula-
current sources where every current source corresponds to one tors, higher SNR can be achieved. The improvement of course
of the 2(∗) levels, where “(∗)” is the number of input bits to comes at some cost, which is the DAC complexity. The DUE
the DAC. Every current source, i.e. one DUE, is proved to be is related to the number of input bits and the results shown
directly related to the input bits. If NY is termed as number in Fig. 5 present a relation between SNR and the number
of bits contained in Y , reffer to the Fig. 2, then the number of DAC bits NY . With larger value of NY , higher SNR can
of output bits from the final adder are be obtained. These results also show a comparison of SNR
obtained for different values of NQ and that of the case when
NQ + 1 if NQ ≥ NM no noise shaping is done.
NY =
NM + 1 if NQ < NM , The fluctuation in the effective number of bits (ENOB)
is observed in terms of SNR. These variations, for different
where NQ is the word length of XQ . The values of NQ values of NQ , are plotted against higher complexity of the
and NM can be different depending on the quantizer in the modulator, as shown in Fig. 6. The ENOB for NQ = 3 shows
the modulator and XM , respectively. To reduce the DAC almost constant value around 14 for the DAC complexity up
complexity in architecture A1, architecture A2, as given in to 10 bits. However, for 9 and 10-bit DAC the ENOB of one-
Fig. 3, is introduced. In this architecture, the DAC E is bit quantizer is same to that of 2-bit. The trade off in terms of
replaced by B1 and B2 and the digital adder by the analog ENOB and DAC’s complexity is that: with higher complexity
one. The number of DACs is doubled, but the cumulative of DAC (or close to k value of NY ) one-bit quantizer is fair
number of required DUEs is reduced. The required numbers choice compare to that of 2-bit.
of DUE in A1 and A2 architectures are computed as Conclusively, for architecture A1, the parameter values
corresponding to NL , close to k, seem to be best in terms
2NY − 1 if A1 of trade-offs.
DUE =
2NQ + 2NM − 2 if A2. The complexity reduction in A2 compared to that of A1 in
terms of DUE is compiled in Table I. Complexity reduction of
By mathematical induction, we have that 2NY must always Σ∆ with respect to its number of input bits (NL ) are compared
be greater than 2NQ + 2NM − 1. with the required number of DUE for both the architectures
in this table. Table shows number of DUE for three values of
NQ . Also note that here one-bit DAC is considered to have 2
DUEs.
XN XM Output
+
Input DAC BW = 40MHz, L = 2, OSR = 50, A1 architecture
truncator 120
B1
+
- DAC 110
B2
XL XQ
∑ a
100
SNR[dB]
90
Fig. 3. To reduce DAC complexity, an architecture termed here as A2 which
utilizes two DACs with analog addition at the output, is introduced.
80
IV. S IMULATION R ESULTS 70 NQ = 1
NQ = 2
Some behavioral-level simulations results are presented and NQ = 3
analyzed in this section. Architecture A1 is simulated for 60
16 14 12 10 8 6 4 2 0
different word lengths and quantizers, i.e., NM , NL and NQ . Σ∆ Input bits, NL
The simulated SNR values, as shown in Fig. 4 present an Fig. 4. Comparison between SNR and modulator complexity in terms of
improvement after the k number of NL . In all of the given number of input bits.
plots, where XN consists of N = 16 bits, this factor k is

4. TABLE I
Bandwidth = 40MHz, L = 2, OSR = 50, A1 architecture
C OMPARISON BETWEEN ARCHITECTURES A1 AND A2 WITH RESPECT TO
COMPLEXITY.
110 Required DUE in A1 and A2 architectures for NQ
NQ = 1 NQ = 2 NQ = 3
100 NL A1 A2 A1 A2 A1 A2
16 2 2 4 4 8 8
15 4 4 8 6 16 10
90 14 8 6 8 8 16 12
13 16 10 16 12 16 16
SNR[dB]
80 12 32 18 32 20 32 24
11 64 34 64 36 64 40
10 128 66 128 68 128 72
70 9 256 130 256 132 256 136
8 512 258 512 260 512 264
60 7 1024 514 1024 516 1024 520
6 2048 1026 2048 1028 2048 1032
Q=3 5 4096 2050 4096 2052 4096 2056
50 Q=2 4 8192 4098 8192 4100 8192 4104
Q =1
3 16384 8194 16384 8196 16384 8200
No noise shaping
40 2 32768 16386 32768 16388 32768 16392
2 4 6 8 10 12 14 16 1 65536 32768 65536 32770 65536 32774
DAC bits, NY
Fig. 5. Comparison of SNR with increased DAC complexity and obtained
resolution provided different quantizers in the A1 architecture.
use the simulated results to select the most suitable parameter
The fluctuation of ENOB arround the complexity of DAC
15 k to trade off between hardware cost and resolution in the
NQ = 1
system.
14.5 NQ = 2
An investigation of the hardware complexity in terms of
NQ = 3
14
the number of real operations and the impact of possible
replacement of the analog adder in A2 architecture are left
13.5 for future work.
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